U.S. patent application number 15/009509 was filed with the patent office on 2016-06-09 for metalorganic chemical vapor deposition of oxide dielectrics on n-polar iii-nitride semiconductors with high interface quality and tunable fixed interface charge.
This patent application is currently assigned to THE REGENTS OF THE UNIVERSITY OF CALIFORNIA. The applicant listed for this patent is THE REGENTS OF THE UNIVERSITY OF CALIFORNIA. Invention is credited to Silvia H. Chan, Stacia Keller, Jeonghee Kim, Matthew Laurent, Xiang Liu, Jing Lu, Umesh K. Mishra, Ramya Yeluri.
Application Number | 20160163846 15/009509 |
Document ID | / |
Family ID | 53522046 |
Filed Date | 2016-06-09 |
United States Patent
Application |
20160163846 |
Kind Code |
A1 |
Liu; Xiang ; et al. |
June 9, 2016 |
METALORGANIC CHEMICAL VAPOR DEPOSITION OF OXIDE DIELECTRICS ON
N-POLAR III-NITRIDE SEMICONDUCTORS WITH HIGH INTERFACE QUALITY AND
TUNABLE FIXED INTERFACE CHARGE
Abstract
A method of fabricating a III-nitride semiconductor device,
including growing an III-nitride semiconductor and an oxide
sequentially to form an oxide/III-nitride interface, without
exposure to air in between growth of the oxide and growth of the
III-nitride semiconductor.
Inventors: |
Liu; Xiang; (Goleta, CA)
; Mishra; Umesh K.; (Montecito, CA) ; Keller;
Stacia; (Santa Barbara, CA) ; Kim; Jeonghee;
(Goleta, CA) ; Laurent; Matthew; (Santa Barbara,
CA) ; Lu; Jing; (Goleta, CA) ; Yeluri;
Ramya; (Santa Barbara, CA) ; Chan; Silvia H.;
(Santa Barbara, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA |
Oakland |
CA |
US |
|
|
Assignee: |
THE REGENTS OF THE UNIVERSITY OF
CALIFORNIA
Oakland
CA
|
Family ID: |
53522046 |
Appl. No.: |
15/009509 |
Filed: |
January 28, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14597989 |
Jan 15, 2015 |
9281183 |
|
|
15009509 |
|
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61927807 |
Jan 15, 2014 |
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Current U.S.
Class: |
257/76 ;
438/191 |
Current CPC
Class: |
H01L 21/0254 20130101;
H01L 29/7787 20130101; H01L 21/02271 20130101; H01L 21/0262
20130101; H01L 21/02178 20130101; C30B 29/406 20130101; H01L 29/517
20130101; H01L 21/28264 20130101; C30B 25/02 20130101; H01L 21/0257
20130101; H01L 29/2003 20130101; H01L 29/66462 20130101; C30B 29/20
20130101; H01L 29/7781 20130101 |
International
Class: |
H01L 29/778 20060101
H01L029/778; H01L 29/66 20060101 H01L029/66 |
Goverment Interests
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND
DEVELOPMENT
[0003] This invention was made with Government support under Grant
No. FY 2010 Multidisciplinary University Research Initiative (MUM),
Topic 7, awarded by the Office of Naval Research (ONR) under the
Dielectric Enhancements of Innovative Electronics program (orbit
Grant No. N00014-10-1-0937). The Government has certain rights in
this invention.
Claims
1. A method of fabricating a III-nitride semiconductor device,
comprising: forming a III-nitride semiconductor layer on a
substrate; and forming an oxide layer on a side of the III-nitride
semiconductor layer opposite the substrate, forming an
oxide/III-nitride interface, wherein a fixed interface charge
density at the oxide/III-nitride interface is greater than
-2.5.times.10.sup.12 cm.sup.-2.
2. The method of claim 1, wherein the oxide layer comprises
Aluminum Silicon Oxide (AlSiO).
3. The method of claim 2, wherein the oxide layer is grown without
exposure to air in between growth of the oxide layer and growth of
the III-nitride semiconductor layer.
4. The method of claim 3, wherein the growing of the oxide layer
and the III-nitride semiconductor layer is performed in-situ in a
growth reactor.
5. The method of claim 1, wherein the device is a metal oxide
semiconductor high electron mobility transistor (MOSHEMT).
6. The method of claim 5, wherein the III-nitride semiconductor
layer includes an active region of the device and the oxide layer
is between a gate of the device and the active region.
7. The method of claim 1, wherein the oxide layer and the
III-nitride semiconductor layer are grown at a temperature above
500.degree. C.
8. The method of claim 1, wherein the oxide layer and the
III-nitride semiconductor layer are grown at a temperature above
900.degree. C.
9. The method of claim 1, wherein the III-nitride semiconductor
layer is an N-polar III-nitride layer.
10. A method of fabricating a III-nitride semiconductor device,
comprising: forming a III-nitride semiconductor layer on a
substrate; and forming an oxide layer on a side of the III-nitride
semiconductor layer opposite the substrate, thereby forming an
oxide/III-nitride interface, wherein a fixed interface charge
density at the oxide/III-nitride interface is negative.
11. The method of claim 10, wherein the oxide layer comprises
Aluminum Silicon Oxide (AlSiO).
12. The method of claim 11, wherein the oxide layer is grown
without exposure to air in between growth of the oxide layer and
growth of the III-nitride semiconductor layer.
13. The method of claim 12, wherein the growing of the oxide and
III-nitride semiconductor layer is performed in-situ in a growth
reactor.
14. The method of claim 10, wherein the device is a metal oxide
semiconductor high electron mobility transistor (MOSHEMT).
15. The method of claim 14, wherein the III-nitride semiconductor
layer includes an active region of the device and the oxide layer
is between a gate of the device and the active region.
16. The method of claim 10, wherein the oxide and the III-nitride
semiconductor layer are grown at a temperature above 500.degree.
C.
17. The method of claim 10, wherein the oxide and the III-nitride
semiconductor layer are grown at a temperature above 900.degree.
C.
18. The method of claim 10, wherein the III-nitride semiconductor
layer is an N-polar III-nitride layer.
19. A semiconductor device, comprising: a III-N semiconductor layer
including an active region, the active region comprising a GaN
channel layer and an AlGaN barrier layer; an oxide layer forming an
interface with the active region; drain and source contacts
electrically coupled to the active region; and a gate deposited on
the oxide layer between the source and drain contacts, wherein the
oxide layer is Aluminum Silicon Oxide (AlSiO).
20. The device of claim 19, wherein a density of trap states at the
interface is less than 10.sup.11 cm.sup.-2.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation under 35 U.S.C. .sctn.120
of U.S. Utility patent application Ser. No. 14/597,989, filed on
Jan. 15, 2015, by Xiang Liu, Umesh K. Mishra, Stacia Keller,
Jeonghee Kim, Matthew Laurent, Jing Lu, Ramya Yeluri, and Silvia H.
Chan, entitled, "METALORGANIC CHEMICAL VAPOR DEPOSITION OF OXIDE
DIELECTRICS ON N-POLAR III-NITRIDE SEMICONDUCTORS WITH HIGH
INTERFACE QUALITY AND TUNABLE FIXED INTERFACE CHARGE" attorney's
docket number 30794.541-US-U1 (2014-449-2), which application
claims the benefit under 35 U.S.C Section 119(e) of U.S.
Provisional Patent Application Ser. No. 61/927,807 filed on Jan.
15, 2014, by Xiang Liu, Umesh K. Mishra, Stacia Keller, Jeonghee
Kim, Matthew Laurent, Jing Lu, Ramya Yeluri, and Silvia H. Chan,
entitled "METALORGANIC CHEMICAL VAPOR DEPOSITION OF OXIDE
DIELECTRICS ON N-POLAR III-NITRIDE SEMICONDUCTORS WITH HIGH
INTERFACE QUALITY AND TUNABLE FIXED INTERFACE CHARGE," attorney's
docket number 30794.541-US-P1 (2014-449-1);
[0002] all of which applications are incorporated by reference
herein.
BACKGROUND OF THE INVENTION
[0004] 1. Field of the Invention
[0005] This invention relates to method of fabricating
oxide/III-nitride interfaces.
[0006] 2. Description of the Related Art
[0007] (Note: This application references a number of different
publications as indicated throughout the specification by one or
more reference numbers within brackets, e.g., Ref. [x]. A list of
these different publications ordered according to these reference
numbers can be found below in the section entitled "References."
Each of these publications is incorporated by reference
herein.)
[0008] There is a need for improved methods for the growth of high
quality oxides and oxide/semiconductor interfaces for device
applications. In existing approaches, semiconductors are usually
grown in one chamber and then transferred to another chamber for
growth of one or more oxides. During the transfer stage, the
semiconductors are usually exposed to ambient air, and common
ambient air species, such as C, Si, as well as moisture, can build
up on one or more surfaces of the semiconductors, resulting in
contamination and formation of a native oxide layer. In order to
remove these contaminants and native oxide layers, extensive
chemical pretreatments are needed, which increases the total
processing time and may have undesired side effects that can
compromise interface quality. For example, the semiconductor
surface structure may be altered, and additional contaminants may
be introduced.
SUMMARY OF THE INVENTION
[0009] A method of fabricating a III-nitride semiconductor device,
including growing a III-nitride semiconductor and oxide
sequentially to form an oxide/III-nitride interface, without
exposure to air in between growth of the oxide and growth of the
III-nitride semiconductor.
[0010] For example, the present invention describes a novel
metalorganic chemical vapor deposition (MOCVD) in situ growth
approach to produce high quality oxides and oxide/semiconductor
interfaces for device applications. In this embodiment, the top
oxide layers and the underlying semiconductor layers are grown in
the same MOCVD reactor chamber sequentially without breaking the
vacuum, e.g., so that no chemical pretreatments are needed on the
as-grown semiconductors and the oxide/semiconductor interface is
free from ambient air contaminants and is of high quality.
[0011] As a result, the use of the in situ growth technique
produces high quality oxides and oxide/semiconductor interfaces for
device applications.
[0012] Thus, one or more embodiments of the present invention
disclose a method of fabricating a III-nitride semiconductor,
comprising forming (e.g., growing) a III-nitride semiconductor
layer (e.g., N-polar III-nitride and/or including an active region
of a device); and depositing (e.g., growing) an oxide (e.g.,
Aluminum Oxide (Al.sub.2O.sub.3)) on the III-nitride semiconductor
layer, e.g., sequentially to form an oxide/III-nitride interface
without exposure to air in between growth of the oxide and growth
of the III-nitride semiconductor. The oxide can be deposited on an
N-face of the III-nitride semiconductor layer. The growing of the
oxide and the III-nitride semiconductor layer can be performed in
situ in a growth reactor. The oxide and the III-nitride
semiconductor can be grown in separate interconnected chambers in a
growth reactor.
[0013] The oxide and III-nitride semiconductor can be grown at a
temperature above 500 degrees centigrade (.degree. C.), at a
temperature above 900.degree. C., e.g., at a temperature in a range
of 900.degree. C.-1100.degree. C.
[0014] A density of active trap states at the oxide/III-nitride
interface can be less than 10.sup.11 cm.sup.-2. Fixed interface
charge at the interface can be negative or negative. The fixed
interface charge at the interface can be greater than
-2.5.times.10.sup.12 cm.sup.-2 (e.g., in a range of
-2.5.times.10.sup.12 cm.sup.-2 to +8.9.times.10.sup.10 cm.sup.-2),
where cm is centimeters.
[0015] The method can further comprise forming contacts (e.g.,
source, drain, gate), e.g. to form a device such as a metal oxide
semiconductor high electron mobility transistor (MOSHEMT). For
example, the oxide can be between a gate of the device and the
active region.
[0016] One or more embodiments of the invention further disclose a
device, comprising an N-polar III-nitride semiconductor active
region (e.g., including an N-polar AlGaN barrier layer and an
N-polar GaN channel layer); an oxide layer (e.g., Al.sub.2O.sub.3)
forming an interface with the active region (e.g., with the N-polar
GaN channel layer); drain and source contacts electrically coupled
to the active region; and a gate deposited on the oxide layer
between the source and drain contacts; wherein a density of active
trap states at the interface is less than 10.sup.11 cm.sup.-2.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Referring now to the drawings in which like reference
numbers represent corresponding parts throughout:
[0018] FIG. 1 is a flowchart illustrating two typical processes (A
and B) of the in situ growth approach according to embodiments of
the present invention.
[0019] FIG. 2 shows Depletion (D) to Accumulation (A) (upward
arrow) and A to D (downward arrow) sweeps measured on
metal-oxide-semiconductor capacitors (MOSCAPs) with Al.sub.2O.sub.3
grown at (a) 900.degree. C. and (b) 1000.degree. C. with
Al.sub.2O.sub.3 thicknesses of 9 nanometers (nm)(red), 17 nm
(green), and 25 nm (blue), respectively, wherein the sweep
directions are indicated for the 9 nm case and remain the same for
the other thicknesses.
[0020] FIG. 3 shows measured flat band voltage V.sub.FB (solid
square) and hysteresis .DELTA.V.sub.FB (open square) versus oxide
film thickness d and the corresponding linear fits using Eq. (1)
and (2) for MOSCAPs with Al.sub.2O.sub.3 grown at (a) 900.degree.
C. and (b) 1000.degree. C., respectively.
[0021] FIG. 4 presents a schematic diagram of the gas lines and
exhausts of the Thomas Swan and Veeco MOCVD systems, wherein the
Thomas Swan MOCVD system is used for the growth of both oxides and
III-nitrides, the Veeco MOCVD system is used for the growth of
III-nitrides only, and the flow directions of the precursors,
carrier, and purge gases are controlled by the switching of 4 pairs
of normally open and normally closed valves.
[0022] FIG. 5 illustrates a possible N-polar High Electron Mobility
Transistor (HEMT) structure fabricated according to a method of the
present invention.
[0023] FIG. 6 is a flowchart illustrating a method of fabricating a
III-nitride semiconductor device.
DETAILED DESCRIPTION OF THE INVENTION
[0024] In the following description of the preferred embodiment,
reference is made to the accompanying drawings which form a part
hereof, and in which is shown by way of illustration a specific
embodiment in which the invention may be practiced. It is to be
understood that other embodiments may be utilized and structural
changes may be made without departing from the scope of the present
invention.
[0025] Technical Description
[0026] One or more embodiments of the invention describe a method
to produce a high quality interfaces with tunable fixed interface
charge between oxide dielectrics and N-polar III-nitride
semiconductors. The oxide and N-polar III-nitride are grown
sequentially by using metalorganic chemical vapor deposition
(MOCVD) in the same reactor chamber without exposing the sample to
air in between. The in situ grown oxide/N-polar III-nitride
interfaces are free from common ambient air contaminants and are of
high quality. In addition, the amount of fixed interface charge can
be controlled by varying the growth temperature of oxide
dielectrics.
[0027] The in situ growth approach is a key novel feature of this
invention, and it enables the realization of other novel properties
that are described here. The flow chart in FIG. 1 illustrates the
two typical processes (A and B) of the in situ growth approach.
[0028] Block 100 represents placing a wafer in a chamber (chamber
1) and Block 102 represents growing N-polar III-N layers in the
chamber 1.
[0029] In process A, the wafer is placed in chamber 1 for the
growth of both N-polar III-nitride and oxide layers (i.e., the
oxide layer is grown without removing the wafer from chamber 1, as
represented in Block 104a).
[0030] In process B, after the wafer is placed in chamber 1 for the
growth of N-polar III-nitride layers, the wafer is subsequently
transferred to an interconnected chamber 2 (Block 104b) for the
growth of oxide layers (as represented in Block 106). In this
latter case, the wafer is not exposed to ambient air when
transferred from chamber 1 to 2.
[0031] The present study is focused on process A using MOCVD for
the growth of both N-polar III-nitride and oxide layers. However,
it is straightforward to generalize the in situ growth approach
based on process B to include the use of multiple growth techniques
and/or multiple chambers. For example, the N-polar III-nitride
layers can be grown by MOCVD or molecular beam epitaxy (MBE), and
the oxide layers can be grown by MOCVD, MBE, atomic layer
deposition (ALD), plasma enhanced chemical vapor deposition
(PECVD), etc., all in specific but interconnected chambers.
[0032] Aluminum oxide (Al.sub.2O.sub.3) on N-polar GaN is used as
an example to demonstrate the advantages of this invention.
Al.sub.2O.sub.3 films were grown over a wide range of temperatures
from 500 degrees centigrade (.degree. C.) to 1100.degree. C., and
the present example is focused on the range from 900.degree. C. to
1000.degree. C. Such MOCVD growth temperatures are much higher than
the typical ALD growth temperatures for Al.sub.2O.sub.3, which
range from 100.degree. C. to 500.degree. C.
[0033] The in situ MOCVD growth of Al.sub.2O.sub.3 on N-polar GaN
was described in Ref. [1]. The MOCVD reactor is a modified Thomas
Swan 1.times.2'' system having a cold-wall, rotating-disk,
vertical-flow, and closed-coupled-showerhead design. The growth was
carried out at a reactor pressure of 100 Torr and a thermocouple
temperature of 1160.degree. C. The initial N-polar GaN
capacitance-voltage (C-V) structure was grown on a semi-insulating
N-polar GaN/sapphire template using trimethylgallium (TMG) and
ammonia (NH.sub.3) precursors. The bottom layer was 1500 nanometer
(nm) thick background Oxygen doped (O-doped) n.sup.+ GaN with a
carrier/electron concentration of 2.times.10.sup.18 per centimeter
cube (2.times.10.sup.18 cm.sup.-3), which was grown at a rate of 5
micrometers per hour (.mu.m/h) using 124 micromole per minute
(.mu.mol/minute) of TMG and 45 millimole per minute (mmol/minute)
(1000 standard cubic centimeters per minute (sccm)) of ammonia
(NH.sub.3). The top layer was 600 nm thick background O-doped
n.sup.- GaN with a carrier/electron concentration of
2.times.10.sup.17 cm.sup.-3, which was grown at a rate of 0.9
micrometers per hour (.mu.m/h) using 34 .mu.mol/minute of TMG and
180 mmol/minute (4000 sccm) of NH.sub.3. The Hydrogen (H.sub.2)
carrier gas flow used was 7000 and 4000 sccm during the growth of
n.sup.+ and n.sup.- GaN, respectively.
[0034] After GaN growth, the reactor temperature was ramped down
from 1160.degree. C. to 20.degree. C. over 30 minutes (min) under
NH.sub.3 and Nitrogen (N.sub.2) with flow rates of 4000 sccm. When
the temperature was reduced below 400.degree. C., the NH.sub.3 and
N.sub.2 flows were changed to 1000 and 7000 sccm, respectively. At
the end of the 30-minute (min) temperature ramp, the NH.sub.3 flow
was stopped and the N.sub.2 flow was further increased to 9000
sccm. The reactor chamber was purged with N.sub.2 for 8 min.
Afterwards, the reactor temperature was ramped up again to the
Al.sub.2O.sub.3 growth temperature of 900.degree. C. or
1000.degree. C., during which NH.sub.3 and N.sub.2 were used and
their flow rates were 2000 and 7000 sccm, respectively. When the
temperature was stabilized, the NH.sub.3 flow was stopped and the
N.sub.2 flow was increased back to 9000 sccm, and the reactor
chamber was purged with N.sub.2 for 12 seconds. Finally, three
Al.sub.2O.sub.3 films with nominal thickness of 9, 17, and 25 nm
were grown with a trimethylaluminum (TMA) flow of 1.6 .mu.mol/min
and an O.sub.2 flow of either 21.4 mmol/min (480 sccm) at
900.degree. C., or 4.5 mmol/min (100 sccm) at 1000.degree. C.
[0035] As we have described in Ref. [2], the crystallinity of
Al.sub.2O.sub.3 can be measured by using techniques such as x-ray
diffraction (XRD) and transmission electron microscopy (TEM). The
Al.sub.2O.sub.3 films grown at 900.degree. C. were polycrystalline,
while those grown at 1000.degree. C. were close to single
crystalline. And as we have described in Ref. [3], the
concentrations of common impurity species inside Al.sub.2O.sub.3,
including carbon, nitrogen, hydrogen, etc., can be measured by
using techniques such as x-ray photoelectron spectroscopy (XPS) and
atom probe tomography (APT). For example, the carbon concentrations
of the 900.degree. C. and 1000.degree. C. Al.sub.2O.sub.3 films
were determined to be 1.times.10.sup.19 cm.sup.-3 and
4.times.10.sup.19 cm.sup.-3, respectively [3].
[0036] The MOSCAP fabrication, measurement, and analysis are the
same as described in Refs. [1,4,5]. A MOSCAP structure with a 200
micrometer by 200 micrometer (200 .mu.m.times.200 .mu.m) square
gate was fabricated. Mesa isolation was performed using a
CF.sub.4/O.sub.2 based inductively coupled plasma reactive ion etch
(ICP-RIE) for Al.sub.2O.sub.3, and a subsequent BCl.sub.3/Cl.sub.2
based reactive ion etch (ME) for GaN. Ohmic contact was made on the
etch-exposed n.sup.+ GaN layer. A non-alloyed 250 nm thick
Aluminum/2500 nm thick gold (Au) metal stack was electron-beam
evaporated as both the ohmic contact metal and the gate electrode.
An Agilent 4294A Precision Impedance Analyzer was used to measure
the C-V characteristics at room temperature in dark conditions. The
signal amplitude and frequency were 50 millivolts (mV) and 1
Megahertz (MHz), respectively. The bias sweep rate was 200 mV per
second (mV/s). MOSCAPs with Al.sub.2O.sub.3 thicknesses of 9, 17,
and 25 nm were measured under different voltage bias ranges of (-8
V, 2 V), (-9 V, 3.5 V), and (-10 V, 5 V) respectively, so that the
maximum oxide electric field in accumulation and the maximum GaN
depletion width were kept approximately the same. A MOSCAP was
initially swept from depletion D to accumulation A (D to A), and
was held at accumulation for 10 min before being swept back to
depletion. It was then swept from D to A and immediately back from
accumulation to depletion (A to D) for a second time. FIGS. 2(a)
and (b) plot the representative second pairs of D to A and A to D
sweeps that were measured on MOSCAPs with Al.sub.2O.sub.3 grown at
900.degree. C. and 1000.degree. C. with thicknesses of 9 (red), 17
(green), and 25 nm (blue), respectively.
[0037] The fixed interface charge within a MOSCAP (Q.sub.I) can be
calculated from
V.sub.FB=-qQ.sub.Id/.di-elect cons..sub.0.di-elect
cons.+V.sub.FB.sup.Ideal, (1)
where V.sub.FB is the measured flat band voltage, and
V.sub.FB.sup.Ideal is the ideal flat band voltage of a charge-free
MOSCAP system. Here d is the oxide film thickness, and q is the
charge on an electron, 1.6.times.10.sup.-19 C. .di-elect
cons..sub.0 and .di-elect cons. are the vacuum permittivity and
oxide dielectric constant, respectively. When Eq. (1) is applied to
both D to A and A to D sweeps, the results can be subtracted from
each other to give the relationship between the relative changes of
V.sub.FB and Q.sub.I as
.DELTA.V.sub.FB=-q.DELTA.Q.sub.Id/.di-elect cons..sub.0.di-elect
cons., (2)
where .DELTA.V.sub.FB is the hysteresis, and .DELTA.Q.sub.I is the
density of active interface trap states. Q.sub.I and .DELTA.Q.sub.I
may be located at or a few nm away from the oxide/semiconductor
interface.
[0038] FIG. 3 plots V.sub.FB (solid square) and .DELTA.V.sub.FB
(open square) versus d for MOSCAPs with Al.sub.2O.sub.3 grown at
(a) 900.degree. C. and (b) 1000.degree. C., respectively. The
values of Q.sub.I and .DELTA.Q.sub.I are extracted by fitting the
above using Eqs. (1) and (2). The result shows that Q.sub.I and
.DELTA.Q.sub.I for MOSCAPs with Al.sub.2O.sub.3 grown at
900.degree. C. are -2.5.times.10.sup.12 cm.sup.-2 and
8.4.times.10.sup.11 cm.sup.-2, respectively. The corresponding
quantities for MOSCAPs with Al.sub.2O.sub.3 grown at 1000.degree.
C. are +8.9.times.10.sup.10 cm.sup.-2 and 6.0.times.10.sup.10
cm.sup.-2, respectively.
[0039] Reactor Examples
[0040] In one embodiment, the in situ growth is carried out inside
a Thomas Swan MOCVD reactor chamber, which has a vertical flow,
cold wall, and closed-coupled showerhead design with a 1.times.2''
sample handling capability. The reactor has a custom designed
exhaust and venting system. The oxidizers are pure O.sub.2 and
N.sub.2O gases, which are injected and controlled through custom
installed valves and mass flow controllers. The metalorganic
sources, including trimethylgallium (TMG), triethylgallium (TEG),
and trimethylalluminum (TMA), are diverted from an adjacent Veeco
Pioneer P75 GaN MOCVD system through custom designed valves and
controlling electronics. Also diverted are the N.sub.2 and H.sub.2
carrier and purge gases and the NH.sub.3 gas for GaN growth. The
oxidizers and H.sub.2 injections are valve interlocked, and only
one can be flowed at a time.
[0041] FIG. 4 shows a schematic diagram of the gas lines 400a-e and
exhausts 402a, 402b of the Thomas Swan 404 and Veeco 406 MOCVD
systems. The Thomas Swann MOCVD system 404 can be used to grow
oxides and III-nitrides and the Veeco MOCVD system 406 can be used
to grow III-nitrides. The gas lines include Group III Alkyls (TMA,
TMG) gas line 400a, Group V Hydrides (NH.sub.3) gas line 400b, gas
line 400c for oxidizers (O.sub.2, N.sub.2O) interlocked with
H.sub.2, carrier and purge line 1 (N.sub.2, H.sub.2) 400d, and
carrier and purge line 2 (N.sub.2, H.sub.2) 400e. The various gas
injection times and sequences are controlled by the Veeco computer
with an Epi View program. The growth temperature is controlled by a
programmable Eurotherm 2404 temperature controller. The growth
pressure is monitored by a MKS 122A Baratron manometer and
controlled by a MKS 651C pressure controller.
[0042] The MOCVD reactor described herein can be used to perform
high quality oxide growth on any materials and substrates that are
as-grown in the same reactor (or loaded externally) including, but
not limited to, III-nitrides with Ga- and N-polarities,
III-nitrides with polar (c-plane), semipolar, and nonpolar
orientations, materials with planar and non-planar surface
morphologies, materials with deep trenches, and patterned surface
of various kinds, etc.
[0043] In addition to the binary oxides, the MOCVD reactor
described herein can also be used to grow any combination of layers
in situ on top of group-III nitride layer structures, for example:
[0044] Tin oxide and Tin-doped Indium oxide (ITO); [0045] Ternary
[e.g., AlSiO and AlON] and multi-material oxides, and any suitable
metal oxide can be used and any suitable combination of oxide
layers in a stack can be fabricated, where Al is Aluminum, Si is
Silicon, N is Nitrogen, and O is Oxygen; [0046] Layer stacks
composed of alternating layers of ternary oxides with different
composition [e.g., repeating stacks comprising x nm thick
(Al.sub.aGa.sub.b).sub.2O.sub.3 and y nm thick
(Al.sub.cGa.sub.d).sub.2O.sub.3), i.e., n times (x nm
(Al.sub.aGa.sub.b).sub.2O.sub.3/y nm
(Al.sub.cGa.sub.d).sub.2O.sub.3), where n is an integer] [0047]
Combinations of MOCVD oxides and silicon nitride (SiN.sub.x), for
example, x nm (Al,Ga).sub.2O.sub.3+y nm SiN.sub.x (the order of the
constituents can be changed or multi-layer stacks can be
fabricated), or AlSiN; [0048] Any suitable combinations of
multi-temperature dielectrics and multi-material dielectrics, and
multi-temperature multi-material dielectrics; [0049] In situ
dielectric can be follow by growth of other ex situ dielectrics,
for example, by atomic layer deposition (ALD), chemical vapor
deposition (CVD), etc; [0050] Oxide layers that are of
semiconducting nature can be used to fabricate field effect
transistors.
[0051] The MOCVD reactor described herein can be used to grow
oxides and dielectrics with any crystallinity, including amorphous,
nanocrystalline (amorphous matrix with scattered crystalline
features on the order of nanometers), polycrystalline, and single
crystalline oxides and dielectrics, etc. The crystallinity of
oxides and dielectrics is mainly determined by the MOCVD growth
temperature, but it can also be influenced by factors such as
substrate, growth rate, film thickness, thermal anneal, and dopants
[e.g., Si], etc.
[0052] A high quality oxide/semiconductor interface can also be
obtained from this single chamber growth approach by introducing
etching reactions to an as-grown or externally transferred
semiconductor prior to oxide growth. For example, the O.sub.2
source in the MOCVD reactor can be used at elevated temperature and
low pressures to introduce active oxidation reactions for etching
[6]. Other possible etching sources include N.sub.2O, H.sub.2,
N.sub.2, NH.sub.3, HCl, and Cl-containing gases, or other halogen
containing compounds, and any material that has a corrosive nature
in its vapor phase. Etching can remove a top layer that is either
contaminated or is of sacrificial nature, and therefore generate a
better starting surface for subsequent growth.
[0053] Etching can also be used to introduce certain patterns on
selective layers at any stage of growth, which greatly opens up the
design space of many devices. For example, a top oxide layer can be
etched to induce faceting, which helps to improve the light
extraction of light emitting diodes and the light absorption of
solar cells. A semiconductor layer can also be etched to alter its
strain behavior. An etched layer can also better accommodate the
growth of another layer with a different lattice constant, since
the lattice and charge discontinuities are reduced.
[0054] The qualities of the oxides and oxide/semiconductor
interfaces can be further enhanced by using in situ thermal anneals
after dielectric(s) growth within the same reactor chamber, as we
have described in Ref [7]. For example, the amount of certain
impurities can be reduced, and certain types of defects can become
passivated [8]. Also, the density of the oxide films can be
increased. Possible ambient gases that can be used during annealing
include N.sub.2, H.sub.2, O.sub.2, N.sub.2O, NH.sub.3,
N.sub.2/H.sub.2 forming gas, etc., or any suitable combinations
that involve two or more gas species.
[0055] In one embodiment, the present invention describes the use
of a single chamber for MOCVD in situ growth of oxide dielectric(s)
on III-nitride semiconductors. However, as discussed above,
alternative embodiments may include growing group III-nitride(s)
and oxide(s) in a multi-chamber MOCVD reactor with designated
separate chambers for nitride and oxide growth. Here the growth is
also "in situ" in nature, since in such an embodiment, the sample
is transferred from the nitride chamber to the oxide chamber in
such a way that it is never exposed to air, thereby preventing any
contamination of its surface during the transfer process. The
multi-chamber approach would also eliminate any problems related to
the dissimilarity of the nitride and oxide growth processes.
[0056] MOCVD growth can be controlled by computer, and devices can
be processed, measured, and analyzed.
[0057] Device Embodiments
[0058] The oxide/N-polar III-nitride interfaces that are described
in this invention are of high quality with very low defect
densities. By taking advantage of such a high quality interface, a
device will have more efficient gate modulation, less gate charge
trapping, less threshold voltage drift, and lower gate leakage
current. Moreover, a high quality oxide/N-polar III-nitride
interface also improves the passivation of the active region of the
device, resulting in less Radio Frequency-Direct Current (RF-DC)
dispersion and better high frequency performance. In addition, the
tunable interface charge at the oxide/N-polar III-nitride
interfaces can greatly expand the design space of III-nitride
devices.
[0059] Al.sub.2O.sub.3/InAlGaN based MOSHEMT devices (e.g., N-polar
Al.sub.2O.sub.3/InAlGaN devices) could be fabricated using the one
or more embodiments of the present invention, for example. In
another example, AlGaSiO/InAlGaN based in situ devices could also
be grown and fabricated and the interface state densities and
output performances could be measured.
[0060] FIG. 5 illustrates a possible N-polar High Electron Mobility
Transistor (HEMT) structure fabricated according to an embodiment
of the present invention. The process consists of growing a N-polar
III-nitride semiconductor active region, comprising a GaN channel
layer 500 and an AlGaN back barrier layer 502, on a GaN buffer
layer 504 on a SiC substrate 506; sequentially growing an oxide
dielectric or passivation layer 508 and the GaN channel layer 500
to form an oxide/GaN interface 510 without exposure to air in
between growth of the oxide 508 and growth of the GaN channel layer
500; forming drain D and source S ohmic contacts to the active
region; and depositing a metal gate G on the oxide dielectric and
between the source and drain. Charge trapping at the interface 410
under device operation may be no more than 10.sup.10 to 10.sup.11
cm.sup.-2, for example. The AlGaN back barrier layer 502 confines a
two dimensional electron gas (2DEG) in the GaN channel layer 500.
It is straightforward to generalize the above process to the use of
different III-nitride channel/barrier/buffer/cap layers and similar
structures with Ga-polarities.
[0061] Process Steps
[0062] FIG. 6 illustrates a method of fabricating a III-nitride
semiconductor device, comprising the following steps.
[0063] Block 600 represents forming (e.g., growing) a III-nitride
semiconductor layer (e.g., including an active region of a device).
The III-nitride semiconductor layer can be an N-polar III-nitride
layer.
[0064] Block 602 represents depositing (e.g., growing) an oxide
(e.g., Aluminum Oxide (Al.sub.2O.sub.3)) on the III-nitride
semiconductor layer. The III-nitride semiconductor layer and the
oxide can be grown sequentially to form an oxide/III-nitride
interface without exposure to air in between growth of the oxide
and growth of the III-nitride semiconductor layer. The oxide can be
deposited on an N-face of the III-nitride semiconductor layer. The
growing of the oxide and the III-nitride semiconductor layer can be
performed in situ in a growth reactor. The oxide and the
III-nitride semiconductor can be grown in separate interconnected
chambers in a growth reactor.
[0065] The oxide and III-nitride semiconductor layer can be grown
at a temperature above 500.degree. C. or at a temperature above
900.degree. C., e.g., at a temperature in a range of
900-1100.degree. C.
[0066] The method can include selecting the growth temperature in
order to tune the fixed interface charge at the oxide/N-polar
III-nitride interface.
[0067] A density of trap states at the oxide/III-nitride interface
(e.g., under device operation) can be less than 10.sup.11 cm.sup.-2
(or no more than 10.sup.10 to 10.sup.11 cm.sup.-2). Fixed interface
charge at the oxide/III-nitride interface can be negative,
positive, or negligibly positive. The fixed interface charge at the
oxide/III-nitride interface can be greater than
-2.5.times.10.sup.12 cm.sup.-2 (e.g., in a range of
-2.5.times.10.sup.12 cm.sup.-2 to +8.9.times.10.sup.10
cm.sup.-2).
[0068] Block 504 represents forming contacts (e.g., source, drain,
gate) to form a device, such as a MOSHEMT. For example, the oxide
(e.g., oxide or passivation layer) can be between a gate of the
device and the active region.
[0069] The device can comprise (referring to the example of FIG. 5)
an N-polar III-nitride semiconductor active region (e.g.,
comprising an N-polar AlGaN barrier layer 502 and an N-polar GaN
channel layer 500); an oxide layer 508 forming an interface 510
with the active region (e.g, forming an interface 510 with the
N-polar GaN channel layer 500); drain D and source S contacts
electrically coupled to the active region; and a gate G deposited
on the oxide layer 508 between the source S and drain D contacts;
wherein a density of trap states at the interface 510 is less than
10.sup.11 cm.sup.-2.
[0070] The interface can achieve at least one of the following
properties: suppressed gate leakage current, improved device
stability under increasing frequency operating conditions, more
efficient gate modulation, less gate charge trapping, less
threshold voltage drift, and improved passivation of the active
region of the device resulting in less RF-DC dispersion and better
high frequency performance.
[0071] Blocks 600-602 can be performed in a reactor. One or more
embodiments of the invention further disclose an apparatus for
growth of oxide(s) and oxide/semiconductors, comprising: a reactor
for growing oxide(s) and oxide/semiconductors via MOCVD, wherein
both top oxide layers and underlying semiconductor layers are grown
in a single chamber (e.g. same chamber) of the reactor sequentially
without breaking vacuum.
[0072] Advantages and Improvements
[0073] Currently the performance of commercial III-nitride MOSHEMTs
is largely limited by the availability of proper dielectrics and
associated deposition techniques to form a high quality
dielectric/III-nitride interface, which is essential for
suppressing gate leakage current and improving device stability
under high frequency operating conditions.
[0074] The in situ MOCVD deposition approach that is used in one or
more embodiments of the present invention to form the high quality
interfaces can be easily integrated into the production of any
modern group III-nitride electronic device that utilizes the MOCVD
technology. The total growth time for the device structures can be
reduced, and the extensive chemical pretreatment steps before
dielectric depositions are no longer needed. Thus, the growth
approach of embodiments of present invention can be integrated into
the production of modern group III-nitride (Al,Ga,In)N electronic
devices to enhance yield.
[0075] The output performance of devices grown using the present
invention can be greatly enhanced due to the existence of high
quality oxide/semiconductor interfaces. The resulting devices will
have more efficient gate modulation, less gate charge trapping,
less threshold voltage drift, and less gate leakage currents. In
addition, the approach of the present invention improves the
passivation of the active region of the devices, resulting in less
RF-DC dispersion and better high frequency performance.
[0076] In one embodiment, the various defects that are located at
or near an Al.sub.2O.sub.3/N-polar GaN interface are measured on a
metal-oxide-semiconductor capacitor (MOSCAP) structure. Some of the
key results are summarized below.
[0077] (1) For in situ MOCVD grown Al.sub.2O.sub.3/N-polar GaN
interfaces with Al.sub.2O.sub.3 grown between 900.degree. C. and
1000.degree. C., the density of fast trap states and the amount of
charge trapping during device operation are both on the order of
10.sup.10 to 10.sup.11 cm.sup.-2. Such numbers are one to two
orders of magnitude smaller than those of typical
Al.sub.2O.sub.3/N-polar GaN interfaces with Al.sub.2O.sub.3 grown
by ex situ techniques, including atomic layer deposition (ALD) and
plasma enhanced chemical vapor deposition (PECVD) techniques, among
others.
[0078] (2) Surprisingly, the in situ MOCVD grown
Al.sub.2O.sub.3/N-polar GaN interface with Al.sub.2O.sub.3 grown at
900.degree. C. has a net negative fixed interface charge of
-2.5.times.10.sup.12 cm.sup.-2. This is unexpected and totally
different from the ex situ ALD grown Al.sub.2O.sub.3/N-polar GaN
interface, which has a net positive fixed interface charge that
ranges from +0.9.times.10.sup.12 to +9.2.times.10.sup.12 cm.sup.-2
[8].
[0079] (3) When the Al.sub.2O.sub.3 growth temperature changes, the
amount of fixed interface charge also becomes different. Most
notably, the in situ MOCVD grown Al.sub.2O.sub.3/N-polar GaN
interface with Al.sub.2O.sub.3 grown at 1000.degree. C. has a net
positive, but negligibly small, interface fixed charge of
+8.9.times.10.sup.10 cm.sup.-2.
[0080] Possible Modifications
[0081] One or more embodiments of the present invention can be used
to fabricate III-nitride semiconductor optoelectronic or electronic
devices (e.g., semipolar, polar, non-polar III-nitride
devices).
[0082] Thus, in addition to electronic devices, this invention can
be extended into the production of group III-nitride
optoelectronics, including, but not limited to, light emitting
diodes, laser diodes, photodetectors, and solar cells, of any
wavelength/frequency operation range. The in situ grown dielectric
layers can improve the morphology stability of group III-nitride
surfaces and prevent unintentional cracking during temperature
ramps. They can control the strain of the underlying group
III-nitride layers to produce desired output performances. They can
also potentially improve light extraction behaviors and enhance
external quantum efficiencies.
[0083] Nomenclature
[0084] GaN and its ternary and quaternary compounds incorporating
aluminum and indium (AlGaN, InGaN, AlInGaN) are commonly referred
to using the terms (Al,Ga,In)N, III-nitride, III-N, Group
III-nitride, nitride, Al.sub.(1-x-y)In.sub.yGa.sub.xN where
0<x<1 and 0<y<1, or AlInGaN, as used herein. All these
terms are intended to be equivalent and broadly construed to
include respective nitrides of the single species, Al, Ga, and In,
as well as binary, ternary and quaternary compositions of such
Group III metal species. Accordingly, these terms comprehend the
compounds AlN, GaN, and InN, as well as the ternary compounds
AlGaN, GaInN, and AlInN, and the quaternary compound AlGaInN, as
species included in such nomenclature. When two or more of the (Ga,
Al, In) component species are present, all possible compositions,
including stoichiometric proportions as well as
"off-stoichiometric" proportions (with respect to the relative mole
fractions present of each of the (Ga, Al, In) component species
that are present in the composition), can be employed within the
broad scope of the invention. Accordingly, it will be appreciated
that the discussion of the invention hereinafter in primary
reference to GaN materials is applicable to the formation of
various other (Al, Ga, In)N material species. Further, (Al,Ga,In)N
materials within the scope of the invention may further include
minor quantities of dopants and/or other impurity or inclusional
materials. Boron (B) may also be included.
[0085] One approach to eliminating the spontaneous and
piezoelectric polarization effects in GaN or III-nitride based
optoelectronic devices is to grow the III-nitride devices on
nonpolar planes of the crystal. Such planes contain equal numbers
of Ga (or group III atoms) and N atoms and are charge-neutral.
Furthermore, subsequent nonpolar layers are equivalent to one
another so the bulk crystal will not be polarized along the growth
direction. Two such families of symmetry-equivalent nonpolar planes
in GaN are the {11-20} family, known collectively as a-planes, and
the {1-100} family, known collectively as m-planes. Thus, nonpolar
III-nitride is grown along a direction perpendicular to the (0001)
c-axis of the III-nitride crystal.
[0086] Another approach to reducing polarization effects in
(Ga,Al,In,B)N devices is to grow the devices on semi-polar planes
of the crystal. The term "semi-polar plane" (also referred to as
"semipolar plane") can be used to refer to any plane that cannot be
classified as c-plane, a-plane, or m-plane. In crystallographic
terms, a semi-polar plane may include any plane that has at least
two nonzero h, i, or k Miller indices and a nonzero 1 Miller
index.
[0087] Some commonly observed examples of semi-polar planes include
the (11-22), (10-11), and (10-13) planes. Other examples of
semi-polar planes in the wurtzite crystal structure include, but
are not limited to, (10-12), (20-21), and (10-14). The nitride
crystal's polarization vector lies neither within such planes or
normal to such planes, but rather lies at some angle inclined
relative to the plane's surface normal. For example, the (10-11)
and (10-13) planes are at 62.98.degree. and 32.06.degree. to the
c-plane, respectively.
[0088] The Gallium or Ga face of GaN is the c.sup.+ or (0001)
plane, and the Nitrogen or N-face of GaN or a III-nitride layer is
the c.sup.- or (000-1) plane.
[0089] The term dielectrics comprehends oxide dielectrics and other
non-oxide dielectrics, for example, nitride dielectrics such as
Si.sub.3N.sub.4.
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CONCLUSION
[0105] This concludes the description of the preferred embodiment
of the present invention. The foregoing description of one or more
embodiments of the invention has been presented for the purposes of
illustration and description. It is not intended to be exhaustive
or to limit the invention to the precise form disclosed. Many
modifications and variations are possible in light of the above
teaching. It is intended that the scope of the invention be limited
not by this detailed description, but rather by the claims appended
hereto.
* * * * *