U.S. patent application number 14/175849 was filed with the patent office on 2015-08-13 for replacement gate compatible edram transistor with recessed channel.
This patent application is currently assigned to GLOBAL FOUNDRIES Inc.. The applicant listed for this patent is GLOBAL FOUNDRIES Inc.. Invention is credited to Peter BAARS, Frank JAKUBOWSKI, Till SCHLOESSER.
Application Number | 20150228656 14/175849 |
Document ID | / |
Family ID | 47742407 |
Filed Date | 2015-08-13 |
United States Patent
Application |
20150228656 |
Kind Code |
A1 |
SCHLOESSER; Till ; et
al. |
August 13, 2015 |
REPLACEMENT GATE COMPATIBLE eDRAM TRANSISTOR WITH RECESSED
CHANNEL
Abstract
An eDRAM is fabricated including high performance logic
transistor technology and ultra low leakage DRAM transistor
technology. Embodiments include forming a recessed channel in a
substrate, forming a first gate oxide to a first thickness lining
the channel and a second gate oxide to a second thickness over a
portion of an upper surface of the substrate, forming a first
polysilicon gate in the recessed channel and overlying the recessed
channel, forming a second polysilicon gate on the second gate
oxide, forming spacers on opposite sides of each of the first and
second polysilicon gates, removing the first and second polysilicon
gates forming first and second cavities, forming a high-k
dielectric layer on the first and second gate oxides, and forming
first and second metal gates in the first and second cavities,
respectively.
Inventors: |
SCHLOESSER; Till; (Dresden,
DE) ; BAARS; Peter; (Dresden, DE) ;
JAKUBOWSKI; Frank; (Dresden, DE) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
GLOBAL FOUNDRIES Inc. |
Grand Cayman |
|
KY |
|
|
Assignee: |
GLOBAL FOUNDRIES Inc.
Grand Cayman
KY
|
Family ID: |
47742407 |
Appl. No.: |
14/175849 |
Filed: |
February 7, 2014 |
Current U.S.
Class: |
257/334 |
Current CPC
Class: |
H01L 27/10823 20130101;
H01L 29/456 20130101; H01L 29/78 20130101; H01L 27/10894 20130101;
H01L 29/66545 20130101; H01L 29/495 20130101; H01L 27/10876
20130101; H01L 27/10897 20130101; H01L 29/66621 20130101; H01L
29/513 20130101; H01L 29/42364 20130101; H01L 29/7833 20130101;
H01L 29/7848 20130101; H01L 29/42372 20130101; H01L 29/42356
20130101; H01L 29/517 20130101; H01L 29/4236 20130101; H01L 29/4966
20130101 |
International
Class: |
H01L 27/108 20060101
H01L027/108; H01L 29/78 20060101 H01L029/78; H01L 29/49 20060101
H01L029/49; H01L 29/45 20060101 H01L029/45; H01L 29/423 20060101
H01L029/423; H01L 29/51 20060101 H01L029/51 |
Claims
1. A device comprising: a substrate; a trench in the substrate; a
first gate oxide at a first thickness lining the trench; a second
gate oxide at a second thickness over a portion of the substrate; a
high-k dielectric layer on the first and second gate oxides; a
first replacement metal gate having a first portion filling the
trench and a second portion overlying the first portion; a second
replacement metal gate over the second gate oxide; and first
spacers on opposite sides of the second portion of the first
replacement metal gate and second spacers on opposite sides of the
second replacement metal gate, wherein the first thickness differs
from the second thickness.
2. The device according to claim 1, wherein a width of the second
portion of the first replacement metal gate is less than a width of
the trench.
3. The device according to claim 2, wherein the width of the second
portion of the first replacement metal gate is 5 nm to 20 nm less
than the width of the trench.
4. The device according to claim 1, further comprising: a third
gate oxide at a third thickness over a second portion of the
substrate; a high-k dielectric layer on the third gate oxide; a
third replacement metal gate over the third gate oxide; third
spacers on opposite sides of the third replacement metal gate,
wherein the first thickness is less than the second thickness but
greater than the third thickness.
5. The device according to claim 4, wherein: the first gate oxide
has a thickness of 1 nm to 2 nm; the second gate oxide has a
thickness of 2 nm to 4 nm; and the third gate oxide has a thickness
of 0.5 nm to 1 nm.
6. The device according to claim 4, wherein the second portion of
the first replacement metal gate, the second replacement metal
gate, and the third replacement metal gate are each formed to a
height of 40 nm to 80 nm.
7. The device according to claim 4, further comprising:
source/drain extensions and source/drain implant regions in the
substrate on opposite sides of each of the first, second, and third
replacement metal gates.
8. The device according to claim 7, further comprising: a silicide
over the source/drain implant regions.
9. The device according to claim 8, further comprising an
interlayer dielectric (ILD) over the silicide and the substrate,
having an upper surface substantially coplanar with an upper
surface of the first, second, and third replacement metal
gates.
10. A device comprising: a substrate; a first transistor and a
second transistor formed on the substrate, wherein: the first
transistor comprises: a u-shaped trench in the substrate, a first
gate oxide at a first thickness lining the u-shaped trench, a first
high-k dielectric layer on the first gate oxide, a first
replacement metal gate having a first portion filling the trench
and a second portion overlying the first portion and having a first
height, and first spacers on opposite sides of the second portion
of the first replacement metal gate; and the second transistor
comprises: a second gate oxide at a second thickness, greater than
the first thickness, over a portion of the substrate, a second
high-k dielectric layer on the second gate oxide, a second
replacement metal gate over the second high-k dielectric layer and
having a second height, and second spacers on opposite sides of the
second replacement metal gate, wherein the first and second heights
are the same.
11. The device according to claim 10, wherein a width of the second
portion of the first replacement metal gate is less than a width of
the trench.
12. The device according to claim 11, wherein the width of the
second portion of the first replacement metal gate is 5 nm to 20 nm
less than the width of the trench.
13. The device according to claim 10, further comprising: a third
transistor on the substrate, the third transistor comprising: a
third gate oxide at a third thickness, less than the first
thickness, over a second portion of the substrate, a third high-k
dielectric layer on the third gate oxide, a third replacement metal
gate over the third high-k dielectric layer and having a third
height, and third spacers on opposite sides of the third
replacement metal gate, wherein the third height is the same as the
first height.
14. The device according to claim 13, wherein: the first gate oxide
has a thickness of 1 nm to 2 nm; the second gate oxide has a
thickness of 2 nm to 4 nm; and the third gate oxide has a thickness
of 0.5 nm to 1 nm.
15. The device according to claim 13, wherein the first, second,
and third heights are each 40 nm to 80 nm.
16. The device according to claim 13, further comprising:
source/drain extensions and source/drain implant regions in the
substrate on opposite sides of each of the first, second, and third
replacement metal gates.
17. The device according to claim 16, further comprising: a
silicide over the source/drain implant regions.
18. The device according to claim 17, further comprising an
interlayer dielectric (ILD) over the silicide and the substrate,
having an upper surface substantially coplanar with an upper
surface of the first, second, and third replacement metal
gates.
19. A device comprising: a substrate; a dynamic random-access
memory (DRAM) transistor, an access transistor and a logic
transistor formed on the substrate, wherein: the DRAM transistor
comprises: a u-shaped trench in the substrate, a first gate oxide
having a thickness of 1 nm to 2 nm lining the u-shaped trench, a
first high-k dielectric layer on the first gate oxide, a first
replacement metal gate having a first portion filling the trench
and a second portion overlying the first portion, and first spacers
on opposite sides of the second portion of the first replacement
metal gate; the access transistor comprises: a second gate oxide at
a thickness of 2 nm to 4 nm over a first portion of the substrate,
a second high-k dielectric layer on the second gate oxide, a second
replacement metal gate over the second high-k dielectric layer, and
second spacers on opposite sides of the second replacement metal
gate; and the logic transistor comprises: a third gate oxide having
a thickness of 0.5 nm to 1 nm over a second portion of the
substrate, a third high-k dielectric layer on the third gate oxide,
a third replacement metal gate over the third high-k dielectric
layer, and third spacers on opposite sides of the third replacement
metal gate.
20. The device according to claim 19, wherein the second portion of
the first replacement metal gate, and the second and third
replacement metal gates have first, second, and third heights,
respectively, of 40 nm to 80 nm, wherein the first, second, and
third heights are the same.
Description
CROSS-REFERENCED APPLICATION
[0001] This application is a division of U.S. application Ser. No.
13/215,635 filed Aug. 23, 2011, entirety of which is incorporated
herein by reference.
TECHNICAL FIELD
[0002] The present disclosure relates to embedded dynamic
random-access memories (eDRAMs) including recessed channel DRAMs
and replacement metal gates. The present disclosure is particularly
applicable to eDRAMs in 28 nanometer (nm) technology nodes and
beyond
BACKGROUND
[0003] The integration of hundreds of millions of circuit elements,
such as transistors, on a single integrated circuit necessitates
further dramatic scaling down or micro-miniaturization of the
physical dimensions of circuit elements, including interconnection
structures. Micro-miniaturization has engendered a dramatic
increase in transistor engineering complexity, such as the
inclusion of lightly doped drain structures, multiple implants for
source/drain regions, silicidation of gates and source/drains, and
multiple sidewall spacers, for example.
[0004] The drive for high performance requires high speed operation
of microelectronic components requiring high drive currents in
addition to low leakage, i.e., low off-state current, to reduce
power consumption. Typically, the structural and doping parameters
tending to provide a desired increase in drive current adversely
impact leakage current.
[0005] Metal gate electrodes have evolved for improving the drive
current by reducing polysilicon depletion. However, simply
replacing polysilicon gate electrodes with metal gate electrodes
may engender issues in forming the metal gate electrode prior to
high temperature annealing to activate the source/drain implants,
as at a temperature in excess of 900.degree. C. This fabrication
technique may degrade the metal gate electrode or cause interaction
with the gate dielectric, thereby adversely impacting transistor
performance.
[0006] Replacement gate techniques have been developed to address
problems attendant upon substituting metal gate electrodes for
polysilicon gate electrodes, for high performance logic for 28
nanometer (nm) technologies and beyond. For example, a polysilicon
gate is used during initial processing until high temperature
annealing to activate source/drain implants has been implemented.
Subsequently, the polysilicon is removed and replaced with a metal
gate.
[0007] In stand-alone dynamic random-access memories (DRAMs),
recessed channel transistors, e.g., u-shaped or saddle shaped
3d-transistors, have been employed for their superior retention
behavior. The recessed channel creates an enlarged effective
channel length, which in turn improves the relationship between
off-state channel leakage (I.sub.off) and gate-induced drain
leakage current. The reduced leakage current corresponds to the
static and dynamic retention characteristics of a DRAM chip,
providing longer retention time than a conventional local-damascene
FinFET.
[0008] Embedded DRAMs, or eDRAMs, integrate memory and logic on a
single chip. Since eDRAMs reduce both total chip count in a system
and also power consumption while increasing performance, they are
particularly useful for system-on-chip (SoC) designs, which may
additionally include other types of transistors, such as high
voltage transistors. However, the recessed channel transistors used
for DRAMs and the replacement gate transistors used for high
performance logic are formed by different processes.
[0009] A need therefore exists for methodology enabling combining
high performance logic transistor technology and ultra low leakage
DRAM transistor technology for embedded DRAM or system-on-chip
(SoC), and the resulting device.
SUMMARY
[0010] An aspect of the present disclosure is a method of combining
replacement metal gate technology with ultra low leakage DRAM
transistor technology.
[0011] Another aspect of the present disclosure is an eDRAM
including a recessed channel transistor and replacement metal gate
electrodes.
[0012] Additional aspects and other features of the present
disclosure will be set forth in the description which follows and
in part will be apparent to those having ordinary skill in the art
upon examination of the following or may be learned from the
practice of the present disclosure. The advantages of the present
disclosure may be realized and obtained as particularly pointed out
in the appended claims.
[0013] According to the present disclosure, some technical effects
may be achieved in part by a method including: forming a recessed
channel in a substrate; forming a first gate oxide to a first
thickness lining the channel and second gate oxide to a second
thickness over a portion of an upper surface of the substrate;
forming a first polysilicon gate having a first portion in the
recessed channel and a second portion overlying the first portion,
above the upper surface of the substrate; forming a second
polysilicon gate on the second gate oxide; forming first spacers on
opposite sides of the second portion of the first polysilicon gate
and second spacers on opposite sides of the second polysilicon
gate; removing the first and second polysilicon gates, forming
first and second cavities respectively; forming a high-k dielectric
layer on the first and second gate oxides; and forming first and
second metal gates in the first and second cavities,
respectively.
[0014] Aspects of the present disclosure include the first
thickness differing from the second thickness. Further aspects
include forming a third gate oxide to a third thickness over a
second portion of the upper surface of the substrate; forming a
third polysilicon on the third gate oxide; forming third spacers on
opposite sides of the third polysilicon gate; removing the third
polysilicon gate, forming a third cavity; forming the high-k
dielectric layer on the third gate oxide; and forming a third metal
gate in the third cavity, wherein the first thickness is less than
the second thickness, but greater than the third thickness. Another
aspect includes forming an interlayer dielectric (ILD) over the
first, second, and third polysilicon gates, the first, second, and
third spacers, and the substrate; and planarizing the ILD, gates,
and spacers to be substantially coplanar, prior to removing the
first, second, and third polysilicon gates. Additional aspects
include forming the first, second, and third polysilicon gates to a
height of 40 nanometers (nm) to 80 nm above the upper surface of
the substrate. Other aspects include forming the second portion of
the first polysilicon gate to a width less than a width of the
first portion, for example by overetching the polysilicon by 5 nm
to 20 nm. Further aspects include forming the first gate oxide to a
thickness of 1 nm to 2 nm; forming the second gate oxide to a
thickness of 2 nm to 4 nm; and forming the third gate oxide to a
thickness of 0.5 nm to 1 nm. Additional aspects include forming the
first, second, and third metal gates by: depositing a work function
metal in the first, second, and third cavities; and filling the
first, second, and third cavities with metal. Other aspects
include, prior to forming the ILD: performing source/drain
extension implants on opposite sides of each polysilicon gate;
performing source/drain implants to form source/drain regions on
opposite sides of each polysilicon gate; annealing; and forming a
silicide over the source/drain regions on opposite sides of each
polysilicon gate. Further aspects include depositing additional
gate oxide for at least one of the first, second, and third gate
oxides; and thinning the at least one gate oxide subsequent to
removing the first, second, and third polysilicon gates.
[0015] Another aspect of the present disclosure is a device
including a substrate; a recessed channel in the substrate; a first
gate oxide at a first thickness lining the recessed channel; a
second gate oxide at a second thickness over a portion of the
substrate; a high-k dielectric layer on the first and second gate
oxides; a first replacement metal gate having a first portion
filling the recessed channel and a second portion overlying the
first portion; a second replacement metal gate over the second gate
oxide; and first spacers on opposite sides of the second portion of
the first metal gate and second spacers on opposite sides of the
second metal gate, wherein the first thickness differs from the
second thickness.
[0016] Aspects include a device including a third gate oxide at a
third thickness over a second portion of the substrate; a high-k
dielectric layer on the third gate oxide; a third replacement metal
gate over the third gate oxide; third spacers on opposite sides of
the third metal gate, wherein the first thickness is less than the
second thickness but greater than the third thickness. Further
aspects include a device wherein a width of the second portion of
the first metal gate is less than a width of the recessed channel,
for example by 5 nm to 20 nm. Another aspect includes a device
wherein the second portion of the first metal gate, the second
metal gate, and the third metal gate are formed to a height of 40
nm to 80 nm. Additional aspects include a device including
source/drain extensions and source/drain regions in the substrate
on opposite sides of each polysilicon gate; and a silicide over the
source/drain implant regions. Other aspects include a device
including an interlayer dielectric (ILD) over the silicide and the
substrate, having an upper surface substantially coplanar with an
upper surface of the first, second, and third metal gates.
[0017] Additional aspects and technical effects of the present
disclosure will become readily apparent to those skilled in the art
from the following detailed description wherein embodiments of the
present disclosure are described simply by way of illustration of
the best mode contemplated to carry out the present disclosure. As
will be realized, the present disclosure is capable of other and
different embodiments, and its several details are capable of
modifications in various obvious respects, all without departing
from the present disclosure. Accordingly, the drawings and
description are to be regarded as illustrative in nature, and not
as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The present disclosure is illustrated by way of example, and
not by way of limitation, in the figures of the accompanying
drawing and in which like reference numerals refer to similar
elements and in which:
[0019] FIGS. 1A through 1G schematically illustrate a process flow
for fabricating an eDRAM, in accordance with an exemplary
embodiment.
DETAILED DESCRIPTION
[0020] In the following description, for the purposes of
explanation, numerous specific details are set forth in order to
provide a thorough understanding of exemplary embodiments. It
should be apparent, however, that exemplary embodiments may be
practiced without these specific details or with an equivalent
arrangement. In other instances, well-known structures and devices
are shown in block diagram form in order to avoid unnecessarily
obscuring exemplary embodiments. In addition, unless otherwise
indicated, all numbers expressing quantities, ratios, and numerical
properties of ingredients, reaction conditions, and so forth used
in the specification and claims are to be understood as being
modified in all instances by the term "about."
[0021] The present disclosure addresses and solves the current
problem of combining high performance logic transistor technology
and ultra low leakage DRAM transistor technology attendant upon
fabricating an eDRAM. In accordance with embodiments of the present
disclosure, a recessed channel is formed in a substrate, multiple
gate oxides are formed on the substrate and in the recessed
channel, and a replacement metal gate process is performed on each
gate oxide, with the gate formed in the recessed channel extending
above the substrate surface.
[0022] Methodology in accordance with embodiments of the present
disclosure includes: forming a recessed channel in a substrate,
forming a first gate oxide to a first thickness lining the channel
and second gate oxide to a second thickness over a portion of an
upper surface of the substrate, forming a first polysilicon gate
having a first portion in the recessed channel and a second portion
overlying the first portion, above the upper surface of the
substrate, forming a second polysilicon gate on the second gate
oxide, forming first spacers on opposite sides of the second
portion of the first polysilicon gate and second spacers on
opposite sides of the second polysilicon gate, removing the first
and second polysilicon gates, forming first and second cavities
respectively, forming a high-k dielectric layer on the first and
second gate oxides, and forming first and second metal gates in the
first and second cavities, respectively.
[0023] Still other aspects, features, and technical effects will be
readily apparent to those skilled in this art from the following
detailed description, wherein preferred embodiments are shown and
described, simply by way of illustration of the best mode
contemplated. The disclosure is capable of other and different
embodiments, and its several details are capable of modifications
in various obvious respects. Accordingly, the drawings and
description are to be regarded as illustrative in nature, and not
as restrictive.
[0024] FIGS. 1A through 1G schematically illustrate a process flow
for fabricating an eDRAM, in accordance with an exemplary
embodiment. Adverting to FIG. 1A, subsequent to a conventional
shallow trench isolation process and well and V.sub.t implants (not
shown for illustrative convenience), a recessed channel 101 is
formed in a substrate 103. The recessed channel may be formed by
lithography and etching, wherein the lithographic mask may, for
example, be a line or hole layout, depending on the DRAM layout,
and the channel may, for example, be a trench. The recessed channel
may be formed to a width of 50 nm or less. The transistor shape is
determined by etch selectivity; silicon (Si) that is selective to
silicon dioxide (SiO.sub.2) will result in a pure recessed channel
transistor, whereas a saddle shaped transistor, which is more like
a FinFET, results from a faster SiO.sub.2 etch rate.
[0025] As illustrated in FIG. 1B, multiple gate oxides 105 may be
grown or deposited over substrate 103, including in recessed
channel 101, for forming different types of transistors on the same
chip. for example, gate oxide 105a, formed in recessed channel 101,
for a DRAM transistor, may be grown or deposited to a thickness of
1 nm to 2 nm. Gate tunneling effects may occur with thicknesses
less than 1 nm, thereby degrading data retention in the memory
portion. A thick gate oxide 105b may be deposited or grown to a
thickness greater than 2 nm, for example 2 nm to 4 nm, for forming
access transistors and I/O circuitry. A thin gate oxide 105c, less
than 1 nm, for example 0.5 nm to 1 nm, may be formed by chemical
oxidation or nitridation, for high speed logic transistors.
[0026] Polysilicon may then be deposited in recessed channel 101
and over substrate 103 and then etched to form polysilicon gates
107, 109, and 111, as illustrated in FIG. 1C. The polysilicon may
optionally be predoped. Polysilicon gates 107, 109, and 111 may be
formed to a height of 40 nm to 80 nm above the surface of substrate
103. Further, the polysilicon overlying recessed channel 101 may be
overetched such that the width of the polysilicon above substrate
103 is 5 nm to 20 nm less than the width of the polysilicon in
recessed channel 101. Polysilicon gate 109 is formed on gate oxide
105b, and polysilicon gate 111 is formed on gate oxide 111.
[0027] Adverting to FIG. 1D, spacers 113 may then be formed by
conventional techniques on opposite sides of each of polysilicon
gates 107, 109, and 111. Substrate 103 may be lightly doped to form
source/drain extension (not shown for illustrative convenience) and
further doped to form source/drain regions 115 on opposite sides of
each of polysilicon gates 107, 109, and 111. The implants may be
activated by performing an anneal, for example a rapid thermal
anneal (RTA). In addition, silicon germanium (SiGe) may be applied
in the formation of the source/drain extensions for improved
stress.
[0028] As illustrated in FIG. 1E, exposed gate oxide 105 may be
removed, and a silicide 117 may be formed over source/drain regions
115. An ILD 119 may then be deposited over the entire
substrate.
[0029] ILD 119, spacers 113, and polysilicon gates 107, 109, and
111 may then be planarized, for example by chemical mechanical
polishing (CMP), as illustrated in FIG. 1F. Polysilicon gates 107,
109, and 111 are then removed by etching, for example with
tetramethylammonium hydroxide (TMAH) or by a dry/wet etching
process, forming cavities 121, 123, and 125, respectively. Gate
oxide 105a, 105b, and/or 105c may be formed to a greater thickness
than the target thickness described with respect to FIG. 1B, to act
as an etch stop when the polysilicon is etched. In that case, the
gate oxides may be thinned, carefully, subsequent to the
polysilicon removal to reach the target thicknesses.
[0030] Adverting to FIG. 1G, a high-k dielectric layer 127, for
example hafnium oxide or hafnium silicate, is deposited on gate
oxides 105a, 105b, and 105c in cavities 121, 123, and 125,
respectively. A work function metal (not shown for illustrative
convenience) is then deposited in each cavity, followed by a metal
fill, for example aluminum, to form metal electrodes 129, 131, and
133, respectively, thereby completing the replacement metal gate
process flow. The work function metal may be a dual metal, e.g.
titanium or tantalum containing with different amounts of oxygen or
nitrogen, with a lithography step and metal strip in between the
two metals. Although voids are possible in the recessed channel
transistor gate, they cause no problems so as long as the first
metal is deposited by atomic layer deposition (ALD) with good step
coverage. After another CMP, further eDRAM processing may proceed,
such with the formation of contacts, capacitors, metal lines,
etc.
[0031] The embodiments of the present disclosure can achieve
several technical effects, including high performance due to the
use of replacement metal gates and ultra low leakage due to the
recessed channel DRAM transistor. The present disclosure enjoys
industrial applicability in any of various types of highly
integrated semiconductor devices including eDRAMS and SoCs,
particularly 28 nm devices and beyond.
[0032] In the preceding description, the present disclosure is
described with reference to specifically exemplary embodiments
thereof. It will, however, be evident that various modifications
and changes may be made thereto without departing from the broader
spirit and scope of the present disclosure, as set forth in the
claims. The specification and drawings are, accordingly, to be
regarded as illustrative and not as restrictive. It is understood
that the present disclosure is capable of using various other
combinations and embodiments and is capable of any changes or
modifications within the scope of the inventive concept as
expressed herein.
* * * * *