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name:-0.07996678352356
name:-0.0064811706542969
Global Foundries Inc. Patent Filings

Global Foundries Inc.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Global Foundries Inc..The latest application filed is for "integrated switched-capacitor-based analog feed-forward equalizer circuits".

Company Profile
6.74.143
  • Global Foundries Inc. - Grand Cayman KY
  • Global Foundries Inc. - Grand Kayman KY
  • GLOBAL FOUNDRIES Inc. - George Town KY
  • Global Foundries Inc - Grand Cayman KY US
  • Global Foundries, Inc. -
  • Global Foundries, Inc. - Grand Cayman Islands KY
  • Global Foundries Inc. - Cayman Islands N/A KY
  • GLOBAL FOUNDRIES Inc. - KY KY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated Switched-Capacitor-Based Analog Feed-Forward Equalizer Circuits
App 20210021448 - Beukema; Troy James
2021-01-21
Forming replacement low-K spacer in tight pitch fin field effect transistors
Grant 10,622,457 - Cai , et al.
2020-04-14
Semiconductor device resistor structure
Grant 10,374,029 - Zang , et al.
2019-08-06
Pre-test power-optimized bin reassignment following selective voltage binning
Grant 10,295,592 - Arsovski , et al.
2019-05-21
Method and device for cooling a heat generating component
Grant 10,278,306 - Brunschwiler , et al.
2019-04-30
Vertical Fet With Self-aligned Source/drain Regions And Gate Length Based On Channel Epitaxial Growth Process
App 20180331213 - Bentley; Steven ;   et al.
2018-11-15
Fin-based diode structures with a realigned feature layout
Grant 10,096,587 - Yu , et al. October 9, 2
2018-10-09
Circuit Tuning Scheme For Fdsoi
App 20180269868 - Bellaouar; Abdellatif ;   et al.
2018-09-20
Temperature-compliant integrated circuits
Grant 9,928,335 - Johnson , et al. March 27, 2
2018-03-27
Junction butting structure using nonuniform trench shape
Grant 9,923,082 - Chou , et al. March 20, 2
2018-03-20
Bipolar junction transistors with a buried dielectric region in the active device region
Grant 9,722,057 - Camillo-Castillo , et al. August 1, 2
2017-08-01
Three-dimensional Hybrid Packaging With Through-silicon-vias And Tape-automated-bonding
App 20170200698 - Graf; Richard S. ;   et al.
2017-07-13
Method, apparatus, and system for global healing of write-limited die through bias temperature instability
Grant 9,704,600 - Gautam , et al. July 11, 2
2017-07-11
Split well zero threshold voltage field effect transistor for integrated circuits
Grant 9,666,717 - Singh , et al. May 30, 2
2017-05-30
Method to prevent lateral epitaxial growth in semiconductor devices by performing plasma nitridation process on Fin ends
Grant 9,646,885 - Pranatharthiharan , et al. May 9, 2
2017-05-09
Controlling Right-of-way For Priority Vehicles
App 20170116849 - Foreman; Eric A. ;   et al.
2017-04-27
Metal gate structure and method of formation
Grant 9,608,086 - Wei , et al. March 28, 2
2017-03-28
Preventing Leakage Inside Air-gap Spacer During Contact Formation
App 20170076978 - Cheng; Kangguo ;   et al.
2017-03-16
Preventing leakage inside air-gap spacer during contact formation
Grant 9,589,833 - Cheng , et al. March 7, 2
2017-03-07
Patterning Scheme To Minimize Dry/wets Strip Induced Device Degradation
App 20170062281 - DONG; Huihang ;   et al.
2017-03-02
Finfet Pcm Access Transistor Having Gate-wrapped Source And Drain Regions
App 20170054005 - Lam; Chung H. ;   et al.
2017-02-23
Design Of Temperature-compliant Integrated Circuits
App 20160357898 - Johnson; James M. ;   et al.
2016-12-08
Integration of electromechanical and CMOS devices in front-end-of-line using replacement metal gate process flow
Grant 9,505,611 - Liu , et al. November 29, 2
2016-11-29
Gate Contact Structure Having Gate Contact Layer
App 20160336399 - LABONTE; Andre ;   et al.
2016-11-17
Method to prevent lateral epitaxial growth in semiconductor devices by performing nitridation process on exposed Fin ends
Grant 9,496,133 - Pranatharthiharan , et al. November 15, 2
2016-11-15
Integrated circuits including selectively deposited metal capping layers on copper lines and methods for fabricating the same
Grant 9,484,252 - Chae , et al. November 1, 2
2016-11-01
Location and orientation based volume control
Grant 9,455,678 - Nguyen September 27, 2
2016-09-27
Safe distance determination
Grant 9,454,905 - Abuelsaad , et al. September 27, 2
2016-09-27
Low threshold voltage CMOS device
Grant 9,455,203 - Ando , et al. September 27, 2
2016-09-27
Pooling entropy to facilitate mobile device-based true random number generation
Grant 9,449,197 - Green , et al. September 20, 2
2016-09-20
Automatic creation, deployment, and upgrade of disk images
Grant 9,448,807 - Haug , et al. September 20, 2
2016-09-20
Optical Die Packaging
App 20160266332 - Fasano; Benjamin ;   et al.
2016-09-15
Metal-insulator-metal Capacitor Architecture
App 20160254345 - SINGH; Jagar ;   et al.
2016-09-01
Maintaining a fabric name across a distributed switch
Grant 9,426,546 - Fenkes , et al. August 23, 2
2016-08-23
Semiconductor Device Metal-Insulator-Semiconductor Contacts with Interface Layers and Methods for Forming the Same
App 20160181380 - Joshi; Amol ;   et al.
2016-06-23
Dynamic visualization for optimization processes
Grant 9,355,481 - Deshpande , et al. May 31, 2
2016-05-31
Methods, Apparatus And System For Voltage Ramp Testing
App 20160146879 - Uppal; Suresh ;   et al.
2016-05-26
Anisotropic dielectric material gate spacer for a field effect transistor
Grant 9,337,041 - Alptekin , et al. May 10, 2
2016-05-10
Low Threshold Voltage Cmos Device
App 20160126145 - Ando; Takashi ;   et al.
2016-05-05
Double self aligned via patterning
Grant 9,330,965 - Chen , et al. May 3, 2
2016-05-03
METHOD AND APPARATUS FOR QUANTIFYING DEFECTS DUE TO THROUGH SILICON VIAs IN INTEGRATED CIRCUITS
App 20160116526 - PANTISANO; Luigi ;   et al.
2016-04-28
Opposite Polarity Borderless Replacement Metal Contact Scheme
App 20160071774 - Wei; Andy Chih-Hung ;   et al.
2016-03-10
Directed Self-assembly Material Etch Mask For Forming Vertical Nanowires
App 20160071929 - Bentley; Steven ;   et al.
2016-03-10
Automated management of private information
Grant 9,280,682 - Hayato , et al. March 8, 2
2016-03-08
Gate Stack And Contact Structure
App 20160049514 - ZANG; Hui
2016-02-18
Low threshold voltage CMOS device
Grant 9,263,344 - Ando , et al. February 16, 2
2016-02-16
Double self-aligned via patterning
Grant 9,257,334 - Chen , et al. February 9, 2
2016-02-09
Methods For Fabricating Integrated Circuits Using Directed Self-assembly
App 20160027685 - Civay; Deniz Elizabeth ;   et al.
2016-01-28
Integrated Circuits With An Insultating Layer And Methods For Producing Such Integrated Circuits
App 20160013050 - Pfutzner; Ronny ;   et al.
2016-01-14
Integrated Circuits Including Modified Liners And Methods For Fabricating The Same
App 20150371898 - RYAN; ERROL TODD ;   et al.
2015-12-24
Double self aligned via patterning
Grant 9,219,007 - Chen , et al. December 22, 2
2015-12-22
Double Self-aligned Via Patterning
App 20150364372 - Chen; Hsueh-Chung ;   et al.
2015-12-17
Reduced Capacitance Interlayer Structures And Fabrication Methods
App 20150348907 - SINGH; Sunil Kumar ;   et al.
2015-12-03
Mask-aware Routing And Resulting Device
App 20150339428 - YUAN; Lei ;   et al.
2015-11-26
Semiconductor Device Configured For Avoiding Electrical Shorting
App 20150318345 - XIE; Ruilong ;   et al.
2015-11-05
Methods Of Forming Gate Structures For Transistor Devices For Cmos Applications And The Resulting Products
App 20150311206 - Hong; Zhendong ;   et al.
2015-10-29
Semiconductor fuse with enhanced post-programming resistance
Grant 9,153,534 - Kurz , et al. October 6, 2
2015-10-06
Devices and methods of forming bulk FinFETS with lateral seg for source and drain on dielectrics
Grant 9,142,673 - Liu , et al. September 22, 2
2015-09-22
Replacement low-K spacer
Grant 9,129,987 - Wan , et al. September 8, 2
2015-09-08
Integrated Circuits With Improved Contact Structures
App 20150235957 - Zhang; Xunyuan ;   et al.
2015-08-20
REPLACEMENT GATE COMPATIBLE eDRAM TRANSISTOR WITH RECESSED CHANNEL
App 20150228656 - SCHLOESSER; Till ;   et al.
2015-08-13
Conformal doping for FinFET devices
Grant 9,105,559 - Basker , et al. August 11, 2
2015-08-11
E-fuse Structure With Methods Of Fusing The Same And Monitoring Material Leakage
App 20150214149 - Moy; Dan ;   et al.
2015-07-30
Gate Structure Cut After Formation Of Epitaxial Active Regions
App 20150214219 - Cai; Xiuyu ;   et al.
2015-07-30
Threshold Voltage Tuning Using Self-aligned Contact Cap
App 20150194350 - CAI; Xiuyu Harry ;   et al.
2015-07-09
Integrated Circuits Including Selectively Deposited Metal Capping Layers On Copper Lines And Methods For Fabricating The Same
App 20150194344 - Chae; Moosung ;   et al.
2015-07-09
MOS transistor operated as OTP cell with gate dielectric operating as an e-fuse element
Grant 9,076,791 - Chi , et al. July 7, 2
2015-07-07
Methods For Fabricating Multiple-gate Integrated Circuits
App 20150187909 - Yan; Ran ;   et al.
2015-07-02
Transistor Device With Strained Layer
App 20150179740 - Triyoso; Dina H. ;   et al.
2015-06-25
Integrated circuits including epitaxially grown strain-inducing fills doped with boron for improved robustness from delimination and methods for fabricating the same
Grant 9,064,961 - Wasyluk , et al. June 23, 2
2015-06-23
Methods Of Forming Replacement Gate Structures For Semiconductor Devices And The Resulting Semiconductor Products
App 20150171216 - Xie; Ruilong ;   et al.
2015-06-18
Semiconductor Device Including A Transistor Having A Low Doped Drift Region And Method For The Formation Thereof
App 20150162439 - Hoentschel; Jan ;   et al.
2015-06-11
Method of Forming A Dielectric Film
App 20150162188 - Liu; Hung-Wei ;   et al.
2015-06-11
Methods for integration of pore stuffing material
Grant 9,054,052 - Licausi , et al. June 9, 2
2015-06-09
Methods Of Forming Spacers On Finfets And Other Semiconductor Devices
App 20150145071 - Cai; Xiuyu ;   et al.
2015-05-28
Low Threshold Voltage Cmos Device
App 20150147876 - Ando; Takashi ;   et al.
2015-05-28
Replacement metal gate structure for CMOS device
Grant 9,041,118 - Ando , et al. May 26, 2
2015-05-26
Replacement metal gate structure for CMOS device
Grant 9,040,404 - Ando , et al. May 26, 2
2015-05-26
Methods Of Forming Gate Structures For Semiconductor Devices Using A Replacement Gate Technique And The Resulting Devices
App 20150137271 - Cai; Xiuyu ;   et al.
2015-05-21
Overlay Metrology System And Method
App 20150138555 - DAI; Xintuo ;   et al.
2015-05-21
Euv Mask For Use During Euv Photolithography Processes
App 20150140477 - Singh; Mandeep
2015-05-21
Tuck Strategy In Transistor Manufacturing Flow
App 20150129933 - Lutz; Robert
2015-05-14
SRAM cell with individual electrical device threshold control
Grant 9,029,956 - Mann , et al. May 12, 2
2015-05-12
Methods For Fabricating Integrated Circuits Including Generating E-beam Patterns For Directed Self-assembly
App 20150126032 - Latypov; Azat ;   et al.
2015-05-07
Common Fill Of Gate And Source And Drain Contacts
App 20150123216 - KONDUPARTHI; Deepasree ;   et al.
2015-05-07
Preventing Epi Damage For Cap Nitride Strip Scheme In A Fin-shaped Field Effect Transistor (finfet) Device
App 20150102414 - Yu; Hong ;   et al.
2015-04-16
Integrated Circuits With Dual Silicide Contacts And Methods For Fabricating Same
App 20150091093 - Bouche; Guillaume ;   et al.
2015-04-02
Finfet Fabrication Method
App 20150093878 - Wu; Xusheng ;   et al.
2015-04-02
Methods Of Forming Finfet Semiconductor Devices Using A Replacement Gate Technique And The Resulting Devices
App 20150091100 - Xie; Ruilong ;   et al.
2015-04-02
Gate Electrode With A Shrink Spacer
App 20150091068 - Hasche; Tom ;   et al.
2015-04-02
Metal semiconductor alloy contact with low resistance
Grant 8,987,078 - Yu , et al. March 24, 2
2015-03-24
Electronic Fuse Having A Substantially Uniform Thermal Profile
App 20150076656 - Kwon; O Sung ;   et al.
2015-03-19
Through-silicon Via Unit Cell And Methods Of Use
App 20150076706 - Kamineni; Himani S. ;   et al.
2015-03-19
Enlarged Fin Tip Profile For Fins Of A Field Effect Transistor (finfet) Device
App 20150076654 - Ganz; Michael ;   et al.
2015-03-19
Test Macro For Use With A Multi-patterning Lithography Process
App 20150076498 - Yamashita; Tenko ;   et al.
2015-03-19
Methods Of Forming Finfet Semiconductor Devices With Self-aligned Contact Elements Using A Replacement Gate Process And The Resulting Devices
App 20150069532 - Xie; Ruilong ;   et al.
2015-03-12
Replacement Metal Gate Structure For Cmos Device
App 20150054087 - Ando; Takashi ;   et al.
2015-02-26
Retargeting Semiconductor Device Shapes For Multiple Patterning Processes
App 20150046887 - Sun; Yuyang ;   et al.
2015-02-12
Reduced Spacer Thickness In Semiconductor Device Fabrication
App 20150035063 - Faul; Juergen ;   et al.
2015-02-05
Wafer Support System For 3d Packaging
App 20150035140 - AGARWAL; Rahul
2015-02-05
Semiconductor Fuse With Enhanced Post-programming Resistance
App 20150034953 - KURZ; Andreas ;   et al.
2015-02-05
Integrated Circuits Having Finfet Semiconductor Devices And Methods Of Fabricating The Same To Resist Sub-fin Current Leakage
App 20150034941 - HARGROVE; Michael ;   et al.
2015-02-05
Methods Of Forming An E-fuse For An Integrated Circuit Product And The Resulting E-fuse Structure
App 20150028447 - Zhang; Xiaoqiang ;   et al.
2015-01-29
Low threshold voltage CMOS device
Grant 8,941,184 - Ando , et al. January 27, 2
2015-01-27
Fin Transformation Process And Isolation Structures Facilitating Different Fin Isolation Schemes
App 20150021690 - JACOB; Ajey Poovannummoottil ;   et al.
2015-01-22
Methods For Forming Integrated Circuits With Reduced Replacement Metal Gate Height Variability
App 20150024584 - Wells; Gabriel Padron ;   et al.
2015-01-22
Methods of self-forming barrier integration with pore stuffed ULK material
Grant 8,932,934 - Chae , et al. January 13, 2
2015-01-13
Semiconductor Structure With Improved Isolation And Method Of Fabrication To Enable Fine Pitch Transistor Arrays
App 20150001628 - LiCausi; Nicholas V. ;   et al.
2015-01-01
Forming Tunneling Field-effect Transistor With Stacking Fault And Resulting Device
App 20150001594 - LIU; Yanxiang ;   et al.
2015-01-01
Lithography Process Monitoring Of Local Interconnect Continuity
App 20140361298 - CHO; Hyun-Jin ;   et al.
2014-12-11
Wafer Carrier Purge Apparatuses, Automated Mechanical Handling Systems Including The Same, And Methods Of Handling A Wafer Carrier During Integrated Circuit Fabrication
App 20140360531 - Fosnight; William J. ;   et al.
2014-12-11
Protection Of The Gate Stack Encapsulation
App 20140353733 - Dilliway; Gabriela ;   et al.
2014-12-04
Replacement metal gate structure for CMOS device
Grant 8,895,434 - Ando , et al. November 25, 2
2014-11-25
Methods Of Forming Semiconductor Devices With Different Insulation Thicknesses On The Same Semiconductor Substrate And The Resulting Devices
App 20140339645 - Lian; Jun
2014-11-20
Computer-implemented Methods And Systems For Revision Control Of Integrated Circuit Layout Recipe Files
App 20140330786 - John; Elizabeth ;   et al.
2014-11-06
Through-silicon via with sidewall air gap
Grant 8,877,559 - Gao , et al. November 4, 2
2014-11-04
Finfet With Active Region Shaped Structures And Channel Separation
App 20140319615 - CHI; Min-Hwa ;   et al.
2014-10-30
Methods of forming trench/hole type features in a layer of material of an integrated circuit product
Grant 8,871,649 - Jang , et al. October 28, 2
2014-10-28
Method Of Forming A Dielectric Film
App 20140315385 - Liu; Hung-Wei ;   et al.
2014-10-23
Automating integrated circuit device library generation in model based metrology
Grant 8,869,081 - Saleh , et al. October 21, 2
2014-10-21
Double Patterning Via Triangular Shaped Sidewall Spacers
App 20140291735 - Shen; HongLiang ;   et al.
2014-10-02
Through-silicon Via With Sidewall Air Gap
App 20140264921 - Gao; Shan ;   et al.
2014-09-18
Semiconductor Devices Having Dielectric Caps On Contacts And Related Fabrication Methods
App 20140264499 - Yuan; Lei ;   et al.
2014-09-18
Technique For Manufacturing Semiconductor Devices Comprising Transistors With Different Threshold Voltages
App 20140273370 - Gerhardt; Martin ;   et al.
2014-09-18
Integrated Circuits And Methods For Fabricating Integrated Circuits With Gate Electrode Structure Protection
App 20140273367 - Javorka; Peter ;   et al.
2014-09-18
Method of manufacturing semiconductor devices including replacement metal gate process incorporating a conductive dummy gate layer
Grant 8,835,292 - Chudzik , et al. September 16, 2
2014-09-16
Multigate device isolation on bulk semiconductors
Grant 8,816,428 - Miller , et al. August 26, 2
2014-08-26
Methods For Fabricating Electrically-isolated Finfet Semiconductor Devices
App 20140213033 - Brunco; David P. ;   et al.
2014-07-31
Enhancing Resolution In Lithographic Processes Using High Refractive Index Fluids
App 20140211175 - Subramany; Lokesh ;   et al.
2014-07-31
Through Silicon Via Device Having Low Stress, Thin Film Gaps And Methods For Forming The Same
App 20140203446 - Liu; Huang ;   et al.
2014-07-24
Integrated Circuits And Methods Of Forming The Same With Metal Layer Connection To Through-semiconductor Via
App 20140203449 - Wong; Chun Yu ;   et al.
2014-07-24
Reticle defect correction by second exposure
Grant 8,785,112 - Hotzel July 22, 2
2014-07-22
Structure and method for forming a low gate resistance high-K metal gate transistor device
Grant 8,772,100 - Huang , et al. July 8, 2
2014-07-08
Gate Electrode(s) And Contact Structure(s), And Methods Of Fabrication Thereof
App 20140183745 - YU; Jialin ;   et al.
2014-07-03
Extreme Ultraviolet Lithography (euvl) Alternating Phase Shift Mask
App 20140170533 - Sun; Lei ;   et al.
2014-06-19
Methods Of Forming A Bi-layer Cap Layer On Copper-based Conductive Structures And Devices With Such A Cap Layer
App 20140167265 - Kioussis; Dimitri R. ;   et al.
2014-06-19
Partial Poly Amorphization For Channeling Prevention
App 20140167110 - JAVORKA; Peter ;   et al.
2014-06-19
Methods Of Forming Bulk Finfet Semiconductor Devices By Performing A Liner Recessing Process To Define Fin Heights And Finfet Devices With Such A Recessed Liner
App 20140159171 - Cai; Xiuyu ;   et al.
2014-06-12
Source And Drain Doping Using Doped Raised Source And Drain Regions
App 20140131735 - Hoentschel; Jan ;   et al.
2014-05-15
Replacement Metal Gate Structure For Cmos Device
App 20140131808 - Ando; Takashi ;   et al.
2014-05-15
Replacement Metal Gate Structure For Cmos Device
App 20140131809 - Ando; Takashi ;   et al.
2014-05-15
Scavenging metal stack for a high-K gate dielectric
Grant 8,716,088 - Ando , et al. May 6, 2
2014-05-06
FinFET formation using double patterning memorization
Grant 8,716,094 - Park , et al. May 6, 2
2014-05-06
Encapsulation Of Closely Spaced Gate Electrode Structures
App 20140077308 - Baars; Peter ;   et al.
2014-03-20
Advanced low k cap film formation process for nano electronic devices
Grant 8,664,109 - Grill , et al. March 4, 2
2014-03-04
Replacement Gate Fabrication Methods
App 20140054714 - Baars; Peter ;   et al.
2014-02-27
Method And Apparatus For Recording Status Of Shippable Goods
App 20130341403 - Uebe; Sebastian ;   et al.
2013-12-26
Soi Semiconductor Device Comprising A Substrate Diode And A Film Diode Formed By Using A Common Well Implantation Mask
App 20130334604 - Scheiper; Thilo ;   et al.
2013-12-19
Methods of selectively forming ruthenium liner layer
Grant 8,609,531 - Zhang December 17, 2
2013-12-17
Use of polarization and composite illumination source for advanced optical lithography
Grant 8,612,904 - Wang , et al. December 17, 2
2013-12-17
Double-sided semiconductor structure using through-silicon vias
Grant 8,610,281 - Nguyen , et al. December 17, 2
2013-12-17
Multilayer Interconnect Structure And Method For Integrated Circuits
App 20130313725 - Kim; Ryoung-Han
2013-11-28
Silicidation And/or Germanidation On Sige Or Ge By Cosputtering Ni And Ge And Using An Intralayer For Thermal Stability
App 20130280907 - DENIZ; Derya
2013-10-24
Removal of an overlap of dual stress liners
Grant 8,492,218 - Cai , et al. July 23, 2
2013-07-23
SOI schottky source/drain device structure to control encroachment and delamination of silicide
Grant 8,482,084 - Khater , et al. July 9, 2
2013-07-09
Strain Enhancement In Transistors Comprising An Embedded Strain-inducing Semiconductor Alloy By Creating A Patterning Non-uniformity At The Bottom Of The Gate Electrode
App 20130130449 - Kronholz; Stephan ;   et al.
2013-05-23
Semiconductor Fuse With Enhanced Post-programming Resistance
App 20130062726 - Kurz; Andreas ;   et al.
2013-03-14
Methods relating to capacitive monitoring of layer characteristics during back end-of the-line processing
Grant 8,241,927 - Choi , et al. August 14, 2
2012-08-14
Method and apparatus for reducing semiconductor package tensile stress
Grant 8,212,346 - Ryan , et al. July 3, 2
2012-07-03
Embedded Sigma-shaped Semiconductor Alloys Formed In Transistors By Applying A Uniform Oxide Layer Prior To Cavity Etching
App 20120153402 - Kronholz; Stephan ;   et al.
2012-06-21
Method of forming source and drain of field-effect-transistor and structure thereof
Grant 8,138,053 - Utomo , et al. March 20, 2
2012-03-20
Self-aligned Contact Structure Laterally Enclosed By An Isolation Structure Of A Semiconductor Device
App 20120021581 - Werner; Thomas ;   et al.
2012-01-26
Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistors
Grant 8,062,952 - Hoentschel , et al. November 22, 2
2011-11-22
Mechanism for profiling program software running on a processor
Grant 7,962,314 - Chernoff June 14, 2
2011-06-14
Stress enhanced MOS circuits
Grant 7,943,999 - Pei May 17, 2
2011-05-17
Dielectric Breakdown Lifetime Enhancement Using Alternating Current (ac) Capacitance
App 20110018565 - Yiang; Kok Yong ;   et al.
2011-01-27
Method of forming fin structures using a sacrificial etch stop layer on bulk semiconductor material
Grant 7,871,873 - Maszara , et al. January 18, 2
2011-01-18
Methods for removing a metal-comprising material from a semiconductor substrate
Grant 7,790,624 - Sharma September 7, 2
2010-09-07
Lithographic mask and methods for fabricating a semiconductor device
Grant 7,776,494 - Chen , et al. August 17, 2
2010-08-17
Redirect recovery cache that receives branch misprediction redirects and caches instructions to be dispatched in response to the redirects
Grant 7,685,410 - Shen , et al. March 23, 2
2010-03-23
Two step optical planarizing layer etch
Grant 7,601,641 - Geiss , et al. October 13, 2
2009-10-13

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