U.S. patent application number 14/151217 was filed with the patent office on 2015-07-09 for semiconductor device package with warpage control structure.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing CO., LTD.. The applicant listed for this patent is Taiwan Semiconductor Manufacturing CO., LTD.. Invention is credited to Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu, Ming-Chih Yew.
Application Number | 20150194389 14/151217 |
Document ID | / |
Family ID | 53443234 |
Filed Date | 2015-07-09 |
United States Patent
Application |
20150194389 |
Kind Code |
A1 |
Yew; Ming-Chih ; et
al. |
July 9, 2015 |
Semiconductor Device Package With Warpage Control Structure
Abstract
Between an adhesive surface of a heat spreader lid and a top
surface of a semiconductor package, in addition to a spreader
adhesive layer, several warpage control adhesive layers are also
provided. The warpage control adhesive layers are disposed on
corner areas of the adhesive surface of the heat spreader lid to
reduce high temperature warpage of the semiconductor device
package.
Inventors: |
Yew; Ming-Chih; (Hsinchu
City, TW) ; Li; Fu-Jen; (Hsinchu City, TW) ;
Lin; Po-Yao; (Zhudong Township, TW) ; Liu;
Kuo-Chuan; (Hsinchu City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing CO., LTD. |
Hsinchu |
|
TW |
|
|
Assignee: |
Taiwan Semiconductor Manufacturing
CO., LTD.
Hsinchu
TW
|
Family ID: |
53443234 |
Appl. No.: |
14/151217 |
Filed: |
January 9, 2014 |
Current U.S.
Class: |
257/704 |
Current CPC
Class: |
H01L 23/40 20130101;
H01L 2224/73253 20130101; H01L 23/562 20130101; H01L 2924/15311
20130101; H01L 2224/32225 20130101; H01L 23/36 20130101; H01L
2224/73204 20130101; H01L 2224/16225 20130101; H01L 2924/3511
20130101; H01L 23/3128 20130101; H01L 2924/0002 20130101; H01L
2924/0002 20130101; H01L 2924/00 20130101; H01L 2224/73204
20130101; H01L 2224/16225 20130101; H01L 2224/32225 20130101; H01L
2924/00 20130101; H01L 2924/15311 20130101; H01L 2224/73204
20130101; H01L 2224/16225 20130101; H01L 2224/32225 20130101; H01L
2924/00 20130101 |
International
Class: |
H01L 23/00 20060101
H01L023/00; H01L 23/367 20060101 H01L023/367 |
Claims
1. A warpage control structure of a semiconductor device package
with a heat spreader lid, the warpage control structure comprising:
a plurality of warpage control adhesive layers disposed between a
top surface of a molding layer and an adhesive surface of a heat
spreader lid as well as on plural corner areas of the adhesive
surface of the heat spreader lid, wherein the top surface of the
molding layer and the adhesive surface of the heat spreader lid are
substantial planar.
2. The warpage control structure of claim 1, wherein a spreader
adhesive layer is disposed on a central area of the adhesive
surface of the heat spreader lid.
3. The warpage control structure of claim 2, wherein the spreader
adhesive layer covers about 30% to about 80% of the adhesive
surface of the heat spreader lid.
4. The warpage control structure of claim 2, wherein the spreader
adhesive layer covers about 40% to about 75% of the adhesive
surface of the heat spreader lid.
5. The warpage control structure of claim 2, wherein the warpage
control adhesive layers are separated from the spreader adhesive
layer by a spacing of at least 1 mm.
6. The warpage control structure of claim 1, wherein an area of the
warpage control adhesive layers is from about 0.5 mm.sup.2 to about
100 mm.sup.2.
7. The warpage control structure of claim 1, wherein the warpage
control adhesive layers is made from a solder, a resin, or a
glue.
8. The warpage control structure of claim 1, wherein a shape of the
warpage control adhesive layers is circle, oval, rectangular,
donut, or an irregular shape.
9. A warpage control pattern of adhesive layers for attaching an
adhesive surface of a heat spreader lid to a top surface of a
semiconductor device package, wherein the top surface of the
semiconductor device package and the adhesive surface of the heat
spreader lid are substantial planar, the warpage control pattern
comprising: a spreader adhesive layer disposed on a central area of
the adhesive surface of the heat spreader lid; and a plurality of
warpage control adhesive layers respectively disposed on plural
corner areas of the adhesive surface of the heat spreader lid and
disposed to be separated from the spreader adhesive layer.
10. The warpage control pattern of claim 9, wherein the spreader
adhesive layer covers about 30% to about 80% of the adhesive
surface of the heat spreader lid.
11. The warpage control pattern of claim 9, wherein the spreader
adhesive layer covers about 40% to about 75% of the adhesive
surface of the heat spreader lid.
12. The warpage control pattern of claim 9, wherein the spreader
adhesive layer and the warpage control adhesive layers are
separated by at least 1 mm.
13. The warpage control pattern of claim 9, wherein an area of the
warpage control adhesive layers is from about 0.5 mm.sup.2 to about
100 mm.sup.2.
14. The warpage control pattern of claim 9, wherein the warpage
control adhesive layers is made from a solder, a resin, or a
glue.
15. A semiconductor device package with a heat spreader lid,
comprising: a substrate having a die surface and a board surface; a
die having an active circuit surface and an inactive surface,
wherein the active circuit surface of the die is electrically and
mechanically coupled to the die surface of the substrate; a molding
layer disposed to fill a space above the die surface of the
substrate, wherein the molding layer or the molding layer and the
inactive surface compose a substantial planar top surface; a heat
spreader lid disposed above the molding layer, wherein the heat
spreader lid has a substantial planar adhesive surface; a spreader
adhesive layer disposed between the substantial planar top surface
and a central area of the adhesive surface of the heat spreader
lid; and a plurality of warpage control adhesive layers disposed
between the top surface and on plural corner areas of the adhesive
surface of the heat spreader lid, wherein the warpage control
adhesive layers are separated from the spreader adhesive layer.
16. The semiconductor device package of claim 15, wherein the
warpage control adhesive layers are separated from the spreader
adhesive layer by at least 1 mm.
17. The semiconductor device package of claim 15, wherein an area
of the warpage control adhesive layers each is from about 0.5
mm.sup.2 to about 100 mm.sup.2.
18. The semiconductor device package of claim 15, wherein the
warpage control adhesive layers is made from a solder, a resin, or
a glue.
19. The semiconductor device package of claim 15, wherein the
spreader adhesive layer covers about 30% to about 80% of the
adhesive surface of the heat spreader lid.
20. The semiconductor device package of claim 15, wherein the
spreader adhesive layer covers about 40% to about 75% of the
adhesive surface of the heat spreader lid.
Description
BACKGROUND
[0001] In semiconductor device package assembly, a semiconductor
die (also referred to as an integrated circuit (IC) chip or "chip")
may be bonded directly to a packaging substrate. Such die is formed
with bumps of solder affixed to its I/O bonding pads. During
packaging, the die is "flipped" onto its front surface (e.g.,
active circuit surface) so that the solder bumps form electrical
and mechanical connections directly between the die and conductive
metal pads on the packaging substrate. Underfill is generally
applied between the gap formed by the solder bumps in order to
further secure the die to the packaging substrate. A semiconductor
device package of this type is commonly called a "flip chip
package."
[0002] In addition, a heat spreader may further attached over the
die and packaging substrate to enhance the heat dissipation ability
of the flip chip package. A problem with such a flip chip package
is that it is subject to different temperatures during the
packaging process. For instance, different temperatures arise with
the cool down from the solder joining temperature and the underfill
curing temperature. As a result, the package is highly stressed due
to the different coefficients of thermal expansion (CTE) of the
various package and die materials. The high stress experienced by
bonded materials during heating and cooling may cause them to warp
or crack and cause the package structure to bow.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0004] FIG. 1A is a top view diagram of a semiconductor device
package with a warpage control structure according some embodiments
in this disclosure.
[0005] FIGS. 1B and 1C are cross-sectional diagrams of cutting line
BC in FIG. 1A.
[0006] FIG. 2A is a table listing simulation results of warpage of
a semiconductor device package with a heat spreader lid at
260.degree. C. by finite element analysis.
[0007] FIG. 2B is a cross-sectional diagram of a warped
semiconductor device package with a crying warpage.
[0008] The drawings, schematics and diagrams are illustrative and
not intended to be limiting, but are examples of embodiments of the
disclosure, are simplified for explanatory purposes, and are not
drawn to scale.
DETAILED DESCRIPTION
[0009] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the invention. Specific examples of components and arrangements are
described below to simplify the present disclosure. These are, of
course, merely examples and are not intended to be limiting. For
example, the formation of a first feature over or on a second
feature in the description that follows may include embodiments in
which the first and second features are formed in direct contact,
and may also include embodiments in which additional features may
be formed between the first and second features, such that the
first and second features may not be in direct contact. In
addition, the present disclosure may repeat reference numerals
and/or letters in the various examples. This repetition is for the
purpose of simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
discussed.
[0010] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0011] It was found that when a flip-chip chip scale package
(fcCSP) without attaching a heat spreader lid, a smiling type
warpage of the fcCSP was occurred at a high temperature. After
attaching a heat spreader lid, the smile warpage of the fcCSP at
the high temperature was changed to crying warpage at the high
temperature, and the warpage was enlarged. Therefore, the bridging
percentage of the BGA balls at the peripheral area of the fcCSP was
increased by this enlarged crying warpage.
[0012] Accordingly, in some embodiments, a semiconductor device
package with a warpage control structure is provided in this
disclosure to reduce the high stress experienced by bonded various
materials in the semiconductor device package during cycles of
heating and cooling. FIG. 1A is a top view diagram of a
semiconductor device package with a warpage control structure
according some embodiments in this disclosure. FIG. 1B or FIG. 1C
is a cross-sectional diagram of cutting line BC in FIG. 1A.
Accordingly, FIGS. 1A-1C are referred below at the same time.
[0013] In a semiconductor device package shown FIGS. 1A-1C, a
substrate 110 has a board surface 112 and a die surface 114. On the
board surface 112 of the substrate 110, ball grid array (BGA)
connectors 116 are disposed for connecting a printed circuit board
(not shown in FIGS. 1A-1C).
[0014] In some embodiments, the substrate 110 above may be a
semiconductor wafer, or a portion of a wafer. The wafer may be
silicon, gallium arsenide, silicon on insulator ("SOT") or other
similar materials. The wafer may include passive devices such as
resistors, capacitors, inductors and the like, or active devices
such as transistors. The wafer may also include additional
integrated circuits. In some other embodiments, the substrate 110
may be made from some other materials, such as a multiple layer
circuit boards made from a bismaleimide-triazine resin (such as a
BT-epoxy resin) or glass-reinforced epoxy laminated sheets, for
example.
[0015] At least one die 120 may be disposed on the die surface 114
of the substrate 110. The die 120 has an active circuit surface 122
and an inactive surface 124. Some solder bumps 126 are disposed on
the active circuit surface 122 of the die 120. The die 120 and the
substrate 110 are electrically connected by the solder bumps
126.
[0016] The solder material of the solder bumps 126 may be lead
based or lead free, such as silver, copper, or tin-based
compositions. The material of the solder bumps 126 will be
eutectics with a common melting point for use in a reflow process.
The solder bumps 16 can be plated using electro or electroless
plating techniques, or may be formed using screening or jet
printing techniques. The solder bumps 126 also may be other types
of connectors, such as copper or gold pillars, conductive studs, or
C4 columns.
[0017] Next, an underfill 130 may be used to mechanically reinforce
the connection between the die 120 and the substrate 110. The
underfill 130 may be made from a thermoset epoxy resin, which is
dispensed into the remaining space (or "gap") between the die 120
and the substrate 110 by a capillary underfill process, for
example. The underfill 130 is then cured by heating.
[0018] In addition, a molding layer 132b in FIG. 1B can be formed
to surround the lateral side of the die 120 to further enhance the
mechanical bonding strength between the die 120 and the substrate
110 in some embodiments. In FIG. 1B, the exposed inactive surface
124 of the die 120 and the top surface 134b of the molding layer
132b compose a substantial planar top surface.
[0019] Alternatively, a molding layer 132c in FIG. 1C also can be
formed to surround the lateral side of the die 120 and cover the
inactive surface 124 of the die 120 by overmolding process to
further enhance the mechanical bonding strength between the die 120
and the substrate 110 in some other embodiments. In FIG. 1C, the
top surface 134c of the molding layer 132c is substantial
planar.
[0020] The molding layer 132b or the molding layer 132c may be made
from a composite material comprises a thermoset epoxy resin (such
as bisphenol-A epoxy or Novolac.TM. epoxy) and a filler (such as
silica, alumina or glass fillers) for adjusting a thermal expansion
coefficient and elasticity of the composite material. In some
embodiments, the content of thermoset epoxy resin may be 25-35 wt
%, and the content of the filler may be 65-73 wt %.
[0021] Furthermore, a molding underfill process may be used in some
other embodiments. Thus, the underfill 130 as well as the molding
layer 132b or the molding layer 132c may be formed by one compound
material by the molding underfill process.
[0022] A sheet of heat spreader lid 150 is further disposed on the
top surface of the semiconductor device package, i.e. the top
surface composed by the top surface 134b of the molding layer 132b
and the inactive surface 124 of the die 120 in FIG. 1B, or the top
surface 134c of the molding layer 132c in FIG. 1C. The heat
spreader lid 150 has an adhesive surface 152, which is
substantially planar and faces the top surface of the semiconductor
device package described above.
[0023] A spreader adhesive layer 140 is disposed between the top
surface of the semiconductor device package, as described above,
and the adhesive surface 152 of the heat spreader lid 150. The
spreader adhesive layer 140 is located on a central area of the
adhesive surface 152 of the heat spreader lid 150 (see FIG. 1A) to
fix the heat spreader lid 150 onto the top surface of the
semiconductor device package.
[0024] Since the spreader adhesive layer 140 is responsible to
attach the heat spreader lid 150 on to the semiconductor device
package, the coverage of the spreader adhesive layer 140 on the
adhesive surface 152 of the heat spreader lid 150 cannot be too
small. In some embodiments, the coverage of the spreader adhesive
layer 140 on the adhesive surface 152 of the heat spreader lid 150
is at least 30%. Oppositely, if the coverage of the spreader
adhesive layer 140 on the adhesive surface 152 of the heat spreader
lid 150 is too much, problems of glue overflowing and warpage may
occur. Therefore, in some embodiments, the coverage of the spreader
adhesive layer 140 on the adhesive surface 152 of the heat spreader
lid 150 may be at most 80%. Accordingly, In some embodiments, the
spreader adhesive 140 covers about 30% to about 80%, such as 30%,
35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, of the
adhesive surface 152. In some other embodiments, the spreader
adhesive 140 covers about 40% to about 80% of the adhesive surface
152. In some other embodiments, the spreader adhesive 140 covers
about 40% to about 75% of the adhesive surface 152.
[0025] In addition, several warpage control adhesive layers 142 are
disposed on corner areas of the adhesive surface 152 of the heat
spreader lid 150 (see FIG. 1A). The warpage control adhesive layers
142 are separated from the spreader adhesive layer 140 by a
distance d. In some embodiments, the distance d may be at least 1
mm. In some other embodiments, the area of the warpage control
adhesive layers 142 each may be from about 0.5 mm.sup.2 to about
100 mm.sup.2. In some other embodiments, the shape of the warpage
control adhesive layers 142 each may be any useful shapes, such as
circle, oval, rectangular, donut, or an irregular shape. In some
other embodiments, the number of the warpage control adhesive
layers 142 disposed on each corner area may be one or more. In some
other embodiments, the warpage control adhesive layers 142 may be
made from a solder, a resin, or a glue.
[0026] Some simulations were done for the pattern composed by the
spreader adhesive layer 140 and the warpage control adhesive layers
142 by finite element analysis (FEA) to predict the warpage of the
semiconductor device package with a heat spreader lid at
260.degree. C., which is a reflow temperature of the BGA balls. The
obtained results are listed in a table shown in FIG. 2A.
[0027] FIG. 2B is a cross-sectional diagram of a warped
semiconductor device package with a crying warpage. In FIG. 2B, the
warped semiconductor device package includes a substrate 210 with
BGA balls 216, a die 220 with solder bumps 226, a spreader adhesive
layer 240 and a heat spreader lid 250. The warpage w is defined by
the level difference between the highest BGA ball 216a and the
lowest BGA ball 216b. Accordingly, in the table of FIG. 2A, the
predicted warpage at 260.degree. C. of a semiconductor device
package with 100% coverage of the spreader adhesive layer (i.e.
example CE1) is normalized to 1.00.
[0028] In the table of FIG. 2, the coverage of the spreader
adhesive layer on the adhesive surface of a heat spreader lid was
varied from 100% to 50% for CE1 to CE4. Along with the decrease of
the coverage of the spreader adhesive layer 240 on the adhesive
surface of a heat spreader lid, the predicted warpage of the fcCSP
at 260.degree. C. was varied from 1.00, 1.11, 1.06, to 0.92. it
seems that the decrease of the spreader adhesive layer's coverage
can slightly decrease the warpage of the semiconductor device
package.
[0029] In examples CE5 and CE6, the coverage of the spreader
adhesive layer 240 was maintained at 50%, but the corners of the
spreader adhesive layer have some extensions 241 extending
respectively toward to the corners of the heat spreader lid. The
coverage of the extension 241 of CE6 is more than CE5, and the
predicted warpage of the CE6 is less than CE5 (0.89 v. 1.00).
[0030] Surprisingly, in examples E1 to E3, after the extensions 241
of the spreader adhesive layer 240 in examples CE5 and CE6 were
separated from the spreader adhesive layer 240 to form warpage
control adhesive layers 242, the predicted warpage can be further
decreased (0.81 to 0.87). Therefore, it can be known that the
warpage control adhesive layers, which are separated from the
spreader adhesive layer, can effectively decrease the predicted
warpage of a semiconductor device package at high temperature to
effectively decrease bridging percentage of BGA connectors of the
semiconductor device package, and the yield can thus be improved as
well.
[0031] Accordingly, in some embodiments, a warpage control
structure of a semiconductor device package with a heat spreader
lid is provided. The warpage control structure comprises a
plurality of warpage control adhesive layers disposed between a top
surface of a molding layer and an adhesive surface of a heat
spreader lid as well as on plural corner areas of the adhesive
surface of the heat spreader lid. The top surface of the molding
layer and the adhesive surface of the heat spreader lid are
substantial planar.
[0032] In some other embodiments, a warpage control pattern of
adhesive layers for attaching an adhesive surface of a heat
spreader lid to a top surface of a semiconductor device package is
provided. The top surface of the semiconductor device package and
the adhesive surface of the heat spreader lid are substantial
planar. The warpage control pattern comprises a spreader adhesive
layer disposed on a central area of the adhesive surface of the
heat spreader lid, and a plurality of warpage control adhesive
layers respectively disposed on plural corner areas of the adhesive
surface of the heat spreader lid and disposed to be separated from
the spreader adhesive layer.
[0033] In some other embodiments, a semiconductor device package
with a heat spreader lid is also provided. The semiconductor device
package comprises a substrate, a die, a molding layer, a heat
spreader lid, a spreader adhesive layer, and a plurality of warpage
control adhesive layers. The substrate has a die surface and a
board surface. The die has an active circuit surface and an
inactive surface, and the active circuit surface of the die is
electrically and mechanically coupled to the die surface of the
substrate. The molding layer is disposed to fill a space above the
die surface of the substrate. The molding layer or the molding
layer and the inactive surface compose a substantial planar top
surface. The heat spreader lid is disposed above the molding layer,
wherein the heat spreader lid has a substantial planar adhesive
surface. The spreader adhesive layer is disposed between the
substantial planar top surface and a central area of the adhesive
surface of the heat spreader lid. The warpage control adhesive
layers are disposed between the top surface and on plural corner
areas of the adhesive surface of the heat spreader lid, and the
warpage control adhesive layers are separated from the spreader
adhesive layer.
[0034] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *