U.S. patent application number 14/278006 was filed with the patent office on 2015-06-11 for intelligent chip placement within a three-dimensional chip stack.
This patent application is currently assigned to International Business Machines Corporation. The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Gerald K. Bartley, Darryl J. Becker, Philip R. Germann, William P. Hovis.
Application Number | 20150162250 14/278006 |
Document ID | / |
Family ID | 53271918 |
Filed Date | 2015-06-11 |
United States Patent
Application |
20150162250 |
Kind Code |
A1 |
Bartley; Gerald K. ; et
al. |
June 11, 2015 |
INTELLIGENT CHIP PLACEMENT WITHIN A THREE-DIMENSIONAL CHIP
STACK
Abstract
An integrated circuit (IC) stack device for thermal management
is disclosed. The IC stack device can include a primary IC having a
first set of cores with a ratio of first enabled cores and first
disabled cores. The IC stack device can also have a supplementary
IC interfaced with the primary IC, and having a second set of cores
with a second ratio of second enabled cores and second disabled
cores, with the second ratio being less than the first ratio. The
integrated circuit stack device can also include a cooling element
located such that the primary integrated circuit is between the
cooling element and the supplementary integrated circuit. The
cooling element can be designed to facilitate heat dissipation of
the first and second enabled cores of the primary integrated
circuit and the supplementary integrated circuit.
Inventors: |
Bartley; Gerald K.;
(Rochester, MN) ; Becker; Darryl J.; (Rochester,
MN) ; Germann; Philip R.; (Oronoco, MN) ;
Hovis; William P.; (Rochester, MN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
53271918 |
Appl. No.: |
14/278006 |
Filed: |
May 15, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14097585 |
Dec 5, 2013 |
|
|
|
14278006 |
|
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Current U.S.
Class: |
438/10 |
Current CPC
Class: |
H01L 24/05 20130101;
H01L 2224/131 20130101; H01L 27/0688 20130101; H01L 24/06 20130101;
H01L 2225/06541 20130101; H01L 25/0657 20130101; H01L 23/36
20130101; H01L 2924/014 20130101; H01L 24/13 20130101; H01L
2225/06589 20130101; H01L 2224/0557 20130101; H01L 2224/0401
20130101; H01L 22/20 20130101; H01L 2224/131 20130101; H01L
2224/05568 20130101; H01L 2224/16145 20130101; H01L 2225/06513
20130101; H01L 24/16 20130101; H01L 2224/06181 20130101; H01L
23/5382 20130101; H01L 23/34 20130101; H01L 23/481 20130101; H01L
2924/37001 20130101; H01L 22/14 20130101 |
International
Class: |
H01L 21/66 20060101
H01L021/66 |
Claims
1. A method of assembling an integrated circuit (IC) stack,
comprising: testing, of a plurality of wafers each having a
plurality of ICs, for factors indicative of the functionality of a
plurality of cores located on each of the plurality of ICs;
categorizing, as primary, a first subset of the plurality of wafers
based on the tested factors indicating that ICs of the first subset
are likely to have a ratio of enabled cores to disabled cores that
is greater than a threshold ratio; categorizing, as supplementary,
a second subset of the plurality of wafers based on the tested
factors indicating that ICs of the second subset are likely to have
a ratio of enabled cores to disabled cores that is less than the
threshold ratio; testing, for each IC of the plurality of ICs,
functionality of the plurality of cores located on the IC;
identifying, based on results of the testing, a subset of the
plurality of cores that have functional defects; disabling, in
response to identifying the subset of the plurality of cores, the
subset of the plurality of cores; matching a first primary IC, from
the categorized primary wafers, with a first supplementary IC, from
the categorized supplementary wafers; and assembling an IC stack of
the first primary IC, the first supplementary IC, and a cooling
element, such that the primary IC is between the cooling element
and the supplementary IC, the cooling element adapted to facilitate
heat dissipation of the enabled cores of the primary and
supplementary ICs.
2. The method of claim 1, wherein the plurality of cores include
one or more microprocessors.
3. The method of claim 1, wherein the matching further comprises
identifying the locations of the enabled cores and disabled cores
on the first primary IC and the first supplementary IC, comparing
ICs from the first subset of wafers with ICs from the second subset
of wafers, and pairing compared ICs such that the location of one
or more disabled cores of the one of the compared ICs corresponds
to the location of an enabled core on another of the compared ICs.
Description
FIELD
[0001] This disclosure relates generally to semiconductor
integrated circuit manufacturing, and more specifically to thermal
management of a 3D integrated circuit stack.
BACKGROUND
[0002] Integrated circuits created by semiconductor manufacturing
processes often contain defects, some of which may impact the
function of the integrated circuit. Some defects may render parts
of the integrated circuit unusable. Semiconductor manufacturers
seek to improve the yield of manufacturing processes by bypassing
defective portions of integrated circuits.
SUMMARY
[0003] Aspects of the present disclosure are directed toward an
integrated circuit stack device, and methods of using, that address
challenges including those discussed herein, and that are
applicable to a variety of applications. These and other aspects of
the present invention are exemplified in a number of
implementations and applications, some of which are shown in the
figures and characterized in the claims section that follows.
[0004] Aspects of the present disclosure, in certain embodiments,
are directed toward an integrated circuit stack device for thermal
management. In certain embodiments the integrated circuit stack
device can include a primary integrated circuit having a first set
of cores with a ratio of first enabled cores and first disabled
cores. The first set of cores can be located on a first side of the
primary integrated circuit. The primary integrated circuit can also
have a second side opposing the first side. In various embodiments,
the integrated circuit stack device can also have a supplementary
IC interfaced with the primary integrated circuit. The
supplementary integrated circuit can have a second set of cores
with a second ratio of second enabled cores and second disabled
cores, with the second ratio being less than the first ratio. The
second set of cores can be located on a third side of the
supplementary integrated circuit. The supplementary integrated
circuit can also have a fourth side opposing the third side.
Consistent with various embodiments, the integrated circuit stack
device can also include a cooling element located such that the
primary integrated circuit is between the cooling element and the
supplementary integrated circuit. The cooling element can be
designed to facilitate heat dissipation of the first and second
enabled cores of the primary integrated circuit and the
supplementary integrated circuit.
[0005] Aspects of the disclosure, in certain embodiments, are
directed toward a method of assembling an integrated circuit (IC)
stack. In certain embodiments, the method can include testing, of a
plurality of wafers each having a plurality of ICs, for factors
indicative of the functionality of a plurality of cores located on
each of the plurality of ICs. The method can also include
categorizing, as primary, a first subset of the plurality of wafers
based on the tested factors indicating that ICs of the first subset
are likely to have a ratio of enabled cores to disabled cores that
is greater than a threshold ratio. Consistent with various
embodiments, the method can also include categorizing, as
supplementary, a second subset of the plurality of wafers based on
the tested factors indicating that ICs of the second subset are
likely to have a ratio of enabled cores to disabled cores that is
less than the threshold ratio. The method can also include testing
of the functionality of the plurality of cores located on each IC
of the plurality of ICs. Based on the results of the testing, a
subset of the plurality of cores can be identified as having
functional defects. The method can also include disabling the
subset of the plurality of cores, in response to identifying the
subset of the plurality of cores. In certain embodiments, the
method can include matching a first primary IC from the categorized
primary wafers, with a first supplementary IC, from the categorized
supplementary wafers. Consistent with various embodiments, the
method can include assembling an IC stack of the first primary IC,
the first supplementary IC, and a cooling element, such that the
primary IC is between the cooling element and the supplementary IC.
The cooling element can be designed to facilitate heat dissipation
of the enabled cores of the primary and supplementary ICs.
[0006] Aspects of the present disclosure, in certain embodiments,
are directed toward an integrated circuit stack device for thermal
management. In certain embodiments the integrated circuit stack
device can include a supplementary integrated circuit having a
first set of cores with first enabled cores and first disabled
cores. The first set of cores can be located on a first side of the
supplementary integrated circuit. The supplementary integrated
circuit can also have a second side opposing the first side.
Consistent with various embodiments, the supplementary integrated
circuit can have a first data bus. In various embodiments, the
integrated circuit stack device can also have a primary integrated
circuit interfaced with the supplementary integrated circuit and
having a second set of cores with second enabled cores and second
disabled cores. The second set of cores can be located on a third
side of the primary integrated circuit. The primary integrated
circuit can also have a fourth side opposing the third side.
Consistent with various embodiments, the integrated circuit stack
device can also include a cooling element located such that the
primary integrated circuit is between the cooling element and the
supplementary integrated circuit. The cooling element can be
designed to facilitate heat dissipation of the first and second
enabled cores of the primary integrated circuit and the
supplementary integrated circuit.
[0007] The above summary is not intended to describe each
illustrated embodiment or every implementation of the present
disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The drawings included in the present application are
incorporated into, and form part of, the specification. They
illustrate embodiments of the present disclosure and, along with
the description, serve to explain the principles of the disclosure.
The drawings are only illustrative of certain embodiments of the
invention and do not limit the disclosure.
[0009] FIG. 1 shows a three-dimensional exploded view of a primary
integrated circuit, supplementary integrated circuit, and cooling
element, consistent with embodiments of the present disclosure
[0010] FIG. 2 shows a logical or functional representation of an IC
stack device in which the functionality of disabled cores on the
primary integrated circuit can be replaced by the functionality of
enabled cores on the supplementary integrated circuit, consistent
with embodiments of the present disclosure.
[0011] FIG. 3 shows a cross-sectional view of a primary IC and a
supplementary IC in a back-to-back orientation, consistent with
embodiments of the present disclosure.
[0012] FIG. 4 shows a cross-sectional view of a primary IC and the
supplementary IC in a front-to-front orientation, consistent with
embodiments of the present disclosure.
[0013] FIG. 5 shows a cross-sectional view of the primary IC 125
and a supplementary IC in a front-to-back orientation, consistent
with embodiments of the present disclosure.
[0014] FIG. 6 shows a cross-sectional view of a primary IC and the
supplementary IC in a back-to-front orientation, consistent with
embodiments of the present disclosure.
[0015] FIG. 7 shows a block diagram of the process of assembling a
3D integrated circuit stack device, consistent with embodiments of
the present disclosure.
[0016] While the invention is amenable to various modifications and
alternative forms, specifics thereof have been shown by way of
example in the drawings and will be described in detail. It should
be understood, however, that the intention is not to limit the
invention to the particular embodiments described. On the contrary,
the intention is to cover all modifications, equivalents, and
alternatives falling within the spirit and scope of the
invention.
DETAILED DESCRIPTION
[0017] Aspects of the present disclosure relate to various
embodiments and methods for improving yields of functional
integrated circuits, more particular aspects relate to a 3D
integrated circuit stack device designed for thermal management.
While the present invention is not necessarily limited to such
applications, various aspects of the invention may be appreciated
through a discussion of various examples using this context.
[0018] Aspects of the present disclosure relate to a 3D integrated
circuit stack device designed for thermal management, with a
primary IC, a supplementary IC, and a cooling element. In certain
embodiments, the primary IC has at least one non-functional core.
Consistent with various embodiments, the primary IC can be
interfaced with the supplementary IC and the cooling element, such
that the supplementary IC can provide functionality from a
functional core to replace that of the non-functional core on the
primary IC, and the cooling element can facilitate heat dissipation
of the IC stack device. In certain embodiments, the primary IC can
be placed higher in the stack, closer to the cooling element.
[0019] In certain instances, the primary IC's greater distance from
the power source may lead to transmitted power losses due to
increased resistance and inductance. Aspects of the present
disclosure relate to the recognition that such power losses are
acceptable with regard to the thermal management benefits
facilitated by a configuration in which the primary IC is placed
higher in the IC stack. Accordingly, such a configuration can
provide acceptable power capabilities with good thermal management
efficiency.
[0020] Consistent with embodiments of the present disclosure, the
stacking of primary and supplementary ICs can be useful for
improving production efficiency. Production efficiency is pertinent
to the success of manufacturing processes because it strongly
influences the profitability and cost of producing manufactured
goods. As a manufacturing process becomes more efficient, the
manufacturer is generally able to produce goods in less time or at
a lower cost than before the efficiency gains occurred.
[0021] In semiconductor manufacturing, yield can refer to the
fraction of functional chips or integrated circuits produced by a
manufacturing process. The product of a semiconductor manufacturing
process may be referred to as either a chip, a die, or an
integrated circuit. A chip or die can be a part of a silicon wafer
that undergoes a manufacturing process to build an integrated
circuit on the surface of the wafer. A wafer can be divided into
pieces by a process called dicing.
[0022] An integrated circuit is a circuit where the parts of the
circuit are physically connected with each other and electrically
connected. Integrated circuits built on silicon wafers can include,
as part of the circuit, areas of the wafer surface that have been
modified to have specific electrical properties. Other parts of the
circuit can be built atop this treated wafer surface as layers of
materials are added to the wafer surface. Because these added-on
components of the circuit (contacts, trenches, vias, conducting
materials, insulating materials, liners, etc. . . . ) are part of
(or integrated within) the wafer surface, the term integrated
circuit can also refer to the chip or die that contains the
integrated circuit.
[0023] Integrated circuits can be designed with one or more
functional blocks, also referred to herein as cores. Each core can
be physically located in a respective region of an integrated
circuit, and can perform an intended function in the greater
integrated circuit. A core can contain a circuit block that
actually performs the intended function as well as circuitry that
communicates data into and out of the circuit block. A core may
also contain additional circuit elements that optionally disable
the circuit block. Many modern integrated circuits contain multiple
cores of different types, including such types as central
processing units (CPUs), graphical processing units (GPUs), memory
management units (MMUs), memory controllers, input/output
controllers, optical sensors, and other specialty digital and
analog circuit components.
[0024] As semiconductor technology has advanced, the structural
features of integrated circuits have become extremely small.
Semiconductor gate structures with lateral measurements smaller
than 30 nanometers can be produced in certain manufacturing
facilities, and film thicknesses as small as a few Angstroms are
possible. While these small dimensions may not be found throughout
the semiconductor device, scaling certain parts of integrated
circuits can be useful for achieving small die sizes that will fit
more chips on a wafer.
[0025] The structure and chemical composition of a circuit's
structural elements dictate the circuit's function. If either the
structure or chemical composition is sufficiently disrupted, the
integrated circuit may not function as intended and the circuit may
need to be discarded or repaired. The small size of individual
structural elements in an integrated circuit makes them very
fragile and susceptible to damage that may disrupt the integrated
circuit's function. Such damage may be localized or widespread,
potentially rendering a circuit block, a core, or an entire
integrated circuit nonfunctional. The level of functionality
acceptable for a core or a functional block can vary depending on
the application and purpose of the integrated circuit. For example,
an integrated circuit intended for use as part of a memory
management system may have a different acceptable functionality
threshold for cores than an integrated circuit intended for use as
part of a graphical processing unit. Cores that are found to be
below the functionality threshold desired for a particular
application can be considered non-functional.
[0026] Integrated circuit defects may occur via chemical
contamination, processing errors, electrostatic discharge, or the
introduction of particles into the circuit so as to disrupt the
electrical characteristics of properly formed circuit structural
elements or to disrupt the physical structure of the circuit
itself, interfering with the circuit's proper electrical function.
For example, chemical contamination may disrupt the electrical
performance of a gate structure creating a short in the circuit.
Alternatively, when the chemical composition of photo-resist is
altered, the resist may not develop or dissolve properly, causing
disruption or destruction of the intended pattern on the silicon
wafer. Electrostatic discharge during film deposition or etching
can melt deposited metal, break insulating barriers, and scatter
particles across the wafer surface that bridge conductive areas or
block conductive lines. Processing errors may result in incomplete
etching, leaving, for example, material at the bottom of via
structures that blocks the intended conductive path through an
insulating dielectric layer. Also, particulate contamination can
block etches, fill and break conductive lines, and knock over
delicate gate structures.
[0027] These and other types of defects can be reduced by
identifying and eliminating the sources of individual defects in
order to increase total chip yield. For instance, sources of
particulate contamination can be identified and eliminated. Wafer
processing steps can also be frequently adjusted to address
chemical contamination or processing errors. The sources of the
largest particulate contaminants can be the easiest to eliminate
and the first ones selected for removal because large particles
affect larger areas of the integrated circuit. Identifying and
eliminating the sources of smaller, more widespread particles can
be a more difficult exercise than for large particles, but may
nevertheless be undertaken if the smaller particles cause
sufficient harm to the final integrated circuits. Chemical
contamination and electrostatic discharge damage may be identified
by special analytical methods before the manufacturing process can
be changed. In some circumstances, in situ defect reduction may not
be a cost effective way to completely eliminate yield problems,
requiring additional steps to improve yield.
[0028] One method of overcoming persistent defects in integrated
circuits is to design redundancy into the overall integrated
circuit by placing additional cores in the chip. When a
manufacturing process is complete, the manufacturer can test the
chips for function and partition them according to their defect
rate or performance. Fully functional chips, or at least
sufficiently functional chips, can be sold or distributed without
further treatment, while chips that have defective cores can be
subject to an in situ repair process, where defective cores are
disabled or bypassed and functional redundant cores are enabled to
provide the intended number of cores in the final integrated
circuit product. Alternatively, a sufficient number of defective
and functional cores may be disabled, providing a lesser number of
cores that will still allow for operation of the integrated circuit
at a lower performance level than originally planned for the
circuit. The use of redundant cores to overcome core-damaging
defects can add additional costs, whether in terms of physical
space on the chip or manufacturing costs. For instance, designs
with redundant cores can use additional wafer surface area per chip
and decrease the number of chips that fit on a single wafer. With
fewer chips available per wafer, a manufacturer may end up having
to produce more wafers to achieve a target number of functional
chips.
[0029] An alternative method of overcoming core-damaging defects is
to perform an ex situ repair process on defective chips by stacking
two same-type chips on top of each other and electrically
connecting parts of the two integrated circuits together.
Consistent with embodiments of the present disclosure, defective
chips from a single manufacturing process can be used to repair
each other by identifying and isolating good cores in a
supplemental chip, deactivating bad cores in a primary chip, and
linking the supplemental chip's good cores into the primary chip
integrated circuit. When ex situ repair is successful, the repaired
primary chip can perform its intended function and increases
overall manufacturing yield. Ex situ stacked chip repair can allow
manufacturers to repair integrated circuits without the need for
redundant cores, thereby reducing the size of each IC and making it
possible to fit more chips on a wafer.
[0030] Aspects of the present disclosure are directed toward
challenges related to 3D chip stacks, such as providing sufficient
thermal management. As computing requirements increase, so too do
the processing speeds and clock frequencies of integrated circuits,
which can result in an increase in power consumption. Similarly,
this increase in power consumption can lead to greater heat output.
It can be desirable for integrated circuits to be maintained within
a specified temperature range in order to avoid overheating,
instability, and component damage, which can lead to a shortened
integrated circuit lifespan. Facilitating adequate cooling for
multiple circuit layers can be more challenging than for a single
integrated circuit, as the heat generated by each integrated
circuit accumulates, resulting in a higher temperature gradient for
the chip stack. Moreover, as the stack size increases, the distance
between the active components and a heat dissipation point can
increase, leading to a reduced cooling efficiency.
[0031] Vertically oriented chip stacks can include a primary IC and
a supplementary IC, the primary IC having a higher number of
functional cores than the supplementary IC, and the supplementary
IC interfaced with the primary IC to provide replacement cores for
those that have been disabled on the primary IC. Additionally, a
cooling element can also be included in the chip stack to
facilitate heat dissipation. As the primary IC can have greater
power requirements than the supplementary IC due to its greater
number of functioning cores, its placement lower in the chip stack
results in the primary IC being located proximate to the power
source. This can be useful for reducing transmission losses (e.g.,
due to increased resistance or inductance).
[0032] Embodiments of the present disclosure relate to the
recognition that from a thermal management perspective, lower
placement of the primary IC can result in a significant heat
generator--the primary IC--being located farther from the cooling
element. For instance, placing the primary IC lower in the IC stack
can lead to the generation of excess heat and result in higher
temperature gradients for the IC stack, leading to impaired
processing efficiency, decreased stability, and shortened component
life spans. Accordingly, aspects of the present disclosure relate
to a stacking configuration which can be particularly useful for
mitigating excess heat, and improving the overall efficiency,
stability, and lifespan of the IC stack components.
[0033] Aspects of the present disclosure relate to a 3D integrated
circuit stack device designed for thermal management and heat
distribution. For instance, embodiments of the present disclosure
are directed toward a 3D integrated circuit stack in which a
primary IC having one or more non-functional cores can be
interfaced with a cooling element and with a supplementary IC to
provide replacement cores, such that the primary IC can be located
between the supplementary IC and the cooling element. Consistent
with various embodiments, the primary IC and the supplementary IC
can both be full-size die. In certain embodiments, the primary IC
and the supplementary IC can be arranged in a front-to-front
stacking configuration. In certain embodiments, the primary IC and
the supplementary IC can be arranged in a front-to-back stacking
configuration. In certain embodiments, the primary IC and the
supplementary IC can be arranged in a back-to-back stacking
configuration.
[0034] Consistent with various embodiments, the primary IC can have
a first set of cores, including enabled cores and disabled cores,
located on a surface of the primary IC. Similarly, the
supplementary IC can have a second set of cores, including enabled
cores and disabled cores, located on a surface of the supplementary
IC. The first set of cores and the second set of cores can include
a variety of types of circuit components, such as central
processing units (CPUs), graphical processing units (GPUs), memory
management units (MMUs), memory controllers, input/output
controllers, optical sensors, and other specialty digital and
analog circuit components.
[0035] Consistent with various embodiments, the cooling element can
be an active or passive component capable of facilitating heat
dissipation of the IC stack. For example, in certain embodiments,
the cooling element can include one or more passive cooling
components such as a heat sink. In certain embodiments, the cooling
element can include one or more active cooling components such as a
fan or liquid cooling delivery system or device.
[0036] Consistent with various embodiments, the primary IC and the
supplementary IC can be equipped with on-chip communication
networks, enabling a variety of connections to other components
such as other chips in the IC stack, devices external to the IC
stack, and power supplies. Further, the primary IC and the
secondary IC can each include a data bus that allows for
communication between cores located on a respective integrated
circuit. Once integrated circuits have been designated as primary
ICs and supplementary ICs in the manufacturing process, the IC
stack device can be connected and configured such that the data bus
on the primary IC functions as an active data bus for all cores on
both the primary IC and the supplementary IC. For example, in
certain embodiments, the data bus on the primary IC can be utilized
to facilitate the routing of information between the cores on one
chip in the IC stack and cores on other chips in the IC stack.
[0037] In various embodiments, the communication networks of the
primary IC and the supplementary IC can include on-chip logical
elements to replace the functionality of disabled cores on the
primary IC with enabled cores from the supplementary IC. In certain
embodiments, the logical elements can include a multiplexer block
configured to route communication between a core on an IC and one
or more data buses that can be connected to other cores, thereby
allowing communication between cores. In certain embodiments, the
multiplexer block can be configured to selectively route signals
between the data bus on the primary IC and cores on either the
primary IC or the supplementary IC. The signal selection can be
based upon the functional state of the cores. For instance, in
certain embodiments, an enabled core on the supplementary IC can
send communication signals through the multiplexer block on the
primary IC, which can route these signals to the data bus in place
of the signal from a disabled core on the primary IC. Control
signals for the multiplexer blocks (e.g., signals to control the
activation or deactivation of cores) can be sent from the
respective IC on which the multiplexer block is located.
[0038] In certain embodiments, the primary IC and the supplementary
IC can be arranged in a variety of configurations. Integrated
circuits have two surfaces that are pertinent to describing certain
configurations mentioned in the present disclosure: an active
device surface on which the components critical to the IC's
function are located, and a die substrate surface opposing the
active device surface. Consistent with various embodiments, the
primary IC and the supplementary IC can be arranged such that the
active device surface (front) of the primary IC can be interfaced
with the front of the supplementary IC. In certain embodiments, the
primary IC and the supplementary IC can be arranged such that the
front of the primary IC can be interfaced with the die substrate
surface (back) of the supplementary IC. Further, in certain
embodiments, the primary IC and the supplementary IC can be
arranged such that the back of the primary IC can be interfaced
with the front of the supplementary IC. In certain embodiments, the
primary IC and the supplementary IC can be arranged such that the
back of the primary IC can be interfaced with the back of the
supplementary IC. Accordingly, the orientation of the primary IC
and the supplementary IC can be varied to meet the needs of a
variety of applications.
[0039] In various embodiments, the orientation of the primary IC
and the supplementary IC may result in cores of the supplementary
IC being located at a greater distance from the primary data bus.
For instance, consistent with various embodiments, the primary IC
and the supplementary IC may be oriented in a front-to-back
stacking configuration, in which case the die substrate layer of
one of the chips may separate the primary data bus from the cores
of the supplementary IC. Accordingly, aspects of the present
disclosure are directed toward a 3D IC stack device that includes
one or more through-silicon vias (TSVs) that enable power delivery
and communication between the primary IC and the supplementary IC
in a variety of stacking configurations. For instance, in certain
embodiments, the signal from one or more functional cores on the
supplementary IC can be carried by a TSV connection to the
multiplexer block on the primary IC. Such configurations can be
particularly useful when the primary IC and the supplementary IC
are oriented in a front-to-back or back-to-back stacking
configuration.
[0040] In certain embodiments, power is supplied to the IC stack
device via a power source located below the cooling element,
primary IC, and supplementary IC in the IC stack. In certain
embodiments, power can be delivered to the IC stack by one or more
TSVs. For example, in certain embodiments, a TSV can carry power
from a power source through or from the supplementary IC to the
primary IC.
[0041] Consistent with various embodiments, during the IC
fabrication process, silicon wafers and individual die (e.g. die
that have passed through the dicing operation) can undergo a
back-grinding process to reduce the thickness of the die substrate
layer. Such a process can facilitate power delivery to chips in an
IC stack, as well as having positive effects on the IC stack's
thermal balance. For instance, back grinding techniques can
decrease the distance between a power source and the active device
layer of a chip in an IC stack, reducing inductance and resistance
while mitigating associated losses in transmitted power. Further,
the use of back grinding techniques to reduce the thickness of the
die substrate layer can decrease the distance between a chip in an
IC stack and a cooling element, facilitating heat dissipation of
the IC stack.
[0042] Turning now to the figures, FIG. 1 shows a three-dimensional
exploded view of the primary integrated circuit 125, supplementary
integrated circuit 150, and cooling element 100, consistent with
embodiments of the present disclosure. Aspects of FIG. 1 are
directed toward a 3D integrated circuit stack device designed for
thermal management, and including a primary IC 125 that can be
located between a supplementary IC 150 and a cooling element 100.
The primary IC 125 can be interfaced with the supplementary IC 150
and the cooling element 100 such that the cooling element can
facilitate heat dissipation of the IC stack device. Consistent with
various embodiments, the primary IC 125 can include a first set of
cores including one or more functional cores (depicted without
shading) and one or more non-functional cores (depicted as shaded),
such as non-functional core 104, located on a surface of the
primary IC 125. Similarly, the supplementary IC 150 can include a
second set of cores including one or more functional cores, such as
functional core 102, and one or more non-functional cores, located
on a surface of the supplementary IC 150. In certain embodiments,
functional cores can be disabled to facilitate thermal and power
management of the IC chip stack.
[0043] Consistent with various embodiments, the primary IC 125 and
the supplementary IC 150 can each include a data bus configured to
route information between cores located on a respective integrated
circuit. In certain embodiments, once an IC has been designated as
a primary IC 125 in the manufacturing process, the IC stack device
can be connected and configured such that the data bus 108 on the
primary IC 125 can function as an active data bus for all cores on
both the primary IC 125 and the supplementary IC 150. In certain
embodiments, the data bus 106 on the supplementary IC can be
capable of facilitating communication between the cores on the
supplementary IC. In certain embodiments, the data bus 106 can be
inactive.
[0044] FIG. 2 shows a logical or functional representation of the
system in which the functionality of non-functional cores (depicted
as shaded) on the primary integrated circuit 125 can be replaced by
the functionality of functional cores (depicted without shading) on
the supplementary integrated circuit 150. Aspects of FIG. 2 are
directed toward systems and methods designed to increase the yield
of functional integrated circuits. Consistent with various
embodiments, FIG. 2 shows a logical or functional representation of
both a primary IC 125 and a supplementary IC 150, which can each
include a number of functional cores, such as functional core 102
and non-functional cores, such as non-functional core 104. As
discussed herein, in certain embodiments, the primary IC 125 can
have more functional cores than the supplementary IC 150.
[0045] In certain embodiments, the 3D IC stack device can be
designed to allow the functionality of functional cores on the
supplementary IC 150 to be utilized in place of non-functional
cores on the primary IC 125, thereby replacing the functionality of
the non-functional core (which may be disabled). For example,
consistent with various embodiments, the functionality of the
functional core 102 can be utilized in place of the functionality
of the non-functional core 104. By replacing the functionality of
non-functional cores on the primary IC 125 with the functionality
of functional cores on the supplementary IC, the IC stack device
can make use of a greater number of cores than either the primary
IC 125 or the supplementary IC 150 individually, as depicted by the
resultant IC logical or functional representation 300.
[0046] Consistent with various embodiments, the primary IC 125 and
the supplementary IC 150 can be matched such that the supplementary
IC 150 has functional cores in locations that correspond to the
locations of the non-functional cores on the primary IC 150. This
configuration can be particularly useful for facilitating
communication between the primary IC and the supplementary IC.
Further, in certain embodiments, there can be a 1:1 ratio between
the non-functional cores on the primary IC and the functional cores
on the supplementary IC 150.
[0047] In certain embodiments, the supplementary IC 150 can have a
greater number of functional cores than the number of
non-functional cores on the primary IC 125. In such a
configuration, the extra functional cores on the supplementary IC
150 can be treated as "spare cores," and can be utilized to
supplement the primary IC 125, or for redundancy, e.g., as a
replacement in case of core failure on the primary IC 125. In
certain embodiments, these "spare cores" can be disabled (e.g.
physically disabled with a fuse, or logically disabled, such as
through the use of an EPROM logic switch) until they are desired as
a replacement core, at which point they can be re-activated.
Further, in certain embodiments, these spare cores can be activated
in order to balance the thermal distribution of the active cores
within the IC stack without adversely impacting performance. For
example, consistent with various embodiments, a functional core on
the primary IC 125 can be temporarily disabled, and a spare core on
the supplementary IC 150 can be utilized instead, shifting the heat
generation to elsewhere in the IC stack, and having positive
effects on the overall thermal distribution of the IC stack
device.
[0048] Aspects of the present disclosure relate to the recognition
that, in certain embodiments, the supplementary IC 150 can have a
lesser number of functional cores than the number of non-functional
cores on the primary IC 125. In certain embodiments, certain cores
within primary IC 125 may have been designed with functionality
similar to or redundant with another core in the IC stack, such
that one of them is sufficient. Further, consistent with various
embodiments, one or more cores on the supplementary IC 150 can be
specifically designed to have functionality redundant with a
non-functional core on the primary IC 125, and thus act as a
replacement. In certain embodiments, the application of the IC
circuit stack may allow for a lesser number of total functional
cores, such that some number of non-functional cores can be
considered acceptable. For example, in certain embodiments, the
resultant IC representation 300 can have 10 functional cores. In
certain embodiments, the resultant IC representation 300 can have 7
functional cores. Other core configurations are also possible. Such
configurations can have positive effects on manufacturing
productivity, and allow for the creation of lower cost
products.
[0049] FIG. 3 shows a cross-sectional view of the primary IC 125
and the supplementary IC 150 in a back-to-back orientation.
Consistent with certain embodiments, functional core 102 can be
enabled, and non-functional core 104 can be disabled. For ease of
discussion with reference to FIGS. 3-5, these cores can be referred
to as enabled core 102 and disabled core 104, respectively. Aspects
of FIG. 3 are directed toward a 3D IC stack device with an on-chip
communication network and logic system configured to replace the
functionality of a disabled core 104 on a primary IC 125 with the
functionality of an enabled core 102 from a supplementary IC 150.
In certain embodiments, the primary IC 125 and the supplementary IC
150 can be arranged in a back-to-back configuration, in which the
die substrate surfaces of each IC are interfaced with one
another.
[0050] Consistent with various embodiments, the primary IC 125 and
the supplementary IC 150 can be arranged in a back-to-back
configuration, in which the die substrate surfaces of each IC are
interfaced with one another. Further, in certain embodiments, the
primary IC 125 and the supplementary IC 150 can have identical
active device layer layouts (i.e. active devices of the same size
and type located in the same respective location of each IC).
Aspects of the present disclosure relate to the recognition that,
in such a configuration (i.e., back-to-back and with identical
active device layer layouts), the primary IC 125 and the
supplementary IC 150 are inverted with respect to one another. This
can cause misalignment between active devices (e.g. cores,
input/output rings, communication contacts, power pins) on the
primary IC 125 with corresponding active devices on the
supplementary IC 150. Accordingly, to facilitate alignment between
the active devices on the primary IC 125 with corresponding active
devices on the supplementary IC 150, aspects of the present
disclosure relate to designing a primary IC 125 and a supplementary
IC 150 with symmetry relative to one another about the horizontal
or vertical axis of the active device surface. Such a symmetry
condition can allow the active devices on the primary IC 125 to
align properly with corresponding active devices on the
supplementary IC 150 in a back-to-back configuration.
[0051] In certain embodiments, the primary IC 125 and the
supplementary IC 150 can be composed of a plurality of layers,
including but not necessarily limited to one or more of the
following: a die substrate layer 220, 240, a front-end-of-line
(FEOL) layer 218, 242, a (critical logic) back-end-of-line (BEOL)
layer 214, 244, a partition/global BEOL layer 212, and a custom
BEOL layer 246. In certain embodiments, after being designated as a
supplementary IC in the manufacturing process, the supplementary IC
150 can be equipped with a custom BEOL layer 246 designed to
facilitate connectivity between the supplementary IC 150 and the
primary IC 125. Consistent with various embodiments, the die
substrate layer 220, 240, FEOL layer 218, 242, (critical logic)
BEOL layer 214, 244, partition/global BEOL layer 212, and custom
BEOL layer 246 can each be made up of one or more sub-layers of
semiconductor materials, interconnection devices, or other
structures.
[0052] Aspects of the present disclosure relate to a 3D IC stack
device with a primary IC 125 and a supplementary IC 150 arranged in
a back-to-back orientation. In such a configuration, with the die
substrate surface 220 of the primary IC 125 interfaced with the die
substrate surface 240 of the supplementary IC 150, the
partition/global BEOL layer 212 of the primary IC 125 can be
directly interfaced with a cooling element, facilitating heat
dissipation of the active devices on the primary IC 125. As these
active devices can be a significant source of heat generation in
the IC chip stack, such a back-to-back configuration can have
positive effects on the thermal management of the IC chip
stack.
[0053] Aspects of the present disclosure are directed toward a 3D
integrated circuit stack device including one or more multiplexer
blocks configured to selectively route data between cores in the IC
stack and a variety of peripheral components, such as an
input/output ring or a data pin. Other peripheral components are
also possible. In certain embodiments, both the primary IC 125 and
the supplementary IC 150 can include a multiplexer block. In
certain embodiments, the multiplexer block 224 on the supplementary
IC 150 can be unused, and the multiplexer block 210 on the primary
IC can function as the active multiplexer block for the IC stack
device. For instance, in certain embodiments, the multiplexer block
210 can be communicatively connected with an enabled core 102 on
the supplementary IC and a disabled core 104 on the primary IC. The
multiplexer block 210 can then selectively route data from the
enabled core 102 to a data bus in place of data from the disabled
core 104.
[0054] Consistent with various embodiments, the primary IC 125 and
the supplementary IC 150 can include one or more TSV connections to
allow for communication between the supplementary IC 150 and the
primary IC 125. In certain embodiments, the primary IC 125 can
include a TSV 202 and a TSV 206, and the supplementary IC 150 can
include a TSV 204 and a TSV 208. The TSV 202 and the TSV 206 can be
connected to the TSV 204 and the TSV 208, respectively, by means of
a first chip interconnect 230 and a second chip interconnect 232.
The chip interconnects can follow one or more of a variety of chip
interconnect designs, including but not necessarily limited to a
solder bump, a pogo pin, or a fuzzy bump. In certain embodiments,
the multiplexer block 210 can be connected to the enabled core 102
through the TSV 206, the second chip interconnect 232, and the TSV
208. In certain embodiments, the multiplexer block 210 can connect
to a peripheral component connection 228 (e.g., an input/output
ring or a data pin) through the TSV 202, the first chip
interconnect 230, and the TSV 204.
[0055] FIG. 4 shows a cross-sectional view of the primary IC 125
and the supplementary IC 150 in a front-to-front orientation.
Aspects of FIG. 4 are directed toward a 3D IC stack device with an
on-chip communication network and logic system configured to
replace the functionality of a disabled or non-functional core 104
on a primary IC 125 with the functionality of an enabled core 102
from a supplementary IC 150. In certain embodiments, the primary IC
125 and the supplementary IC 150 can be arranged in a
front-to-front configuration, in which the active device surfaces
of each IC are interfaced with one another.
[0056] Consistent with various embodiments, the primary IC 125 and
the supplementary IC 150 can be arranged in a front-to-front
configuration, in which the die substrate surfaces of each IC are
interfaced with one another. Further, in certain embodiments, the
primary IC 125 and the supplementary IC 150 can have identical
active device layer layouts (i.e. active devices of the same size
and type located in the same respective location of each IC).
Aspects of the present disclosure relate to the recognition that,
in such a configuration (i.e., front-to-front and with identical
active device layer layouts), the primary IC 125 and the
supplementary IC 150 are inverted with respect to one another. This
can cause misalignment between active devices (e.g. cores,
input/output rings, communication contacts, power pins) on the
primary IC 125 with corresponding active devices on the
supplementary IC 150. Accordingly, to facilitate alignment between
the active devices on the primary IC 125 with corresponding active
devices on the supplementary IC 150, aspects of the present
disclosure relate to designing a primary IC 125 and a supplementary
IC 150 with symmetry relative to one another about the horizontal
or vertical axis of the active device surface. Such a symmetry
condition can allow the active devices on the primary IC 125 to
align properly with corresponding active devices on the
supplementary IC 150 in a front-to-front configuration.
[0057] In certain embodiments, the primary IC 125 and the
supplementary IC 150 can be composed of a plurality of layers,
including but not necessarily limited to one or more of the
following: a die substrate layer 220, 240, a front-end-of-line
(FEOL) layer 218, 242, a (critical logic) back-end-of-line (BEOL)
layer 214, 244, a partition/global BEOL layer 212, and a custom
BEOL layer 246. In certain embodiments, after being designated as a
supplementary IC in the manufacturing process, the supplementary IC
150 can be equipped with a custom BEOL layer 246 designed to
facilitate connectivity between the supplementary IC 150 and the
primary IC 125. Consistent with various embodiments, the die
substrate layer 220, 240, FEOL layer 218, 242, (critical logic)
BEOL layer 214, 244, partition/global BEOL layer 212, and custom
BEOL layer 246 can each be made up of one or more sub-layers of
semiconductor materials, interconnection devices, or other
structures.
[0058] Aspects of the present disclosure relate to a 3D IC stack
device with a primary IC 125 and a supplementary IC 150 arranged in
a front-to-front orientation. In such a configuration, with the
partition/global BEOL layer 212 of the primary IC 125 interfaced
with the custom BEOL layer of the supplementary IC 150, few (if
any) TSVs are needed to connect the primary IC 125 and the
supplementary IC 150, reducing the overall complexity and number of
components of the IC stack device. As the front-to-front
orientation allows for proximate connection between the active
device layer of the primary IC 125 and the supplementary IC 150,
such a configuration can be particularly useful for facilitating
communication between the integrated circuits in the IC stack. For
instance, high speed data signals may be subject to restrictions on
signal path length, capacitive loading and other parameters that
can be mitigated with shorter signal connection paths.
[0059] Aspects of the present disclosure are directed toward a 3D
integrated circuit stack device including one or more multiplexer
blocks configured to selectively route data between cores in the IC
stack and a variety of peripheral devices, such as an input/output
ring, a power source, or a data pin. Other peripheral devices are
also possible. In certain embodiments, both the primary IC 125 and
the supplementary IC 150 can include a multiplexer block. In
certain embodiments, the multiplexer block 224 on the supplementary
IC 150 can be unused, and the multiplexer block 210 on the primary
IC can function as the active multiplexer block for the IC stack
device. For instance, in certain embodiments, the multiplexer block
210 can be communicatively connected with an enabled core 102 on
the supplementary IC and a disabled core 104 on the primary IC 125,
and selectively route data from the enabled core 102 to a data bus
in place of data from the disabled core 104.
[0060] Consistent with various embodiments, the supplementary IC
150 can have one or more TSV connections that allow for
communication between one or more ICs in the chip stack and devices
external to the chip stack, as well as between the supplementary IC
150 and the primary IC 125. For example, in certain embodiments,
the supplementary IC 150 can include a TSV 204 that provides an
electrical connection between the multiplexer block 210 and a
peripheral device connection 228. The TSV 204 can be electrically
connected to the primary IC 125 through the use of a chip
interconnection 230. In certain embodiments, the multiplexer block
210 on the primary IC can be connected to the enabled core 102
through the chip interconnection 232. The chip interconnects can
follow one or more of a variety of chip interconnect designs,
including but not necessarily limited to a solder bump, a pogo pin,
or a fuzzy bump. In certain embodiments, the multiplexor block 210
can be communicatively connected with an input/output ring on the
primary IC 125 or the supplementary IC 150 that can facilitate
connection to devices external to the IC stack through a TSV
connection.
[0061] FIG. 5 shows a cross-sectional view of the primary IC 125
and the supplementary IC 150 in a front-to-back orientation.
Aspects of FIG. 5 are directed toward a 3D IC stack device with an
on-chip communication network and logic system configured to
replace the functionality of a disabled or non-functional core 104
on a primary IC 125 with the functionality of an enabled core 102
on a supplementary IC 150. In certain embodiments, the primary IC
125 and the supplementary IC 150 can be arranged in a front-to-back
configuration, in which the active device surface of the primary IC
125 is interfaced with the die substrate surface of the
supplementary IC 150.
[0062] In certain embodiments, the primary IC 125 and the
supplementary IC 150 can be composed of a plurality of layers,
including but not necessarily limited to one or more of the
following: a die substrate layer 220, 240, a front-end-of-line
(FEOL) layer 218, 242, a (critical logic) back-end-of-line (BEOL)
layer 214, 244, a partition/global BEOL layer 212, and a custom
BEOL layer 246. In certain embodiments, after being designated as a
supplementary IC in the manufacturing process, the supplementary IC
150 can be equipped with a custom BEOL layer 246 designed to
facilitate connectivity between the supplementary IC 150 and the
primary IC 125. Consistent with various embodiments, the die
substrate layer 220, 240, FEOL layer 218, 242, (critical logic)
BEOL layer 214, 244, partition/global BEOL layer 212, and custom
BEOL layer 246 can each be made up of one or more sub-layers of
semiconductor materials, interconnection devices, or other
structures.
[0063] Aspects of the present disclosure relate to a 3D IC stack
device with a primary IC 125 and a supplementary IC 150 arranged in
a front-to-back orientation. In such a configuration, with the
partition/global BEOL layer 212 of the primary IC 125 interfaced
with the die substrate surface of the supplementary IC 150, power
from a power source below the supplementary IC 150 can be delivered
to the active device layer of the primary IC 125 without passing
through the die substrate layer 220 of the primary IC 125. Such a
configuration can be particularly useful for facilitating power
delivery to the primary IC 125, and can reduce inductance and
resistance while mitigating associated losses in transmitted
power.
[0064] Aspects of the present disclosure are directed toward a 3D
integrated circuit stack device including one or more multiplexer
blocks configured to selectively route data between cores in the IC
stack and a variety of peripheral devices, such as an input/output
ring, a power source, or a data bus. Other peripheral devices are
also possible. In certain embodiments, both the primary IC 125 and
the supplementary IC 150 can include a multiplexer block. In
certain embodiments, the multiplexer block 224 on the supplementary
IC 150 can be unused, and the multiplexer block 210 on the primary
IC can function as the active multiplexer block for the IC stack
device. For instance, in certain embodiments, the multiplexer block
210 can be communicatively connected with an enabled core 102 on
the supplementary IC and a disabled core 104 on the primary IC 125,
and selectively route data from the enabled core 102 to a data bus
in place of data from the disabled core 104. In certain
embodiments, the multiplexor block 210 can be communicatively
connected to an input/output ring or other communication elements
through a TSV connection.
[0065] Consistent with various embodiments, the supplementary IC
150 can include one or more TSV connections to allow for
communication between the supplementary IC 150 and the primary IC
125. In certain embodiments, the supplementary IC 150 can include a
TSV 204 and a TSV 208. The TSV 204 and the TSV 208 can be connected
to the primary IC 125 through the use of a first chip interconnect
230 and a second chip interconnect 232, respectively. In certain
embodiments, the multiplexer block 210 can be connected to the
enabled core 102 through the second chip interconnect 232 and the
TSV 208. In certain embodiments, the multiplexer block 210 can
connect to a peripheral component connection 228 (e.g., an
input/output ring or a data pin) through the first chip
interconnect 230 and the TSV 204.
[0066] FIG. 6 shows a cross-sectional view of the primary IC 125
and the supplementary IC 150 in a back-to-front orientation.
Aspects of FIG. 6 are directed toward a 3D IC stack device with an
on-chip communication network and logic system configured to
replace the functionality of a disabled or non-functional core 104
on a primary IC 125 with the functionality of an enabled core 102
from a supplementary IC 150. In certain embodiments, the primary IC
125 and the supplementary IC 150 can be arranged in a back-to-front
configuration, in which the die substrate surface of the primary IC
125 is interfaced with the active device surface of the
supplementary IC 150.
[0067] In certain embodiments, the primary IC 125 and the
supplementary IC 150 can be composed of a plurality of layers,
including but not necessarily limited to one or more of the
following: a die substrate layer 220, 240, a front-end-of-line
(FEOL) layer 218, 242, a (critical logic) back-end-of-line (BEOL)
layer 214, 244, a partition/global BEOL layer 212, and a custom
BEOL layer 246. In certain embodiments, after being designated as a
supplementary IC in the manufacturing process, the supplementary IC
150 can be equipped with a custom BEOL layer 246 designed to
facilitate connectivity between the supplementary IC 150 and the
primary IC 125. Consistent with various embodiments, the die
substrate layer 220, 240, FEOL layer 218, 242, (critical logic)
BEOL layer 214, 244, partition/global BEOL layer 212, and custom
BEOL layer 246 can each be made up of one or more sub-layers of
semiconductor materials, interconnection devices, or other
structures.
[0068] Aspects of the present disclosure relate to a 3D IC stack
device with a primary IC 125 and a supplementary IC 150 arranged in
a back-to-front orientation. In such a configuration, the
partition/global BEOL layer 212 of the primary IC 125 can be
directly interfaced with the cooling element. As the active devices
(e.g. cores) located proximate to the partition/global BEOL layer
212 of the primary IC 125 are a significant source of heat for the
IC stack device, placement next to the cooling element can
facilitate heat dissipation and thermal management of the IC stack
device. Further, as the active devices located on the custom BEOL
layer 246 of the supplementary IC 150 can also generate heat, such
a configuration with the custom BEOL layer 246 oriented facing the
cooling element can have further positive effects on the overall
thermal distribution of the IC stack device.
[0069] Aspects of the present disclosure are directed toward a 3D
integrated circuit stack device including one or more multiplexer
blocks configured to selectively route data between cores in the IC
stack and a variety of peripheral devices, such as an input/output
ring, a power source, or a data pin. Other peripheral devices are
also possible. In certain embodiments, both the primary IC 125 and
the supplementary IC 150 can include a multiplexer block. In
certain embodiments, the multiplexer block 224 on the supplementary
IC 150 can be unused, and the multiplexer block 210 on the primary
IC can function as the active multiplexer block for the IC stack
device. For instance, in certain embodiments, the multiplexer block
210 can be communicatively connected with an enabled core 102 on
the supplementary IC and a disabled core 104 on the primary IC 125,
and selectively route data from the enabled core 102 to a data bus
in place of data from the disabled core 104.
[0070] Consistent with various embodiments, the primary IC 125 and
the supplementary IC 150 can include one or more TSV connections to
allow for communication between the supplementary IC 150 and the
primary IC 125. In certain embodiments, the primary IC 125 can
include a TSV 202 and a TSV 206, and the supplementary IC 150 can
include a TSV 204. The TSV 202 can be connected to the TSV 204 by
means of a first chip interconnect 230. Similarly, the TSV 206 can
be connected to the supplementary IC 150 by means of a second chip
interconnect 232. In certain embodiments, the multiplexer block 210
can be connected to the enabled core 102 through the TSV 206 and
the second chip interconnect 232. In certain embodiments, the
multiplexer block 210 can be connected to a peripheral component
connection 228 (e.g., an input/output ring) through the TSV 202,
the first chip interconnect 230, and the TSV 204. The multiplexer
block 210 can also be communicatively connected with a data bus
located on the primary IC 125.
[0071] FIG. 7 shows a block diagram of the process of assembling a
3D integrated circuit stack device, consistent with embodiments of
the present disclosure. Consistent with various embodiments, the
process can begin with the preparation of silicon wafers at block
700. Wafer preparation can include the cutting and polishing of a
slice from a mono-crystalline ingot, as well as the process of
pre-cleaning the wafer with high purity, low particle chemicals. In
certain embodiments, the silicon wafers can be heated and exposed
to ultra-pure oxygen to form a uniform-film silicon dioxide film on
the surface of the wafer. At certain stages throughout the process
described herein, the silicon wafers can undergo photolithography,
or "masking." In certain embodiments, a photo-resist or
light-sensitive film can be applied to the wafer, and the wafer can
be aligned to a photomask pattern. The wafer can then be exposed to
high intensity light, transferring the geometric pattern from the
photomask to the silicon substrate.
[0072] The silicon wafer can then pass to block 704, at which point
the front-end-of-line (FEOL) devices can be formed. In certain
embodiments, the FEOL devices can include transistors, capacitors,
resistors and other discrete circuit components. At block 706, some
of the back-end-of-line (BEOL) devices can be formed on the silicon
wafer. In certain embodiments, the BEOL devices can provide
interconnections for the FEOL devices already formed on the silicon
wafer. In certain embodiments, the BEOL devices can include
resistors, inductors, transmission lines, capacitors, wires,
contacts, dielectrics, insulators or bonding sites.
[0073] At block 708, the wafers can undergo a partial device test.
The semiconductor devices can be subjected to a variety of
electrical tests to determine whether or not they are functioning
properly. In certain embodiments, the silicon wafers can undergo
kerf testing to monitor for factors (e.g. defects in the kerf
structures) that indicate likelihood of cores on the wafer being
defective or non-functional. For example, in certain embodiments,
kerf testing can include testing of DRAM arrays, SRAM arrays, logic
structures (e.g. latches and combinational logic) and other kerf
structures. The results of the kerf testing can provide information
about the health of a given silicon wafer, which can impact its
path through the assembly process. In certain embodiments, if the
results of the kerf testing indicate that a silicon wafer has a
likelihood beyond a certain tolerance level of cores on the wafer
being defective, production of the entire wafer can be halted to
avoid the costs of further processing.
[0074] At block 710, the results of the kerf testing and/or partial
device testing of block 708 can be used to classify a silicon wafer
as a primary based IC wafer or a supplementary based IC wafer. For
example, consistent with various embodiments, wafers that were
determined to be substantially healthy by the kerf testing and/or
partial device testing process can be classified as primary based
IC wafers. In certain embodiments, wafers that were not determined
to be substantially healthy can be classified as supplementary
based IC wafers.
[0075] Based upon their classification as primary based IC wafers
or supplementary based IC wafers at block 710, the wafers can then
proceed to either block 712 or block 714. If a wafer has been
classified as a primary based IC wafer it can proceed to block 714
to receive a final BEOL layer. In certain embodiments, the final
BEOL layer can include additional metal interconnection layers. In
certain embodiments, if a wafer has been classified as a
supplementary based IC wafer, it can proceed to block 712 to
receive a custom BEOL layer. The custom BEOL layer can be unique
with respect to the final BEOL layer of the primary based IC wafer,
and can facilitate connection between the enabled cores on the
supplementary IC and the active data bus on the primary IC.
[0076] Further, blocks 712 and 714 can allow for the processing of
through-silicon-vias in the silicon wafers. In certain embodiments,
one or more TSVs can be created to allow for communication between
the supplementary IC and a primary IC or other peripheral component
after assembly of an IC stack device. In certain embodiments, the
supplementary based IC wafers can undergo TSV processing. In
certain embodiments, both the supplementary based IC wafers and the
primary based IC wafers can undergo TSV processing.
[0077] The primary based IC wafers and the supplementary based IC
wafers can then pass to blocks 716 and 718, respectively, to
undergo a final test to evaluate the functionality of the
semiconductor devices. In certain embodiments, the final testing
can be customized for the primary based IC wafers and the
supplementary based IC wafers due to the relative differences in
their BEOL layers. In certain embodiments, the individual cores on
a die can be tested to determine whether or not they are
functioning properly. The cores on a die that are determined to be
non-functional can be identified and disabled. For example, the
location of non-functional cores can be marked on the wafer using a
drop of die. In certain embodiments, the non-functional cores can
be physically disabled with a fuse, or logically disabled, such as
through the use of an EPROM logic switch. In certain embodiments,
the location of non-functional or disabled cores on a given wafer
can be logged to a wafer map stored on a central computer database.
This wafer map can then be used subsequently in block 724 and 726
for device categorization and assembly.
[0078] The primary based IC wafers and the supplementary based IC
wafers can then pass to blocks 720 and 722, respectively, to
undergo wafer dicing and be cut into individual silicon die (i.e.
primary ICs and supplementary ICs). In certain embodiments, the
dicing process can be based upon the number and location of the
enabled and disabled cores stored on the wafer map created in
blocks 716 and 718.
[0079] After undergoing the dicing process, the primary ICs and the
supplementary ICs can then pass to blocks 724 and 726,
respectively. Here, the individually cut silicon die can be
categorized and respectively sorted into one of a plurality of
bins. In certain embodiments, primary ICs that have a full set of
enabled cores, or "fully functional" die can pass directly to block
732 to undergo module/build testing. In certain embodiments, the
binning process of the primary ICs and the supplementary ICs can be
based upon the number and location of disabled cores on the primary
IC and the supplementary IC. Accordingly, the wafer maps created in
blocks 716 and 718 can be referenced and used to sort the primary
ICs and the supplementary ICs. For example, in certain embodiments,
a supplementary IC could be sorted into one of the bins A, B, C . .
. N based upon a wafer map created in block 716, and a primary IC
could be sorted into one of the bins 1, 2, 3 . . . N based upon a
wafer map created in block 718.
[0080] At block 728, each primary IC can be matched with a
supplementary IC. In certain embodiments, the matching can be
performed by using the wafer maps created in blocks 716 and 718 to
pair each primary IC with a supplementary IC such that the location
of one or more disabled cores on the primary IC correspond to the
location of an enabled core on the supplementary IC. The primary IC
and supplementary IC pairs can then proceed to block 730, where
they can be assembled into a chip stack. In certain embodiments,
the primary IC can undergo a back grinding process to reduce the
thickness of the die substrate layer, and facilitate thermal
management of the IC stack. For example, in certain embodiments,
the supplementary IC and the primary IC can receive back-grinding
as part of the TSV creation process. Consistent with various
embodiments, the primary IC can be communicatively connected to the
supplementary IC, and equipped with an on-chip logic system
configured to replace the functionality of disabled or
non-functional cores on the primary IC with the functionality of
enabled cores from the supplementary IC. The assembled IC stack
devices can then proceed to block 732 for final module/build
testing to evaluate the functionality of the IC stack device as a
whole. If they are determined to be functional, the IC stack
devices can then proceed to block 734 for final processing and
packaging.
[0081] Although the present disclosure has been described in terms
of specific embodiments, it is anticipated that alterations and
modifications thereof will become apparent to those skilled in the
art. Therefore, it is intended that the following claims be
interpreted as covering all such alterations and modifications as
fall within the true spirit and scope of the disclosure.
* * * * *