Hovis; William P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hovis; William P..The latest application filed is for "circuit design for balanced logic stress".

Company Profile

0.38.33

Hovis; William P. - Rochester MN
Hovis; William P. - US
Hovis; William P - Rochester MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and memory controller for interruptible memory refresh Grant 10,096,353 - Cordero , et al. October 9, 2	2018-10-09
Memory device for interruptible memory refresh Grant 9,972,376 - Cordero , et al. May 15, 2	2018-05-15
Donor cores to improve integrated circuit yield Grant 9,612,988 - Bartley , et al. April 4, 2	2017-04-04
Multiple active vertically aligned cores for three-dimensional chip stack Grant 9,568,940 - Bartley , et al. February 14, 2	2017-02-14
Circuit design for balanced logic stress Grant 9,383,767 - Chadwick , et al. July 5, 2	2016-07-05
Intelligent chip placement within a three-dimensional chip stack Grant 9,312,199 - Bartley , et al. April 12, 2	2016-04-12
Multiple active vertically aligned cores for three-dimensional chip stack Grant 9,310,827 - Bartley , et al. April 12, 2	2016-04-12
Intelligent chip placement within a three-dimensional chip stack Grant 9,281,261 - Bartley , et al. March 8, 2	2016-03-08
Circuit design for balanced logic stress Grant 9,250,645 - Chadwick , et al. February 2, 2	2016-02-02
Interconnect solder bumps for die testing Grant 9,207,275 - Bartley , et al. December 8, 2	2015-12-08
Circuit Design For Balanced Logic Stress App 20150253808 - Chadwick; Nathaniel R. ; et al.	2015-09-10
Circuit Design For Balanced Logic Stress App 20150253807 - Chadwick; Nathaniel R. ; et al.	2015-09-10
Intelligent Chip Placement Within A Three-dimensional Chip Stack App 20150162259 - Bartley; Gerald K. ; et al.	2015-06-11
Multiple Active Vertically Aligned Cores For Three-dimensional Chip Stack App 20150162311 - Bartley; Gerald K. ; et al.	2015-06-11
Intelligent Chip Placement Within A Three-dimensional Chip Stack App 20150162250 - Bartley; Gerald K. ; et al.	2015-06-11
Multiple Active Vertically Aligned Cores For Three-dimensional Chip Stack App 20150160685 - Bartley; Gerald K. ; et al.	2015-06-11
Memory Device For Interruptible Memory Refresh App 20150127899 - Cordero; Edgar R. ; et al.	2015-05-07
System And Memory Controller For Interruptible Memory Refresh App 20150127898 - Cordero; Edgar R. ; et al.	2015-05-07
Method For Relating Test Time And Escape Rate For Multivariate Issue App 20150051869 - Appleyard; Jennifer E. ; et al.	2015-02-19
Donor Cores To Improve Integrated Circuit Yield App 20150032933 - Bartley; Gerald K. ; et al.	2015-01-29
Determining chip burn-in workload using emulated application condition Grant 8,943,458 - Chadwick , et al. January 27, 2	2015-01-27
Setting a reference voltage in a memory controller trained to a memory device Grant 8,902,681 - Fox , et al. December 2, 2	2014-12-02
Interconnect Solder Bumps For Die Testing App 20140167808 - Bartley; Gerald K. ; et al.	2014-06-19
Training a memory controller and a memory device using multiple read and write operations Grant 8,681,571 - Fox , et al. March 25, 2	2014-03-25
Sorting movable memory hierarchies in a computer system Grant 8,639,879 - Bartley , et al. January 28, 2	2014-01-28
Setting a reference voltage in a memory controller trained to a memory device Grant 8,289,784 - Fox , et al. October 16, 2	2012-10-16
Setting a Reference Voltage in a Memory Controller Trained to a Memory Device App 20120224436 - Fox; Benjamin A. ; et al.	2012-09-06
Structure for multi-level memory architecture with data prioritization Grant 8,255,628 - Bartley , et al. August 28, 2	2012-08-28
Setting controller termination in a memory controller and memory device interface in a communication bus Grant 8,111,564 - Fox , et al. February 7, 2	2012-02-07
Setting controller VREF in a memory controller and memory device interface in a communication bus Grant 8,102,724 - Fox , et al. January 24, 2	2012-01-24
Training a Memory Controller and a Memory Device Using Multiple Read and Write Operations App 20110307671 - Fox; Benjamin A. ; et al.	2011-12-15
Setting a Reference Voltage in a Memory Controller Trained to a Memory Device App 20110307717 - Fox; Benjamin A. ; et al.	2011-12-15
Sorting Movable Memory Hierarchies In A Computer System App 20110238879 - Bartley; Gerald K. ; et al.	2011-09-29
Setting memory controller driver to memory device termination value in a communication bus Grant 7,990,768 - Fox , et al. August 2, 2	2011-08-02
Setting memory device termination in a memory device and memory controller interface in a communication bus Grant 7,978,538 - Fox , et al. July 12, 2	2011-07-12
Setting memory device VREF in a memory controller and memory device interface in a communication bus Grant 7,974,141 - Fox , et al. July 5, 2	2011-07-05
Calibration of memory driver with offset in a memory controller and memory device interface in a communication bus Grant 7,848,175 - Fox , et al. December 7, 2	2010-12-07
Design structure of implementing power savings during addressing of DRAM architectures Grant 7,791,978 - Bartley , et al. September 7, 2	2010-09-07
Setting Memory Device VREF in a Memory Controller and Memory Device Interface in a Communication Bus App 20100188908 - Fox; Benjamin A. ; et al.	2010-07-29
Setting Memory Device Termination in a Memory Device and Memory Controller Interface in a Communication Bus App 20100188917 - Fox; Benjamin A. ; et al.	2010-07-29
Setting Controller Termination in a Memory Controller and Memory Device Interface in a Communication Bus App 20100192000 - Fox; Benjamin A. ; et al.	2010-07-29
Setting Controller VREF in a Memory Controller and Memory Device Interface in a Communication Bus App 20100188918 - Fox; Benjamin A. ; et al.	2010-07-29
Setting Memory Controller Driver to Memory Device Termination Value in a Communication Bus App 20100188916 - Fox; Benjamin A. ; et al.	2010-07-29
Calibration of Memory Driver With Offset in a Memory Controller and Memory Device Interface in a Communication Bus App 20100188919 - Fox; Benjamin A ; et al.	2010-07-29
Dynamic latency map for memory optimization Grant 7,707,379 - Bartley , et al. April 27, 2	2010-04-27
Production of limited lifetime devices achieved through E-fuses Grant 7,672,105 - Borkenhagen , et al. March 2, 2	2010-03-02
Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof Grant 7,645,645 - Hovis , et al. January 12, 2	2010-01-12
Efficient memory usage in systems including volatile and high-density memories Grant 7,613,870 - Bartley , et al. November 3, 2	2009-11-03
Design Structure Of Implementing Power Savings During Addressing Of DRAM Architectures App 20090196118 - Bartley; Gerald K. ; et al.	2009-08-06
Multi-level memory architecture with data prioritization Grant 7,496,711 - Bartley , et al. February 24, 2	2009-02-24
Structure and method of implementing power savings during addressing of DRAM architectures Grant 7,492,662 - Bartley , et al. February 17, 2	2009-02-17
Spider Web Interconnect Topology Utilizing Multiple Port Connection App 20090031067 - Bartley; Gerald K. ; et al.	2009-01-29
Structure and Method of Implementing Power Savings During Addressing of DRAM Architectures App 20080232185 - Bartley; Gerald K. ; et al.	2008-09-25
Design Stucture for Multi-Level Memory Architecture With Data Prioritization App 20080177951 - Bartley; Gerald K. ; et al.	2008-07-24
Fin field effect transistors (FinFETs) and methods for making the same Grant 7,368,787 - Hovis , et al. May 6, 2	2008-05-06
Production of Limited Lifetime Devices Achieved Through E-Fuses App 20080061816 - Borkenhagen; John M. ; et al.	2008-03-13
Multi-Level Memory Architecture With Data Prioritization App 20080016297 - Bartley; Gerald K. ; et al.	2008-01-17
Dynamic Latency Map for Memory Optimization App 20080016308 - Bartley; Gerald K. ; et al.	2008-01-17
Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof App 20070210411 - Hovis; William P. ; et al.	2007-09-13
Fin field effect transistors (FinFETs) and methods for making the same App 20070010059 - Hovis; William P. ; et al.	2007-01-11
Fin field effect transistors (FinFETs) and methods for making the same App 20060261414 - Hovis; William P. ; et al.	2006-11-23
Device having spare I/O and method of using a device having spare I/O Grant 7,124,213 - Cochran , et al. October 17, 2	2006-10-17
Methods and apparatus for efficient memory usage App 20060106984 - Bartley; Gerald K. ; et al.	2006-05-18
Device having spare I/O and method of using a device having spare I/O App 20050081125 - Cochran, William H. ; et al.	2005-04-14
System and method for memory self-timed refresh for reduced power consumption Grant 6,334,167 - Gerchman , et al. December 25, 2	2001-12-25
Early row address strobe (RAS) precharge Grant 5,297,091 - Blake , et al. March 22, 1	1994-03-22
Dynamic RAM with on-chip ECC and optimized bit and word redundancy Grant 5,134,616 - Barth, Jr. , et al. July 28, 1	1992-07-28
Multiple mode-set for IC chip Grant 5,036,495 - Busch , et al. July 30, 1	1991-07-30

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