U.S. patent application number 14/457338 was filed with the patent office on 2014-11-27 for packaging substrate having a passive element embedded therein.
The applicant listed for this patent is Unimicron Technology Corporation. Invention is credited to Shih-Ping Hsu, Zhao-Chong Zeng.
Application Number | 20140345930 14/457338 |
Document ID | / |
Family ID | 45563975 |
Filed Date | 2014-11-27 |
United States Patent
Application |
20140345930 |
Kind Code |
A1 |
Hsu; Shih-Ping ; et
al. |
November 27, 2014 |
PACKAGING SUBSTRATE HAVING A PASSIVE ELEMENT EMBEDDED THEREIN
Abstract
A packaging substrate includes: a dielectric layer unit having
top and bottom surfaces; a positioning pad embedded in the bottom
surface of the dielectric layer unit; at least a passive element
having a plurality of electrode pads disposed on upper and lower
surfaces thereof, the passive element being embedded in the
dielectric layer unit and corresponding to the positioning pad; a
first circuit layer disposed on the top surface of the dielectric
layer unit, the first circuit layer having first conductive vias
electrically connected to the electrode pads disposed on the upper
surface of the passive element; and a second circuit layer disposed
on the bottom surface of the dielectric layer unit, the second
circuit layer having second conductive vias electrically connected
to the electrode pads disposed on the lower surface of the passive
element. Through the embedding of the passive element, the overall
structure may have a reduced height.
Inventors: |
Hsu; Shih-Ping; (Taoyuan,
TW) ; Zeng; Zhao-Chong; (Taoyuan, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Unimicron Technology Corporation |
Taoyuan |
|
TW |
|
|
Family ID: |
45563975 |
Appl. No.: |
14/457338 |
Filed: |
August 12, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13208745 |
Aug 12, 2011 |
8829356 |
|
|
14457338 |
|
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Current U.S.
Class: |
174/260 |
Current CPC
Class: |
H05K 2201/10636
20130101; Y10T 29/49146 20150115; H05K 2203/1536 20130101; H05K
1/183 20130101; H05K 1/185 20130101; H05K 3/4602 20130101; H01L
23/49822 20130101; H05K 3/4679 20130101; Y02P 70/50 20151101; H01L
23/50 20130101; H05K 1/113 20130101; H05K 1/187 20130101; H01L
2924/0002 20130101; H05K 2201/0129 20130101; H05K 3/4644 20130101;
Y02P 70/611 20151101; H05K 3/0097 20130101; Y10T 29/4913 20150115;
H05K 3/4038 20130101; H05K 2203/1469 20130101; H01L 2924/0002
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
174/260 |
International
Class: |
H05K 1/18 20060101
H05K001/18; H05K 1/11 20060101 H05K001/11 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 13, 2010 |
TW |
099127018 |
Claims
1-7. (canceled)
8. A packaging substrate having a passive element embedded therein,
comprising: a dielectric layer unit having a top surface and a
bottom surface; solder bumps embedded in the bottom surface of the
dielectric layer unit; at least a passive element having a
plurality of electrode pads formed on an upper surface and a lower
surface of the passive element, wherein the at least a passive
element is embedded in the dielectric layer unit, and the electrode
pads are on the lower surface of the at least a passive element are
electrically connected to the second circuit layer via the solder
bumps; a first circuit layer formed on the top surface of the
dielectric layer unit, and having first conductive vias
electrically connected to the electrode pads formed on the upper
surface of the passive element; and a second circuit layer disposed
on the bottom surface of the dielectric layer unit, and
electrically connected to the electrode pads disposed on the lower
surface of the passive element through the solder bumps.
9. The packaging substrate of claim 8, further comprising a circuit
built-up structure formed on the top and bottom surfaces of the
dielectric layer unit and the first and second circuit layers.
10. The packaging substrate of claim 9, further comprising a solder
mask layer formed on the circuit built-up structure, wherein the
solder mask layer layer is formed with at least an opening for
exposing a part of the circuit built-up structure, for the exposed
part of the circuit built-up structure to be used as conductive
pads.
11. The packaging substrate of claim 8, further comprising a
circuit built-up structure formed on the top surface of the
dielectric layer unit and the first circuit layer.
12. The packaging substrate of claim 11, further comprising a
solder mask layer formed on the circuit built-up structure, the
bottom surface of the dielectric layer unit, and the second circuit
layer, wherein the solder mask layer is formed with at least an
opening for exposing a part of the circuit built-up structure and
the second circuit layer, for the exposed parts of the circuit-up
structure and the second circuit layer to be used as conductive
pads.
13-24. (canceled)
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates to packaging substrates and methods
of fabricating the same, and, more particularly, to a packaging
substrate having a passive element and a method of fabricating the
same.
[0003] 2. Description of Related Art
[0004] With the rapid development of semiconductor package
technology, passive elements are in increasing demands. Passive
elements do not affect the basic characteristics of signal, but
only allow the signals to pass therethrough. Passive elements
include capacitors, resistors and inductors. Compared to active
elements, the passive elements have their resistances unchanged
even when voltages or currents change, because the passive elements
do not participate in electron exercises.
[0005] Any product that is driven by electricity needs passive
elements that provide electrical loop controlling functions. Such
applications include 3C and other industrial fields. Please refer
to FIG. 1, which is a cross-sectional diagram of a packaging
substrate having a passive element according to the prior art. A
passive element 12 is disposed on conductive pads 11 on a substrate
10 by means of solder bumps 13.
[0006] With the development of technology, electronic devices are
designed to meet the low-profile and compact-size requirements.
However, a package structure of the prior art, in which the passive
element 12 is disposed on the substrate 10, has an increased
height, and is adverse in the thinning design for the electronic
devices. Since the passive element 12 is disposed on an external
surface of the substrate 10, a signal transmission route between an
interlayer circuit and a passive element of the substrate 10 is
very long, which results in the loss of electricity and electrical
functionality. Also, the surface of the substrate 10 is occupied by
a circuit layout, so an area within which passive elements may be
disposed is very limited. Therefore, only a small number of passive
elements may be disposed on the substrate 10. As the number of
passive elements increases, the area reduction of the circuit
layout is inevitable.
[0007] Therefore, how to avoid the drawbacks of the packaging
substrate having a passive element of the prior art is becoming one
of the popular issues in the art.
SUMMARY OF THE INVENTION
[0008] In view of the above-mentioned problems of the prior art, it
is an objective of the present invention to provide a packaging
substrate having a passive element embedded therein, with a reduced
structural height.
[0009] It is another objective of the present invention to provide
a packaging substrate having a passive element embedded therein,
with a shortened signal transmission route.
[0010] It is yet another objective of the present invention to
provide a packaging substrate having a passive element embedded
therein, in which more passive elements may be installed.
[0011] In order to achieve the above and other objectives, the
present invention provides a packaging substrate having a passive
element embedded therein, the packaging substrate including: a
dielectric layer unit having a top surface and a bottom surface; at
least a positioning pad embedded in the bottom surface of the
dielectric layer unit; at least a passive element embedded in the
dielectric layer unit and being corresponding in position to the at
least a positioning pad, the at least a passive element having a
plurality of electrode pads formed on one or both of an upper
surface and an opposing lower surface of the at least a passive
element; a first circuit layer formed on the top surface of the
dielectric layer unit, and having a plurality of first conductive
vias electrically connected to the electrode pads formed on the
upper surface of the at least a passive element; and a second
circuit layer formed on the bottom surface of the dielectric layer
unit, and having a plurality of second conductive vias electrically
connected to the electrode pads disposed on the lower surface of
the at least a passive element.
[0012] In an embodiment of the present invention, the dielectric
layer unit includes a plurality of thermalplastic dielectric layers
that include: at least a first thermalplastic dielectric layer for
the positioning pad to be embedded therein and for the passive
element to be disposed thereon; and at least a second
thermalplastic dielectric layer attached to the first
thermalplastic dielectric layer, allowing the at least a passive
element to be embedded in the second thermalplastic dielectric
layer.
[0013] In an embodiment of the present invention, the electrode
pads formed on the lower surface of the passive element correspond
in position to the positioning pads, and the second conductive vias
penetrate through the positioning pads.
[0014] In an embodiment of the present invention, a circuit
built-up structure is further formed on the top and bottom surfaces
of the dielectric layer unit and the first and second circuit
layers, and a solder mask layer is further formed on the circuit
built-up structure, wherein the solder mask layer is formed with at
least an opening for exposing a part of the circuit built-up
structure, for the exposed part of the circuit built-up structure
to be used as conductive pads.
[0015] In an embodiment of the present invention, a circuit
built-up structure is further formed on the top surface of the
dielectric layer unit and the first circuit layer, and a solder
mask layer is further disposed on the circuit built-up structure,
the bottom surface of the dielectric layer unit, and the second
circuit layer, wherein the solder mask layer is formed with at
least an opening for exposing a part of the circuit built-up
structure and the second circuit layer, for the exposed parts of
the circuit built-up structure and the second circuit layer to be
used as conductive pads.
[0016] The present invention provides another packaging substrate
having a passive element embedded therein, the packaging substrate
including: a dielectric layer unit having a top surface and a
bottom surface; solder bumps embedded in the bottom surface of the
dielectric layer unit; at least a passive element having a
plurality of electrode pads formed on an upper surface and a lower
surface of the passive element, wherein the at least a passive
element is embedded in the dielectric layer unit, and the electrode
pads are on the lower surface of the at least a passive element are
electrically connected to the second circuit layer via the solder
bumps; a first circuit layer formed on the top surface of the
dielectric layer unit, and having first conductive vias
electrically connected to the electrode pads formed on the upper
surface of the passive element; and a second circuit layer disposed
on the bottom surface of the dielectric layer unit, and
electrically connected to the electrode pads disposed on the lower
surface of the passive element through the solder bumps.
[0017] In an embodiment of the present invention, a circuit
built-up structure is further formed on the top and bottom surfaces
of the dielectric layer unit and the first and second circuit
layers, and a solder mask layer is further formed on circuit
built-up structure, wherein the solder mask layer is formed with at
least an opening for exposing a part of the circuit built-up
structure, for the exposed part of the circuit built-up structure
to be used as conductive pads.
[0018] In an embodiment of the present invention, a circuit
built-up structure is further formed on the top surface of the
dielectric layer unit and the first circuit layer, and a solder
mask layer is further formed on the circuit built-up structure, the
bottom surface of the dielectric layer unit, and the second circuit
layer, wherein the solder mask layer is formed with at least an
opening for exposing a part of the circuit built-up structure and
the second circuit layer, for the exposed parts of the circuit
built-up structure and the second circuit layer to be used as
conductive pads.
[0019] The present invention further discloses a method of
fabricating a packaging substrate having a passive element embedded
therein, the method including: providing a carrier board having two
surfaces, each of which has a release film and a metal layer
sequentially; forming positioning pads on the metal layers;
encapsulating the metal layers disposed on the two surfaces of the
carrier board with a first thermalplastic dielectric layer;
providing at least a passive element having a plurality of
electrode pads formed on an upper surface and a lower surface of
the passive element, and disposing the at least a passive element
on the first thermalplastic dielectric layer, with the positioning
pads as positioning sites; providing a second thermalplastic
dielectric layer that is stacked above the first thermalplastic
dielectric layer and the at least a passive element; heating and
compressing the first and second thermalplastic dielectric layers,
to form two dielectric layer units, each of which has top and
bottom surfaces, wherein the at least a passive element is embedded
in the dielectric layer unit, and the positioning pads are embedded
in the bottom surface of the dielectric layer unit; removing the
carrier board and the release film, so as to separate the two
dielectric layer units; and forming first and second circuit layers
on the top and bottom. surfaces of the dielectric layer units,
wherein the first circuit layer is formed with a plurality of first
conductive vias electrically connected to the electrode pads formed
on the upper surface of the at least a passive element, and the
second circuit layer is formed with a plurality of second
conductive vias electrically connected to the electrode pads
disposed on the lower surface of the at least a passive
element.
[0020] In an embodiment of the present invention, the electrode
pads formed on the lower surface of the passive element correspond
in position to the positioning pad, and the second conductive vias
penetrate through the positioning pads; a circuit built-up
structure is further formed on the top and bottom surfaces of the
dielectric layer unit and the first and second circuit layers; and
a solder mask layer is further formed on the circuit built-up
structure, wherein the solder mask layer is formed with at least an
opening for exposing a part of the circuit built-up structure, for
the exposed part of the circuit built-up structure to be used as
conductive pads.
[0021] The present invention provides another method of fabricating
a packaging substrate having a passive element embedded therein,
the method including: providing a carrier board having two
surfaces, each of which has a release film and a metal layer
sequentially; forming solder bumps on the metal layers; providing
at least a passive element having a plurality of electrode pads
formed on an upper surface and a lower surface of the at least a
passive element, and disposing the electrode pads disposed on the
lower surface of the at least a passive element on the solder
bumps; forming on the metal layers two dielectric layer units, each
of which has top and bottom surfaces, wherein the at least a
passive element is embedded in the dielectric layer unit, and the
solder bumps are embedded in the bottom surface of the dielectric
layer unit; removing the carrier board and the release film, so as
to separate the two dielectric layer units; and forming on the top
and bottom surfaces of the dielectric layer units first and second
circuit layers, wherein the first circuit layer is formed with a
plurality of first conductive vias electrically connected to the
electrode pads formed on the upper surface of the at least a
passive element, and the second circuit layer is electrically
connected to the electrode pads formed on the lower surface of the
at least a passive element through the solder bumps.
[0022] In an embodiment of the present invention, the method
further includes forming a circuit built-up structure on the top
and bottom surfaces of the dielectric layer unit and the first and
second circuit layers, and forming a solder mask layer on the
circuit built-up structure, wherein the solder mask layer is formed
with at least an opening for exposing a part of the circuit
built-up structure, for the exposed part of the circuit built-up
structure to be used as conductive pads.
[0023] The present invention further provides a method of
fabricating a packaging substrate having a passive element embedded
therein, the method including: providing a carrier board having two
surfaces, each of which has a release film and a metal layer
sequentially; forming positioning pads on the metal layers;
encapsulating the metal layers formed on the two surfaces of the
carrier board with a first thermalplastic dielectric layer;
providing at least a passive element having a plurality of
electrode pads disposed on an upper surface and a lower surface of
the at least a passive element, and disposing the at least a
passive element on the first thermalplastic dielectric layer, with
the positioning pads used as positioning sites; providing a second
thermalplastic dielectric layer that is stacked above the first
thermalplastic dielectric layer and the at least a passive element;
heating and compressing the first and second thermalplastic
dielectric layers, to form two dielectric layer units, each of
which has top and bottom surfaces, wherein the passive element is
embedded in the dielectric layer unit, and the positioning pads are
embedded in the bottom surface of the dielectric layer unit;
forming a first circuit layer on the top surface of the dielectric
layer unit, wherein the first circuit layer is formed with a
plurality of first conductive vias electrically connected to the
electrode pads formed on the upper surface of the at least a
passive element; forming a circuit built-up structure on the top
surface of the dielectric layer unit and the first circuit layer;
removing the carrier board and the release film, so as to separate
the two dielectric layer units and the first circuit layer and the
circuit built-up structure formed on the two dielectric layer units
from the carrier board and the release film; and forming a second
circuit layer on the bottom surface of the dielectric layer unit,
wherein the second circuit layer is formed with a plurality of
second conductive vias electrically connected to the electrode pads
formed on the lower surface of the at least a passive element.
[0024] In an embodiment of the present invention, the electrode
pads formed on the lower surface of the passive element correspond
to the positioning pads, and the second conductive vias penetrate
through the positioning pads; and the method further includes
forming a solder mask layer on the circuit built-up structure, the
bottom surface of the dielectric layer unit, and the second circuit
layer, wherein the solder mask layer is formed with at least an
opening for exposing a part of the circuit built-up structure and
the second circuit layer, for the exposed parts of the circuit
built-up structure and the second circuit layer to be used as
conductive pads.
[0025] The present invention provides yet another method of
fabricating a packaging substrate having a passive element embedded
therein, the method including: providing a carrier board having two
surfaces, each of which has a release film and a metal layer
sequentially; forming solder bumps on the metal layers; providing
at least a passive element having a plurality of electrode pads
formed on an upper surface and a lower surface of the at least a
passive element, the electrode pads disposed on the lower surface
of the passive element being disposed on the solder bumps; forming
on the metal layers two dielectric layer units, each of which has
top and bottom surfaces, wherein the at least a passive element is
embedded in the dielectric layer unit, and the solder bumps are
embedded in the bottom surface of the dielectric layer unit;
forming a first circuit layer on the top surface of the dielectric
layer unit, wherein the first circuit layer is formed with a
plurality of first conductive vias electrically connected to the
electrode pads formed on the upper surface of the at least a
passive element; forming a circuit built-up structure on the top
surface of the dielectric layer unit and the first circuit layer;
removing the carrier board and the release film, so as to separate
the two dielectric layer units and the first circuit layer and the
circuit built-up structure formed on the two dielectric layer units
from the carrier board and the release film; and forming a second
circuit layer on the bottom surface of the dielectric layer unit,
wherein the second circuit layer is electrically connected to the
electrode pads formed on the lower surface of the at least a
passive element through the solder bumps.
[0026] In an embodiment of the present invention, the method
further includes forming a solder mask layer on the circuit
built-up structure, the bottom surface of the dielectric layer
unit, and the second circuit layer, wherein the solder mask layer
is formed with at least an opening for exposing parts of the
circuit built-up structure and the second circuit layer, for the
exposed parts of the circuit built-up structure and the second
circuit layer to be used as conductive pads.
[0027] It can be known from the above that the present invention,
through the embedding of the passive element, may have a reduced
overall structural height and shortened signal transmission route
between the passive element and interlayer circuits, as compared to
the prior art. Therefore, more passive elements may be installed,
without affecting the layout.
BRIEF DESCRIPTION OF DRAWINGS
[0028] The invention can be more fully understood by reading the
following detailed description of the preferred embodiments, with
reference made to the accompanying drawings, wherein:
[0029] FIG. 1 is a cross-section diagram of a packaging substrate
having a passive element according to the prior art;
[0030] FIGS. 2A to 2G are cross-sectional diagrams illustrating a
method of fabricating a packaging substrate having a passive
element embedded therein of a first embodiment according to the
present invention, wherein FIG. 2C is another embodiment of FIG.
2C';
[0031] FIGS. 3A to 3F are cross-sectional diagrams illustrating a
method of fabricating a packaging substrate having a passive
element embedded therein of a second embodiment according to the
present invention;
[0032] FIGS. 4A to 4D are cross-sectional diagrams illustrating a
method of fabricating a packaging substrate having a passive
element embedded therein of a third embodiment according to the
present invention; and
[0033] FIGS. 5A to 5C are cross-sectional diagrams illustrating a
method of fabricating a packaging substrate having a passive
element embedded therein of a fourth embodiment according to the
present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0034] The following illustrative embodiments are provided to
illustrate the disclosure of the present invention, these and other
advantages and effects can be apparently understood by those in the
art after reading the disclosure of this specification. The present
invention can also be performed or applied by other different
embodiments. The details of the specification may be on the basis
of different points and applications, and numerous modifications
and variations can be devised without departing from the spirit of
the present invention.
The First Embodiment
[0035] FIGS. 2A to 2G are cross-sectional diagrams illustrating a
method of fabricating a packaging substrate having a passive
element embedded therein according to the present invention.
[0036] As shown in FIG. 2A, a carrier board 20 is provided. Two
surfaces 20a of the carrier board 20 have release film 200 and
metal layers 201 sequentially.
[0037] As shown in FIG. 2B, a positioning pad 21 is formed on the
metal layer 201.
[0038] As shown in FIG. 2C, the metal layers 201 on the two
surfaces 20a of the carrier board 20 are encapsulated by a first
thermalplastic dielectric layer 230; a passive element 22 is
provided that has a plurality of electrode pads 220 disposed on
upper and lower surfaces thereof; and the passive element 22 is
disposed on the first thermalplastic dielectric layer 230, with the
positioning pad 21 as a positioning site, wherein the electrode
pads 220 disposed on the lower surface of the passive element 22
correspond in position to the positioning pad 21.
[0039] As shown in FIG. 2C', a positioning pads 21' or 21'' may be
formed that is arranged in different manners. The passive element
22 and the positioning pad 21' or 21'' correspond to different
positions.
[0040] As shown in FIG. 2D, a second thermalplastic dielectric
layer 231 is provided that is stacked above the first
thermalplastic dielectric layer 230 and the passive element 22; and
the first and second thermalplastic dielectric layers 230 and 231
are heated and compressed to form a dielectric layer unit 23 having
top and bottom surfaces 23a and 23b, wherein the passive element 22
is embedded in the dielectric layer unit 23, and the positioning
pad 21 is embedded in the bottom surface 23b of the dielectric
layer unit 23.
[0041] As shown in FIG. 2E, the carrier board 20 and the release
film 200 are removed, so as to separate the two dielectric layer
units 23.
[0042] As shown in FIG. 2F, first and second circuit layers 24a and
24b are formed on the top and bottom surfaces 23a and 23b of the
dielectric layer unit 23; the first circuit layer 24a has first
conductive vias 240a electrically connected to the electrode pads
220 disposed on the upper surface of the passive element 22; the
second circuit layer 24b has second conductive vias 240h
electrically connected to the electrode pads 220 disposed on the
lower surface of the passive element 22; and the second conductive
vias 240b penetrate through the positioning pad 21.
[0043] The metal layer 201 may be used as a current transmission
route required during a metal electroplating process, so as to
fabricate the second circuit layer 24b.
[0044] As shown in FIG. 2G a circuit built-up structure 25 is
formed on the top and bottom surfaces 23a and 23b of the dielectric
layer unit 23 and the first and second circuit layers 24a and 24b;
the circuit built-up structure 25 comprises at least a dielectric
layer 250, a circuit layer 251 disposed on the dielectric layer
250, and conductive vias 252 disposed in the dielectric layer 250
and electrically connected to circuits.
[0045] A solder mask layer 26 is further formed on a surface of the
circuit built-up structure 25. The solder mask layer 26 has an
opening 260 for exposing a part of the surface of the circuit
built-up structure 25, for used as conductive pads 253.
The Second Embodiment
[0046] Please refer to FIGS. 3A to 3F. The second embodiment
differs from the first embodiment in that in the second embodiment,
the solder bumps are replaced with positioning pads, and the
dielectric layer unit and the second circuit layer are fabricated
by different processes.
[0047] As shown in FIG. 3A, a carrier board shown in FIG. 2A is
provided, and solder bumps 31 are formed on the metal layer
201.
[0048] As shown in FIG. 3B, a passive element 22 shown in FIG. 2C
is provided, and electrode pads 220 disposed on a lower surface of
the passive element 22 are disposed on the solder bumps 31.
[0049] As shown in FIG. 3C, two dielectric layer units 33, each of
which has top and bottom surfaces 33a and 33b, are formed on the
metal layers 201; the passive element 22 is embedded in the
dielectric layer unit 33; and the solder bumps 31 are embedded in
the bottom surface 33b of the dielectric layer unit 33.
[0050] As shown in FIG. 3D, the carrier board 20 and the release
film 200 are removed, so as to separate the two dielectric layer
units 33.
[0051] As shown in FIG. 3E, first and second circuit layers 24a and
34b are formed on the top and bottom surfaces 33a and 33b of the
dielectric layer unit 33; the second circuit layer 34b is
electrically connected to the electrode pads 220 disposed on the
lower surface of the passive element 22 by means of the solder
bumps 31; and the first circuit layer 24a has first conductive vias
240a electrically connected to the electrode pads 220 disposed on
the upper surface of the passive element 22.
[0052] The metal layer 201 may be used as a current transmission
route required during a metal electroplating process, so as to
fabricate the second circuit layer 34b.
[0053] As shown in FIG. 3F, a circuit built-up structure 25 and a
solder mask layer 26 shown in FIG. 2G are formed on the top and
bottom surfaces 33a and 33b of the dielectric layer unit 33 and the
first and second circuit layers 24a and 34b.
The Third Embodiment
[0054] Please refer to FIGS. 4A to 4D. The third embodiment differs
from the first embodiment in the processes of fabricating the first
circuit layer and the circuit built-up structure.
[0055] As shown in FIG. 4A, subsequent to the fabrication process
shown in FIG. 2D, in which the dielectric layer unit 23 is formed
by the heating and compressing processes, a first circuit layer 44a
is formed on the top surface 23a of the dielectric layer unit 23,
and the first circuit layer 44a has first conductive vias 440a
electrically connected to the electrode pads 220 disposed on the
upper surface of the passive element 22; and a circuit built-up
structure 45 is then formed on the top surface 23a of the
dielectric layer unit 23 and the first circuit layer 44a. The
circuit built-up structure 45 comprises at least a dielectric layer
450, a circuit layer 451 disposed on the dielectric layer 450, and
conductive vias 452 disposed in the dielectric layer 450 and
electrically connected to circuits.
[0056] As shown in FIG. 4B, the carrier board 20 and the release
film 200 are removed, allowing the two dielectric layer units 23
and the first circuit layer 44a and the circuit built-up structure
45 formed thereon to be separated from the carrier board 20 and the
release film 200.
[0057] As shown in FIG. 4C, a second circuit layer 24b is formed on
the bottom surface 23b of the dielectric layer unit 23, the second
circuit layer 24b has second conductive vias 240b electrically
connected to the electrode pads 220 disposed on the lower surface
of the passive element 22, and the second conductive vias 240b
penetrate through the positioning pad 21.
[0058] The metal layer 201 may be used as a current transmission
route required during a metal electroplating process, so as to
fabricate the second circuit layer 24b.
[0059] As shown in FIG. 4D, a solder mask layer 46 is formed on the
circuit built-up structure 45, the bottom surface 23b of the
dielectric layer unit 23, and the second circuit layer 24b, the
solder mask layer 46 having an opening 460 for exposing a part of
surfaces of the circuit built-up structure 45 and the second
circuit layer 24b, for used as conductive pads 453.
The Fourth Embodiment
[0060] Please refer to FIGS. 5A to 5C. The fourth embodiment
differs from the second embodiment in the processes of fabricating
the first circuit layer and the circuit built-up structure.
[0061] As shown in FIG. 5A, subsequent to the fabrication process
shown in FIG. 3C, in which the dielectric layer unit 33 is formed,
a first circuit layer 54a is formed on the top surface 33a of the
dielectric layer unit 33; the first circuit layer 54a has first
conductive vias 540a electrically connected to the electrode pads
220 disposed on the upper surface of the passive element 22; and a
circuit built-up structure 55 is then formed on the top surface 33a
of the dielectric layer unit 33 and the first circuit layer 54a.
The circuit built-up structure 55 comprises at least a dielectric
layer 550, a circuit layer 551 disposed on the dielectric layer
550, and conductive vias 552 disposed in the dielectric layer 550
and electrically connected to circuits.
[0062] As shown in FIG. 5B, the carrier board 20 and the release
film 200 are removed, allowing the two dielectric layer units 33
and the first circuit layer 54a and the circuit built-up structure
55 formed thereon to be separated from the carrier board 20 and the
release film 200.
[0063] As shown in FIG. 5C, a second circuit layer 34b is formed on
the bottom surface 33b of the dielectric layer unit 33, and the
second circuit layer 34b is electrically connected to the electrode
pads 220 disposed on the lower surface of the passive element 22 by
means of the solder bumps 31.
[0064] The metal layer 201 may be used as a current transmission
route required during a metal electroplating process, so as to
fabricate the second circuit layer 34h.
[0065] A solder mask layer 56 is then formed on the circuit
built-up structure 55, the bottom surface 33b of the dielectric
layer unit 33, and the second circuit layer 34b. The solder mask
layer 56 has an opening 560 for exposing a part of surfaces of the
circuit built-up structure 55 and the second circuit layer 34b, for
used as conductive pads 553.
[0066] A packaging substrate having a passive element embedded
therein may be obtained by the methods of the first to third
embodiments. The packaging substrate comprises: a dielectric layer
unit 23 having top and bottom surfaces 23a and 23b; a positioning
pad 21 embedded in the bottom surface 23b of the dielectric layer
unit 23; a passive element 22 having a plurality of electrode pads
220 disposed on upper and lower surfaces thereof, the passive
element 22 being embedded in the dielectric layer unit 23 and
corresponding to the positioning pad 21; first circuit layers 24a
and 44a disposed on the top surface 23a of the dielectric layer
unit 23, the first circuit layers 24a and 44a having first
conductive vias 240a and 440a electrically connected to the
electrode pads 220 disposed on the upper surface of the passive
element 22; and a second circuit layer 24b disposed on the bottom
surface 23b of the dielectric layer unit 23, the second circuit
layer 24b having second conductive vias 240b electrically connected
to the electrode pads 220 disposed on the lower surface of the
passive element 22.
[0067] The dielectric layer unit 23 is composed by a plurality of
thermalplastic dielectric layers. The dielectric layer unit 23
includes: a first thermalplastic dielectric layer 230 in which the
positioning pad 21 is embedded, wherein the passive element 22 is
disposed on the first thermalplastic dielectric layer 230; and a
second thermalplastic dielectric layer 231 that combines with the
first thermalplastic dielectric layer 230, allowing the passive
element 22 to be embedded in the first and second thermalplastic
dielectric layers 230 and 231.
[0068] The electrode pads 220 disposed on the lower surface of the
passive element 22 correspond to the positioning pad 21, and the
second conductive vias 240b penetrate through the positioning pad
21.
[0069] According to the first embodiment, a symmetrical structure
may be formed: a circuit built-up structure 25 may be further
disposed on the top and bottom surfaces of the dielectric layer
unit 23 and the first and second circuit layers 24a and 24b; and
the packaging substrate further comprises a solder mask layer 26
disposed on the circuit built-up structure 25, the solder mask
layer 25 having an opening 260 for exposing a part of a surface of
the circuit built-up structure 25, for used as conductive pads
253.
[0070] According to the third embodiment, an asymmetrical structure
may be formed: a circuit built-up structure 45 is disposed on the
top surface 23a of the dielectric layer unit 23 and the first
circuit layer 44a, and the packaging substrate further comprises a
solder mask layer 46 disposed on the circuit built-up structure 45,
the bottom surface 23b of the dielectric layer unit 23, and the
second circuit layer 24b, the solder mask layer 46 having an
opening 460 for exposing a part of surfaces of the circuit built-up
structure 45 and the second circuit layer 24b, for used as
conductive pads 453.
[0071] A packaging substrate having a passive element embedded
therein may be obtained from the methods of the second and fourth
embodiments. The packaging substrate comprises: a dielectric layer
unit 33 having top and bottom surfaces 33a and 33b; solder bumps 31
embedded in the bottom surface 33b of the dielectric layer unit 33;
a passive element 22 having a plurality of electrode pads 220
disposed on upper and lower surfaces thereof, wherein the passive
element 22 is embedded in the dielectric layer unit 33, and the
electrode pads 220 disposed on the lower surface of the passive
element 22 are disposed on the solder bumps 31; first circuit
layers 24a and 54a disposed on the top surface 33a of the
dielectric layer unit 33, the first circuit layers 24a and 54a
having first conductive vias 240a and 540a electrically connected
to the electrode pads 220 disposed on the upper surface of the
passive element 22; and a second circuit layer 34b disposed on the
bottom surface of the dielectric layer unit 33, the second circuit
layer 34b being electrically connected to the electrode pads 220
disposed on the lower surface of the passive element 22 by means of
the solder bumps 31.
[0072] According to the second embodiment, a symmetrical structure
may be formed: a circuit built-up structure 25 is further disposed
on the top and bottom surfaces 33a and 33h of the dielectric layer
unit 33 and the first and second circuit layers 24a and 34b, and
the packaging substrate further comprises a solder mask layer 26
disposed on the circuit built-up structure 25, the solder mask
layer 26 having an opening 260 for exposing a part of a surface of
the circuit built-up structure 25, for used as conductive pads
253.
[0073] According to the fourth embodiment, an asymmetrical
structure may be funned: a circuit built-up structure 55 is further
disposed on the top surface 33a of the dielectric layer unit 33 and
the first circuit layer 54a, and the packaging substrate further
comprises a solder mask layer 56 disposed on the circuit built-up
structure 55, the bottom surface 33b of the dielectric layer unit
33, and the second circuit layer 34b, the solder mask layer 56
having an opening 560 for exposing a part of surfaces of the
circuit built-up structure 55 and the second circuit layer 34b, for
used as conductive pads 553.
[0074] In conclusion, the present invention, through the embedding
of the passive element 22, has a reduced overall structural height,
and is advantage for designing thinned electronic products. Also,
the signal transmission route between the passive element 22 and
interlayer circuits (e.g., the first and second circuit layers 24a,
44a, 54a, 24b and 34b) is shortened. Therefore, the electrical loss
is reduced, and the expected electrical functionality may be
achieved.
[0075] Moreover, since the passive element 22 is embedded in the
dielectric layer unit 23, more passive elements may be installed,
without affecting the layout area (e.g., the circuit built-up
structures 25, 45 and 55, and the first and second circuit layers
24a, 44a, 54a, 24b and 34b). As such, the demands of gain operation
function and process capability of electronic devices may be
satisfied.
[0076] The foregoing descriptions of the detailed embodiments are
only illustrated to disclose the features and functions of the
present invention and not restrictive of the scope of the present
invention. It should be understood to those in the art that all
modifications 115 and variations according to the spirit and
principle in the disclosure of the present invention should fall
within the scope of the appended claims.
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