U.S. patent application number 14/449157 was filed with the patent office on 2014-11-20 for semiconductor device with oxygen-containing metal gates.
The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Cheng-Guo Chen, Yi-Wen Chen, Ying-Tsung Chen, Che-Hua Hsu, Shao-Hua Hsu, Tong-Jyun Huang, Wen-Han Hung, Guang-Yaw Hwang, Chien-Ming Lai, Zhi-Cheng Lee, Jiunn-Hsiung Liao, Po-Jui Liao, Chien-Ting Lin, Chun-Hsien Lin, Cheng-Yu Ma, Hung-Ling Shih, Tsung-Lung Tsai, Jung-Tsung Tseng, Jie-Ning Yang.
Application Number | 20140339652 14/449157 |
Document ID | / |
Family ID | 46965443 |
Filed Date | 2014-11-20 |
United States Patent
Application |
20140339652 |
Kind Code |
A1 |
Hwang; Guang-Yaw ; et
al. |
November 20, 2014 |
SEMICONDUCTOR DEVICE WITH OXYGEN-CONTAINING METAL GATES
Abstract
A semiconductor device with oxygen-containing metal gates
includes a substrate, a gate dielectric layer and a multi-layered
stack structure. The multi-layered stack structure is disposed on
the substrate. At least one layer of the multi-layered stack
structure includes a work function metal layer. The concentration
of oxygen in the side of one layer of the multi-layered stack
structure closer to the gate dielectric layer is less than that in
the side of one layer of the multi-layered stack structure opposite
to the gate dielectric layer.
Inventors: |
Hwang; Guang-Yaw; (Tainan
City, TW) ; Lin; Chun-Hsien; (Tainan City, TW)
; Shih; Hung-Ling; (Chiayi County, TW) ; Liao;
Jiunn-Hsiung; (Tainan City, TW) ; Lee; Zhi-Cheng;
(Tainan City, TW) ; Hsu; Shao-Hua; (Taoyuan
County, TW) ; Chen; Yi-Wen; (Tainan City, TW)
; Chen; Cheng-Guo; (Changhua County, TW) ; Tseng;
Jung-Tsung; (Tainan City, TW) ; Lin; Chien-Ting;
(Hsinchu City, TW) ; Huang; Tong-Jyun; (Tainan
City, TW) ; Yang; Jie-Ning; (Pingtung County, TW)
; Tsai; Tsung-Lung; (Tai-Nan City, TW) ; Liao;
Po-Jui; (Taichung City, TW) ; Lai; Chien-Ming;
(Tainan City, TW) ; Chen; Ying-Tsung; (Kaohsiung
City, TW) ; Ma; Cheng-Yu; (Tainan City, TW) ;
Hung; Wen-Han; (Kaohsiung City, TW) ; Hsu;
Che-Hua; (Hsinchu County, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsin-Chu City |
|
TW |
|
|
Family ID: |
46965443 |
Appl. No.: |
14/449157 |
Filed: |
August 1, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13082387 |
Apr 7, 2011 |
|
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14449157 |
|
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Current U.S.
Class: |
257/410 |
Current CPC
Class: |
H01L 29/517 20130101;
H01L 29/6656 20130101; H01L 29/6659 20130101; H01L 29/4966
20130101; H01L 29/513 20130101; H01L 29/7845 20130101; H01L 29/7833
20130101; H01L 29/7843 20130101; H01L 29/7846 20130101; H01L
29/66545 20130101; H01L 21/28088 20130101; H01L 21/823842 20130101;
H01L 21/823857 20130101 |
Class at
Publication: |
257/410 |
International
Class: |
H01L 29/51 20060101
H01L029/51; H01L 29/49 20060101 H01L029/49 |
Claims
1. A semiconductor device having a metal gate, comprising: a
substrate; a gate dielectric layer on the substrate; and a
multi-layered stack structure disposed on the gate dielectric
layer, wherein at least one layer of the multi-layered stack
structure comprises a work function metal layer, and a
concentration of oxygen in the side of one layer of the
multi-layered stack structure closer to the gate dielectric layer
is less than a concentration of oxygen in the side of one layer of
the multi-layered stack structure opposite to the gate dielectric
layer.
2. The semiconductor device having a metal gate according to claim
1, further comprising a metal layer disposed on the multi-layered
stack structure, wherein the metal layer and the multi-layered
stack structure together form a metal gate of the semiconductor
device.
3. The semiconductor device having a metal gate according to claim
1, wherein the multi-layered stack structure comprises two or more
than two layers of metal/metal nitride.
4. The semiconductor device having a metal gate according to claim
1, wherein the multi-layered stack structure comprises an etch stop
layer, a barrier layer or a work function metal layer.
5. The semiconductor device having a metal gate according to claim
4, wherein the etch stop layer comprises TiN, the barrier layer
comprises TaN and the work function metal layer comprises TiN.
6. The semiconductor device having a metal gate according to claim
1, wherein a dielectric constant of the gate dielectric layer is
substantially greater than 4, and the gate dielectric layer
comprises hafnium oxide (HfO.sub.2), hafnium silicon oxide
(HfSiO.sub.4), hafnium silicon oxynitride (HfSiON), aluminum oxide
(Al.sub.2O.sub.3), lanthanum oxide (La.sub.2O.sub.3), lanthanum
aluminum oxide (LaAlO), tantalum oxide (Ta.sub.2O.sub.5), zirconium
oxide (ZrO.sub.2), zirconium silicon oxide (ZrSiO.sub.4), hafnium
zirconium oxide (HfZrO), yttrium oxide (Yb.sub.2O.sub.3), yttrium
silicon oxide (YbSiO), zirconium aluminate (ZrAlO), hafnium
aluminate (HfAlO), aluminum nitride (AlN), titanium oxide
(TiO.sub.2), zirconium oxynitride (ZrON), hafnium oxynitride
(HfON), zirconium silicon oxynitride (ZrSiON), hafnium silicon
oxynitride (HfSiON), strontium bismuth tantalite
(SrBi.sub.2Ta.sub.2O.sub.9, SBT), lead zirconate titanate
(PbZr.sub.xTi.sub.1-xO.sub.3, PZT) or barium strontium titanate
(Ba.sub.xSr.sub.1-xTiO.sub.3, BST).
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a division of U.S. application Ser. No.
13/082,387, filed Apr. 7, 2011, the disclosure of which is
incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a metal gate, and more
particularly, to a metal gate with a multi-layered stack structure
and at least one layer of the multi-layered stack structure
includes oxygen.
[0004] 2. Description of the Prior Art
[0005] Poly-silicon is conventionally used as a gate electrode in
semiconductor devices, such as the metal-oxide-semiconductor (MOS).
However, with a trend toward scaling down the size of semiconductor
devices, the conventional poly-silicon gate has faced problems such
as inferior performance due to boron penetration and unavoidable
depletion effect which increases equivalent thickness of the gate
dielectric layer, reduces gate capacitance, and worsens a driving
force of the devices. Therefore, work function metals are used to
replace the conventional poly-silicon gate to be the control
electrode that are suitable for use as the high-K gate dielectric
layer.
[0006] In a complementary metal-oxide semiconductor (CMOS) device,
one of the dual work function metal gates is used in an NMOS device
and the other one is alternatively used in a PMOS device. It is
well-known that compatibility and process control for the dual
metal gate are more complicated, meanwhile thickness and
composition controls for materials used in the dual metal gate
method are more precise. The conventional dual metal gate methods
are categorized into gate first processes and gate last processes.
In a conventional dual metal gate method applied with the gate
first process, the annealing process for forming the source/drain
ultra-shallow junction, and the silicide process are performed
after forming the metal gate. In the conventional gate last
process, a sacrificial gate or a replacement gate is provided and
followed by performing processes used to construct a normal MOS
transistor. Then, the sacrificial/replacement gate is removed to
form a gate trench. Consequently, the gate trench is filled with
metals according to the different electrical requirements. However,
because of the complicated steps of the gate last processes, the
manufacturers are devoted to simplifying the manufacturing
process.
[0007] In the gate first process or the gate last process, the
metal gate of the PMOS or the NMOS may include a plurality of metal
layers. The materials of the metal layers always affect the work
function of the NMOS or the PMOS, therefore affect the performance
of the product. Thus, the manufacturers are searching for new
manufacturing method to obtain a MOS with better work function
performance.
SUMMARY OF THE INVENTION
[0008] To this end, according to one embodiment of the present
invention, a semiconductor device having a metal gate is provided.
The semiconductor device includes a substrate, a gate dielectric
layer and a multi-layered stack structure. The multi-layered stack
structure is disposed on the substrate. At least one layer of the
multi-layered stack structure includes a work function metal layer.
The concentration of oxygen in the side of one layer of the
multi-layered stack structure closer to the gate dielectric layer
is less than that in the side of one layer of the multi-layered
stack structure opposite to the gate dielectric layer.
[0009] One embodiment of the present invention provides a
semiconductor device with oxygen-containing metal gates. By using
the O.sub.2 ambience treatment during the fabrication process, the
work function of the metal gate can be improved and a product with
better performance can be obtained.
[0010] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 illustrates schematic diagrams of a first embodiment
of the flow chart of the method of fabricating a metal gate in the
present invention.
[0012] FIG. 2 and FIG. 3 illustrate schematic diagrams of a first
embodiment of the method of fabricating a metal gate in the present
invention.
[0013] FIG. 4 to FIG. 10 illustrate schematic diagrams of a second
embodiment of the method of fabricating a metal gate in the present
invention.
[0014] FIG. 11 to FIG. 19 illustrate schematic diagrams of a third
embodiment of the method of fabricating a metal gate in the present
invention.
[0015] FIG. 20 illustrates schematic diagram of an embodiment of
the method of fabricating a metal gate in the present
invention.
[0016] FIG. 21 illustrates schematic diagram of an embodiment of
the method of fabricating a metal gate in the present
invention.
DETAILED DESCRIPTION
[0017] To provide a better understanding of the presented
invention, preferred embodiments will be made in detail. The
preferred embodiments of the present invention are illustrated in
the accompanying drawings with numbered elements.
[0018] Please refer to FIG. 1 and in conjunction with FIG. 2 and
FIG. 3. FIG. 1 illustrates the first embodiment of the flow chart
of the method of fabricating a metal gate in the present invention.
FIG. 2 and FIG. 3 illustrate schematic diagrams of the first
embodiment of the schematic diagram of the method of fabricating a
metal gate in the present invention. As shown in FIG. 2, a
substrate 100 is provided (step 200). Then an interface layer 102
and a high-k layer 104 are formed on the substrate (step 202). The
interface layer 102 may include SiO2 which is formed by an
oxidation process for example. The high-k layer 104 may include
rare earth metal oxide or lanthanide oxide, such as hafnium oxide
(HfO.sub.2), hafnium silicon oxide (HfSiO.sub.4), hafnium silicon
oxynitride (HfSiON), aluminum oxide (Al.sub.2O.sub.3), lanthanum
oxide (La.sub.2O.sub.3), lanthanum aluminum oxide (LaAlO), tantalum
oxide (Ta.sub.2O.sub.5), zirconium oxide (ZrO.sub.2), zirconium
silicon oxide (ZrSiO.sub.4), hafnium zirconium oxide (HfZrO),
yttrium oxide (Yb.sub.2O.sub.3), yttrium silicon oxide (YbSiO),
zirconium aluminate (ZrAlO), hafnium aluminate (HfAlO), aluminum
nitride (AlN), titanium oxide (TiO.sub.2), zirconium oxynitride
(ZrON), hafnium oxynitride (HfON), zirconium silicon oxynitride
(ZrSiON), hafnium silicon oxynitride (HfSiON), strontium bismuth
tantalite (SrBi.sub.2Ta.sub.2O.sub.9, SBT), lead zirconate titanate
(PbZr.sub.xTi.sub.1-xO.sub.3, PZT) or barium strontium titanate
(Ba.sub.xSr.sub.1-xTiO.sub.3, BST), but is not limited thereto.
Next, a multi-layered stack structure 112 is formed on the high-k
layer 104 (step 204, step 206, step 208). The multi-layered stack
structure 112 includes two or more than two layers of metal/metal
nitride. In one embodiment, the multi-layered stack structure 112
includes a first layer 106 including TiN, a second layer 108
including TaN and a third layer 110 including TiN. Subsequently, a
conductive layer such as a metal layer 114 which has low resistance
is formed on the multi-layered stack structure 114 (step 210).
[0019] As shown in FIG. 3, a photo-etching-process is performed to
pattern the metal layer 114, the multi-layered stack structure 112,
the high-k layer 104 and the interface layer 102. The metal layer
114 and the multi-layered stack structure 112 together form a metal
gate 116, and the high-l layer 104 and the interface layer 102
together form a gate dielectric layer 101 (step 212). Next, a
source/drain region 118 is formed. Optionally, a stress formation
process, a silidation process or a CESL formation process can be
performed so as to complete the formation of the transistor
120.
[0020] In order to increase the performance of the transistor 120,
one salient feature of the present invention is to provide an
O.sub.2 ambience treatment to at least one layer of the
multi-layered stack structure 112. The O.sub.2 ambience treatment
may include using solvent having oxygen atom. As shown in FIG. 1,
after forming the first layer 106, an O.sub.2 ambience treatment
can be performed upon the first layer 106 (step 214). After forming
the second layer 108, an O.sub.2 ambience treatment can be
performed upon the second layer 108 (step 216). After forming the
third layer 110, an O.sub.2 ambience treatment can be performed
upon the third layer 110 (step 218). It is understood that the
method can be performed by choosing one or two or three of the step
214, step 216 and step 218. The O.sub.2 ambience treatment may
include an annealing process, a plasma treatment process or a
chemical treatment process. In one preferred embodiment, the
annealing process includes supplying gas containing O.sub.2 under
300.degree. C. to 500.degree. C., preferably 100% O.sub.2 gas under
400.degree. C. Plasma treatment process includes using plasma
containing O.sub.2. Chemical treatment includes using a chemical
solvent containing NH.sub.4OH, H.sub.2O.sub.2 and H.sub.2O, such as
SCl solvent. By using the abovementioned O.sub.2 ambience
treatment, at least one layer of the multi-layered stack structure
112 may include oxygen and the concentration of oxygen in the side
closer to the metal layer 114 is greater than that in the side
opposite from the metal layer 114.
[0021] The above-mentioned embodiment shows the gate first process.
It is understood that the present invention can also be applied to
the gate last process. Please refer to FIG. 4 to FIG. 10,
illustrating schematic diagrams of the second embodiment of the
method of fabricating a metal gate in the present invention. First,
a substrate 300 is provided, such as a silicon substrate, a
silicon-containing substrate or a silicon-on-insulator (SOI)
substrate. A plurality of shallow trench isolations (STI) 302 is
disposed on the substrate 300. In one embodiment, the STI 302 can
provide a stress. According to the areas encompassed by the STI
302, a first active region 400 and a second active region 500,
which are insulated from each other, are defined on the substrate
300. Then, a first conductive type transistor 402 and a second
conductive type transistor 502 are formed on the substrate 300
respectively in the first active region 400 and the second active
region 500. In one preferred embodiment of the present invention,
the first conductive type transistor 402 is a P-type transistor,
while the second conductive type transistor 502 is an N-type
transistor.
[0022] As shown in FIG. 4, the first conductive type transistor 402
includes a first interface layer 404, a first high-k layer 405, a
first etch stop layer 407, a first sacrificial gate 406, a first
capping layer 408, a first spacer 410, a first lightly doped drain
(LDD) 412 and a first source/drain 414. In one preferred embodiment
of the present invention, the first interface layer 404 can be a
SiO.sub.2 layer. The high-k gate dielectric layer includes
above-mentioned high-k material. The first etch stop layer 407
includes metal/metal nitride, such as TiN. The first sacrificial
gate 406 is a poly-silicon gate. In another embodiment, the first
sacrificial gate 406 is a multi-layered gate including a
poly-silicon layer, an amorphous silicon layer or a germanium
layer. In another embodiment, the sacrificial gate 406 may include
an inclined sidewall, thereby forming an "up-large-bottom-small"
structure. The first capping layer 408 is a SiN layer for example.
The first spacer 410 can be a multi-layered structure including
high temperature oxide (HTO), SiN, SiO or SiN formed by
hexachlorodisilane (Si.sub.2Cl.sub.6) (HCD-SiN). In one embodiment,
the first spacer 410 can be partially or completely removed to
produce a desired stress of the contact etch stop layer (CESL) 306
toward the first conductive type transistor 402 and the second
conductive type transistor 502. The first LDD 412 and the first
source/drain 414 are formed by appropriate implant doping.
[0023] The second conductive type transistor 502 includes a second
gate dielectric layer 504, a second sacrifice gate 506, a second
capping layer 508, a second spacer 510, a second LDD 512 and a
second source/drain 514. The embodiment of each component in the
second conductive type transistor 502 is similar to that of the
first conductive type transistor 402 and is not described
repeatedly. In addition, the first conductive type transistor 402
and the second conductive type transistor 502 can further include
other semiconductor structures which are not explicitly shown in
FIG. 4, such as a silicide layer, a source/drain having an hexagon
(also called sigma E) or octagon shaped cross-section which is
formed by selective epitaxial growth (SEG) , or other protective
films. After forming the first conductive type transistor 402 and
the second conductive type transistor 502, a contact etch stop
layer (CESL) 306 and an inter-layer dielectric (ILD) layer 308 are
formed on the substrate 300 to cover the first conductive type
transistor 402 and the second conductive type transistor 502. In
one embodiment, the CESL 306 can generate a stress to form a
selective strain scheme (SSS) wherein a compressing force is
applied on the first conductive type electrode 402 and a straining
force is applied on the second conductive type electrode 502.
[0024] As shown in FIG. 5, a planarization process, such as a
chemical mechanical polish (CMP) process or an etching-back process
or their combination is performed to remove a part of the ILD layer
308, a part of the CESL 306, a part of the first spacer 410, a part
of the second spacer 510, and completely remove the first capping
layer 408 and the second capping layer 508, until the top surface
of the first sacrificial gate 406 and the second sacrificial gate
506 are exposed.
[0025] As shown in FIG. 6, a wet etching process is performed to
remove the first sacrificial gate 406 and the second sacrificial
gate 506 until exposing the first etch stop layer 407 and the
second etch stop layer 507. A first trench 416 is formed in the
first conductive type transistor 402 and a second trench 516 is
formed in the second conductive type transistor 502. Then, an
O.sub.2 ambience treatment is performed on the exposed first etch
stop layer 407 and the exposed second etch stop layer 507,
simultaneously or respectively. In another embodiment, the O.sub.2
ambience treatment can also be performed when forming the first
etch stop layer 407 and the second etch stop layer 507. The O.sub.2
ambience treatment may include an annealing process, a plasma
treatment process or a chemical treatment process. In one preferred
embodiment, the annealing process includes supplying gas containing
O.sub.2 under 300.degree. C. to 500.degree. C., preferably 100%
O.sub.2 gas under 400.degree. C. Plasma treatment process includes
using plasma containing O.sub.2. Chemical treatment includes using
a chemical solvent containing NH.sub.4OH, H.sub.2O.sub.2 and
H.sub.2O, such as SCl solvent.
[0026] As shown in FIG. 7, a barrier layer 317 is formed on the
substrate 300. The barrier layer 317 is formed on the surface of
the first trench 416 and the second trench 516 where the first
trench 416 and the second trench 516 are not completely filled with
the barrier layer 317. The barrier layer 317 includes metal/metal
nitride, in one preferred embodiment, the barrier layer 317 in TaN.
Next, an O.sub.2 ambience treatment is performed to the barrier
layer 317. The O.sub.2 ambience treatment may include an annealing
process, a plasma treatment process or a chemical treatment
process. In one preferred embodiment, the annealing process
includes supplying gas containing O.sub.2 under 300.degree. C. to
500.degree. C., preferably 100% O.sub.2 gas under 400.degree. C.
Plasma treatment process includes using plasma containing O.sub.2.
Chemical treatment includes using a chemical solvent containing
NH.sub.4OH, H.sub.2O.sub.2 and H.sub.2O, such as SCl solvent. Next,
a P type work function metal layer 318 is formed on the barrier
layer 317. In the present embodiment, the P type work function
metal layer 318 serves as a work function metal required by a
P-type transistor including Ni, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, W,
Mo, or WN, RuN, MoN, TiN, TaN, or WC, TaC, TiC, or TiAlN, TaAlN,
but should not be limited thereto. The P type work function metal
layer 318 has a good etching ratio in respect to the barrier layer
317. Next, an O.sub.2 ambience treatment is performed on the P type
work function metal layer 318. The O.sub.2 ambience treatment may
include an annealing process, a plasma treatment process or a
chemical treatment process. In one preferred embodiment, the
annealing process includes supplying gas containing O.sub.2 under
300.degree. C. to 500.degree. C., preferably 100% O.sub.2 gas under
400.degree. C. for 1-5 minutes, preferably 2 minutes. Plasma
treatment process includes using plasma containing O.sub.2.
Chemical treatment includes using a chemical solvent containing
NH.sub.4OH, H.sub.2O.sub.2 and H.sub.2O, such as SCl solvent.
[0027] As shown in FIG. 8, the P type work function metal 318 is
patterned to remove the P type work function metal 318 in the
second active region 500. Since there is good etching selection
between the P type work function metal 318 and the barrier layer
317, the barrier layer 317 in the second active region 500 is not
removed. As shown in FIG. 9, an N type work function metal layer
322 is formed on the substrate 300. The N type work function metal
layer 322 is formed on the surface of barrier layer 317 in the
second trench 516 and on the surface of the P type work function
metal layer 318 in the first trench 416. However, the first trench
416 and the second trench 516 are not completely filled with the N
type work function metal layer 322. In one preferred embodiment of
the present invention, the second metal layer 324 serves as a work
function metal required by an N-type transistor including titanium
aluminides (TiAl), aluminum zirconium (ZrAl), aluminum tungsten
(WAl), aluminum tantalum (TaAl) or aluminum hafnium (HfAl), but
should not be limited thereto. Lastly, a low resistive metal layer
326 is formed on the substrate 300. The metal layer 326 is formed
on the N type work function metal layer 322 and completely fills
the first trench 416 and the second trench 516. The metal layer 326
includes Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W or Ti/TiN, but
is not limited thereto.
[0028] As shown in FIG. 10, a planarization process is performed to
simultaneously remove the P type work function metal layer 318, the
N type work function metal layer 322, the barrier layer 324 and the
metal layer 326 outside the first trench 416 and the second trench
516. Thus, the first etch stop layer 407, the barrier layer 317,
the P type work function metal layer 318, the N type work function
metal layer 322, and the metal layer 326 in the first trench 416
together form a first metal gate 418 of the first conductive type
transistor 402 (P-type transistor), which has a work function
substantially between 4.8 eV and 5.2 eV. The second etch stop layer
507, the barrier layer 317, the N type work function metal layer
322 and the metal layer 326 in the second trench 516 together form
a second metal gate 518 of the second conductive type transistor
502 (N-type transistor) which has a work function substantially
between 3.9 eV and 4.3 eV. Because an O.sub.2 ambience treatment is
performed to the first etch stop layer 407, the second etch stop
layer 507, the barrier layer 317 and the P type work function metal
layer 318, the first metal gate 418 and the second metal gate 518
can have a better work function.
[0029] After finishing the first metal gate 418 and the second
metal gate 518, a contact plug forming process can be carried out,
for example, a contact plug having a stress can be formed. In
another embodiment, before forming the contact plug, the ILD layer
306 and the CESL 308 can be removed completely. Then, at least one
CESL (not shown) can be formed on the substrate 300. By applying a
UV or a heat energy, the new CSEL can generate a stress, thereby
enhancing the efficiency of the first conductive type transistor
402 and the second conductive type transistor 502, respectively.
Another ILD layer (not shown) is then formed and at least a contact
plug having appropriate stress can be formed therein.
[0030] It should be noted that the above methods present forming
the high-k gate dielectric layer at first (namely, the high-K first
process). However, those skilled in the art can realize that, in
the present invention, it is also available to form the high-k
layer 405 after removing the sacrificial gate (namely, the high-K
last process). For example, as shown in FIG. 20, a high-K layer 405
can be formed on the surface of the first trench 416 before forming
the P type work function metal layer 318. Subsequently, the P type
work function metal layer 318 and the metal layer 326 are formed on
the high-K gate dielectric layer 405 in the first trench 416. In
this embodiment, the high-K gate dielectric layer 405 and the P
type work function metal layer 318 will form a U shape in their
cross section. In another embodiment, it is also available to form
a high-K gate dielectric layer on the surface of the second trench
516 before forming the N type work function metal layer 322. Then,
the N type work function metal layer 322 and the metal layer 326
are formed on the high-K gate dielectric layer in the second trench
516. In this embodiment, the high-K gate dielectric layer and the N
type work function metal layer 322 will form a U shape in their
cross section. In addition, when the invention is performed in the
high-k last process, the material of the dielectric layer formed
under the sacrifice gate is not limited to high-k material but can
include another dielectric material such as SiO.sub.2.
[0031] Please refer to FIG. 11 to FIG. 19, illustrating a third
embodiment of the method of fabricating a metal gate in the present
invention. The former steps of the second embodiment are similar to
those in FIG. 1 to FIG. 2 of the first embodiment and repeated
descriptions are omitted. As shown in FIG. 11, a mask layer 312 and
an optional auxiliary layer 314 are formed on the substrate 300. In
one preferred embodiment of the present invention, the mask layer
312 is a TiN layer, and the auxiliary layer 314 is a SiO.sub.2
layer. The auxiliary layer 314 can provide a better adhesive force
toward the first patterned photoresist layer 316 which is formed in
the follow-up step. In one embodiment, the thickness of the mask
layer 312 is about 50 to 100 A (angstrom), preferably 100 A, and
the thickness of the auxiliary layer 314 is about 0 to 50 A,
preferably 20 A. However, the thickness is not limited thereto.
Then, a first patterned photoresist layer 316 is formed on the
substrate 300 to cover at least the second active region 500.
[0032] As shown in FIG. 12, by using the first patterned
photoresist layer 316 as a mask, a portion of the mask layer 312,
the auxiliary layer 314 and the first sacrificial gate 406 not
covered by the first patterned photoresist layer 316 are removed,
thereby forming a first trench 416. The second sacrificial gate 506
of the second conductive type transistor 502 is not removed since
it is covered by the mask layer 312. Then, an O.sub.2 ambience
treatment is performed to the first etch stop layer 407. The
O.sub.2 ambience treatment may include an annealing process, a
plasma treatment process or a chemical treatment process. In one
preferred embodiment, the annealing process includes supplying gas
containing O.sub.2 under 300.degree. C. to 500.degree. C.,
preferably 100% O.sub.2 gas under 400.degree. C.. Plasma treatment
processes include using plasma containing O.sub.2. Chemical
treatment includes using a chemical solvent containing NH.sub.4OH,
H.sub.2O.sub.2 and H.sub.2O, such as SCl solvent. Then, a P type
work function metal layer 318 is formed on the substrate 300. The P
type work function metal layer 318 is formed on the surface of the
first trench 416. However, the first trench 416 is not completely
filled with the P type work function metal layer 318. In the
present embodiment, the P type work function metal layer 318 serves
as a work function metal required by a P-type transistor including
Ni, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, W, Mo, or WN, RuN, MoN, TiN,
TaN, or WC, TaC, TiC, or TiAlN, TaAlN, but should not be limited
thereto. The P type work function metal layer 318 has a good
etching ratio in respect to the barrier layer 317. Next, an O.sub.2
ambience treatment is performed to the P type work function metal
layer 318. The O.sub.2 ambience treatment may include an annealing
process, a plasma treatment process or a chemical treatment
process. In one preferred embodiment, the annealing process
includes supplying gas containing O.sub.2 under 300.degree. C. to
500.degree. C., preferably 100% O.sub.2 gas under 400.degree. C.,
for 1-5 minutes, preferably 2 minutes. Plasma treatment process
includes using plasma containing O.sub.2. Chemical treatment
includes using a chemical solvent containing NH.sub.4OH,
H.sub.2O.sub.2 and H.sub.2O, such as SCl solvent.
[0033] In another embodiment of the present invention, the first
etch stop layer 407 can be removed. Please refer to FIG. 13,
illustrating another embodiment of the method of fabricating the
metal gate in the present invention. As shown in FIG. 13, the first
etch stop layer 407 can be removed and then the P type work
function metal layer 318 is formed. In this embodiment, the P type
work function metal layer 318 can directly contact the first high-k
layer 405.
[0034] As shown in FIG. 14, an organic layer 320 is formed on the
substrate 300. The organic layer 320 at least fills into the first
trench 416. In one embodiment, the organic layer 320 may include
spin-on glass (SOG), bottom anti-reflective coating (BARC layer),
or photoresist layer. As shown in FIG. 15, by using a patterning
process or an etching process, the organic layer 320 outside the
first trench 416 is removed. As shown in FIG. 16, another etching
process is performed to remove a part of the P type work function
metal layer 318 and a part of the organic layer 320 in the first
trench 416. The remained P type work function metal layer 318 in
the first trench therefore forms a U type feature in a
cross-section and the most top portion of the U type feature is
lower than the opening of the first trench 416. That is, the
opening of the first trench 416 is not covered by the P type work
function metal layer 318. As shown in FIG. 17, the organic layer
320 in the first trench 416 is removed. In one embodiment, the
process of removing the organic layer 320 includes using a plasma
containing O.sub.2/H.sub.2/N.sub.2, and the concentration of
O.sub.2 is less than 10%. After removing the organic layer 320, the
process can be continued to further provide the treatment upon the
P type work function metal layer 318.
[0035] As shown in FIG. 11, the second sacrificial gate 506 is
removed by using a dry etching process and/or a wet etching
process, thereby forming a second trench 516 in the second
conductive type transistor 502. Subsequently, an N type work
function metal layer 322 is formed on the substrate 300. The N type
work function metal layer 322 is formed on the surface of the
second trench 516 and on the surface of the P type work function
metal layer 318 in the first trench 416. However, the first trench
416 and the second trench 516 are not completely filled with the N
type work function metal layer 322. In one preferred embodiment of
the present invention, the second metal layer 324 serves as a work
function metal required by an N-type transistor including titanium
aluminides (TiAl), aluminum zirconium (ZrAl), aluminum tungsten
(WAl), aluminum tantalum (TaAl) or aluminum hafnium (HfAl), but
should not be limited thereto. Lastly, a low resistive metal layer
326 is formed on the substrate 300. The metal layer 326 is formed
on the N type work function metal layer 322 (if the barrier layer
324 is utilized, the metal layer 326 is formed on the barrier layer
324) and completely fills the first trench 416 and the second
trench 516. The metal layer 326 includes Al, Ti, Ta, W, Nb, Mo,
TiN, TiC, TaN, Ti/W or Ti/TiN, but is not limited thereto.
[0036] As shown in FIG. 19, a planarization process is performed to
simultaneously remove the P type work function metal layer 318, the
N type work function metal layer 322 and the metal layer 326
outside the first trench 416 and the second trench 516. Thus, the
first etch stop layer 407, the P type work function metal layer
318, the N type work function metal layer 322, and the metal layer
326 in the first trench 416 together forma first metal gate 418 of
the first conductive type transistor 402 (P-type transistor), which
has a work function substantially between 4.8 eV and 5.2 eV. The
second etch stop layer 507, the N type work function metal layer
322 and the metal layer 326 in the second trench 516 together form
a second metal gate 518 of the second conductive type transistor
502 (N-type transistor) which has a work function substantially
between 3.9 eV and 4.3 eV. Because an O.sub.2 ambience treatment is
performed to the first etch stop layer 407, the second etch stop
layer 507, the barrier layer 317 and the P type work function metal
layer 318, the first metal gate 418 and the second metal gate 518
can have better work functions. Besides, in one embodiment, the P
type work function metal layer 318 around the opening of the first
trench 416 is removed, so the metal layer 324 can have better gap
filling ability.
[0037] After finishing the first metal gate 418 and the second
metal gate 518, a contact plug forming process can be carried out,
for example, a contact plug having a stress can be formed. In
another embodiment, before forming the contact plug, the ILD layer
306 and the CESL 308 can be removed completely. Then, at least one
CESL (not shown) can be formed on the substrate 300. By applying a
UV or a heat energy, the new CSEL can generate a stress, thereby
enhancing the efficiency of the first conductive type transistor
402 and the second conductive type transistor 502, respectively.
Another ILD layer (not shown) is then formed and at least a contact
plug having appropriate stress can be formed therein.
[0038] It should be noted that the above methods present forming
the high-k gate dielectric layer at first (namely, the high-K first
process). However, those skilled in the art can realize that, in
the present invention, it is also available to form the high-k
layer 405 after removing the sacrificial gate (namely, the high-K
last process). For example, as shown in FIG. 21, a high-K layer 405
can be formed on the surface of the first trench 416 before forming
the P type work function metal layer 318. Subsequently, the P type
work function metal layer 318 and the metal layer 326 are formed on
the high-K gate dielectric layer 405 in the first trench 416. In
this embodiment, the high-K gate dielectric layer 405 and the P
type work function metal layer 318 will form a U shape in their
cross section. In another embodiment, it is also available to form
a high-K gate dielectric layer on the surface of the second trench
516 before forming the N type work function metal layer 322. Then,
the N type work function metal layer 322 and the metal layer 326
are formed on the high-K gate dielectric layer in the second trench
516. In this embodiment, the high-K gate dielectric layer and the N
type work function metal layer 322 will form a U shape in their
cross section. In addition, when the invention is performed in the
high-k last process, the material of the dielectric layer formed
under the sacrifice gate is not limited to high-k material but can
include another dielectric material such as SiO.sub.2.
[0039] In summary, a semiconductor device with oxygen-containing
metal gates is provided according to one embodiment of the present
invention provides. By using the O.sub.2 ambience treatment during
the fabrication process, the work function of the metal gate can be
improved and a product with better performance can be obtained.
[0040] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
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