U.S. patent application number 14/266433 was filed with the patent office on 2014-10-23 for semiconductor package and semiconductor device.
This patent application is currently assigned to Advanced Semiconductor Engineering, Inc.. The applicant listed for this patent is Advanced Semiconductor Engineering, Inc.. Invention is credited to Pao-Huei CHANG CHIEN, Chi-Chih CHU, Cheng-Yin LEE, Wei-Yueh SUNG, Gwo-Liang WENG, Yen-Yi WU.
Application Number | 20140312496 14/266433 |
Document ID | / |
Family ID | 39224055 |
Filed Date | 2014-10-23 |
United States Patent
Application |
20140312496 |
Kind Code |
A1 |
WU; Yen-Yi ; et al. |
October 23, 2014 |
SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE
Abstract
The present invention relates to a semiconductor package and a
semiconductor device and a method of making the same. The method of
making the semiconductor package comprises: providing a substrate;
attaching a chip to a surface of the substrate; forming a plurality
of connecting elements for electrically connecting the chip and the
substrate; forming a plurality of first conductive bodies on the
surface of the substrate; forming a molding compound for
encapsulating the surface of the substrate, the chip, the
connecting elements and the first conductive bodies; and removing a
part of a border portion of the molding compound, so that the
molding compound has two heights and one end of each first
conductive bodies is exposed. Thereby, the molding compound covers
the entire surface of the substrate, so that the bonding pads on
the surface of the substrate will not be polluted.
Inventors: |
WU; Yen-Yi; (Kao-Hsiung
City, TW) ; SUNG; Wei-Yueh; (Ping-Tung City, TW)
; CHIEN; Pao-Huei CHANG; (Kaohsiung County, TW) ;
CHU; Chi-Chih; (Kao-Hsiung City, TW) ; LEE;
Cheng-Yin; (Tai-Nan City, TW) ; WENG; Gwo-Liang;
(Kao-Hsiung City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Advanced Semiconductor Engineering, Inc. |
Kaohsiung |
|
TW |
|
|
Assignee: |
Advanced Semiconductor Engineering,
Inc.
Kaohsiung
TW
|
Family ID: |
39224055 |
Appl. No.: |
14/266433 |
Filed: |
April 30, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11828351 |
Jul 26, 2007 |
|
|
|
14266433 |
|
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Current U.S.
Class: |
257/738 |
Current CPC
Class: |
H01L 23/3128 20130101;
H01L 2225/1023 20130101; H01L 2924/00014 20130101; H01L 2924/181
20130101; H01L 2924/15321 20130101; H01L 2224/73265 20130101; H01L
2924/181 20130101; H01L 2924/00014 20130101; H01L 24/14 20130101;
H01L 2924/1815 20130101; H01L 2224/1405 20130101; H01L 2224/73265
20130101; H01L 25/105 20130101; H01L 2924/00014 20130101; H01L
2224/48091 20130101; H01L 2924/00012 20130101; H01L 23/49816
20130101; H01L 24/73 20130101; H01L 24/48 20130101; H01L 2224/48091
20130101; H01L 2924/12042 20130101; H01L 2224/48227 20130101; H01L
2224/32225 20130101; H01L 2924/00014 20130101; H01L 2924/00012
20130101; H01L 2224/32225 20130101; H01L 2224/45099 20130101; H01L
2224/45015 20130101; H01L 2924/00 20130101; H01L 2924/207 20130101;
H01L 2224/48227 20130101; H01L 21/56 20130101; H01L 2225/1058
20130101; H01L 25/50 20130101; H01L 2924/01079 20130101; H01L
2924/12042 20130101; H01L 2924/15331 20130101 |
Class at
Publication: |
257/738 |
International
Class: |
H01L 23/00 20060101
H01L023/00 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 27, 2006 |
TW |
095135866 |
Claims
1-19. (canceled)
20. A semiconductor package, comprising: a substrate including a
top patterned conductive layer at a top surface of the substrate,
the top patterned conductive layer defining a plurality of top
pads; a plurality of conductive components positioned on
corresponding ones of the top pads; a chip positioned on the top
surface of the substrate and electrically connected to the top
patterned conductive layer; and a molding compound encapsulating
the chip, the top patterned conductive layer, and the plurality of
conductive components, wherein: the molding compound extends
laterally to edges of the substrate; the molding compound at a
central portion of the substrate has a first height, and the
central portion extends beyond a periphery of the chip; the molding
compound in a border area between the central portion and the edges
of the substrate has a second height less than half of the first
height; and the molding compound in the border area exposes and is
coplanar with a top surface of at least one of the plurality of
conductive components.
21. The semiconductor package of claim 20, wherein the top pads are
arranged in multiple rows surrounding the chip.
22. The semiconductor package of claim 20, wherein the conductive
components are arranged in multiple rows surrounding the chip.
23. The semiconductor package of claim 20, wherein the conductive
components include solder.
24. The semiconductor package of claim 20, wherein the bottom
patterned conductive layer is substantially coplanar with the
bottom surface of the substrate.
25. The semiconductor package of claim 20, wherein each of the
conductive components has a hemispherical shape.
26. The semiconductor package of claim 20, wherein a top surface
extending across the border area includes cut marks.
27. A semiconductor device, comprising: a semiconductor package
including a chip, conductive components, and a molding compound
including a central portion and a border portion, wherein: the
central portion fully encapsulates the chip, and the central
portion has a first height greater than the height of the chip; the
border portion extends between the central portion and an external
periphery of the package, and wherein: the border portion has a
second height less than the first height, a top surface across the
extent of the border portion includes marks incurred by removal of
a portion of the molding compound, and the top surface exposes the
conductive components embedded in the molding compound.
28. The semiconductor device of claim 27, wherein the second height
is less than half of the first height.
29. The semiconductor device of claim 27, further comprising solder
balls at a lower surface of the semiconductor package.
30. The semiconductor device of claim 27, further comprising a
substrate and a patterned conductive layer, wherein the chip is
positioned on the substrate and is electrically connected to the
patterned conductive layer, and the conductive components are
positioned on pads defined by the patterned conductive layer.
31. The semiconductor device of claim 27, wherein the semiconductor
package is a first package, further comprising a second package
stacked on the first package, and the second package is
electrically coupled to the first package through the conductive
components.
32. The semiconductor device of claim 31, wherein the second
package is electrically coupled to the first package through the
conductive components by way of a plurality of solder balls
positioned at a lower surface of the second package and contacting
respective ones of the conductive components.
33. A method of forming a stackable package, comprising:
positioning conductive elements on respective top pads in a top
surface of a substrate; mounting a chip on the top surface of the
substrate; applying a molding compound over the top surface of the
substrate to a first height, including applying the molding
compound over the chip, the top pads, and the conductive elements;
and cutting the molding compound in a border area around a
circumference of the package to a second height less than the first
height, wherein the second height is less than an original height
of the conductive elements, and wherein the conductive elements are
exposed in the border area by the cutting.
34. The method of claim 33, wherein the cutting includes removing a
part of each of the conductive elements, such that at least one of
the conductive elements has a hemispherical shape.
35. The method of claim 33, wherein subsequent to the cutting, the
molding compound in a central area has the first height.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 11/828,351, filed on Jul. 26, 2007, which
claims the benefit of Taiwan Patent Application No. 095135866,
filed on Sep. 27, 2006, the disclosures of which are incorporated
herein by reference in their entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor package and
a method of making the same, and particularly to a semiconductor
package comprising a molding compound with different heights and a
semiconductor device comprising the semiconductor package and
methods of making the same.
[0004] 2. Description of the Prior Art
[0005] Please refer to FIG. 1 showing a schematic diagram of a
conventional semiconductor device consisting of stacked packages.
The conventional semiconductor device 1 comprises a first package
10 and a second package 20. The first package 10 comprises a first
substrate 11, a first chip 12, a plurality of first conductive
wires 13, a first molding compound 14, and a plurality of first
solder balls 15. The first substrate 11 has an upper surface 111, a
lower surface 112, and a plurality of first pads 113. The first
pads 113 are disposed on the upper surface 111 of the first
substrate 11. The first chip 12 is adhered to the upper surface 111
of the first substrate 11 and electrically connected to the upper
surface 111 of the first substrate 11 by the first conductive wires
13. The first molding compound 14 encapsulates the first chip 12,
the first conductive wires 13, and a part of the upper surface 111
of the first substrate 11, and the first pads 113 are exposed. The
first solder balls 15 are on the lower surface 112 of the first
substrate 11.
[0006] The second package 20 is stacked on the first package 10.
The second package 20 comprises a second substrate 21, a second
chip 22, a plurality of second conductive wires 23, a second
molding compound 24, and a plurality of second solder balls 25. The
second substrate 21 has an upper surface 211, a lower surface 212,
and a plurality of second pads 213. The second pads 213 are
disposed on the lower surface 212 of the second substrate 21. The
second chip 22 is adhered to the upper surface 211 of the second
substrate 21 and electrically connected to the upper surface 211 of
the second substrate 21 by the second conductive wires 23. The
second molding compound 24 encapsulates the second chip 22, the
second conductive wires 23, and the upper surface 211 of the second
substrate 21. The upper ends of the second solder balls 25 are
connected to the second pads 213 on the lower surface 212 of the
second substrate 21, and the lower ends are connected to the first
pads 113 on the upper surface 111 of the first substrate 11.
[0007] One of the drawbacks of the conventional semiconductor
device 1 is that the area encapsulated by the first molding
compound 14 in the first package 10 is smaller than that
encapsulated by the second molding compound 24 in the second
package 20. As a result, two different molds are required in the
molding processes for the first package 10 and the second package
20. The cost is high for making a mold. Molds of different sizes
are often needed for molding processes to make different package
devices. Accordingly, the production cost will be dramatically
increased. Moreover, in the first package 10, there is an included
angle of about 60 degrees between the sidewall of the first molding
compound 14 and the first substrate 11. The included angle is
namely the draft angle of the mold. Furthermore, the top surface of
the first molding compound 14 has a mold insert gate mark. In
addition, in the molding process for the first package 10, the
first molding compound 14 tends to overflow onto the upper surface
111 of the first substrate 11 to pollute the first pads 113.
[0008] Therefore, it is necessary to provide a novel and
progressive semiconductor package and semiconductor device and
method of making the same to solve the aforesaid problems.
SUMMARY OF THE INVENTION
[0009] One main objective of the present invention is to provide a
method of making a semiconductor package comprising the following
steps of: providing a first substrate having a first surface and a
second surface; attaching a first chip to the first surface of the
first substrate; forming a plurality of first connecting elements
for electrically connecting the first chip and the first substrate;
forming a plurality of first conductive bodies on the first surface
of the first substrate; forming a first molding compound for
encapsulating the first surface of the first substrate, the first
chip, the first connecting elements, and the first conductive
bodies; and removing a part of a border portion of the first
molding compound, so that the first molding compound has at least
two heights and one end of each of the first conductive bodies is
exposed.
[0010] Another objective of the present invention is to provide a
semiconductor package, which comprises a substrate, a chip, a
plurality of connecting elements, a plurality of first conductive
bodies, and a molding compound. The substrate has a first surface
and a second surface. The chip is attached to the first surface of
the substrate. The connecting elements electrically connect the
chip and the substrate. The first conductive bodies are disposed on
the first surface of the substrate. The molding compound
encapsulates the first surface of the substrate, the chip, the
connecting elements, and the first conductive bodies. The molding
compound has at least two heights and one end of each of the first
conductive bodies is exposed. Thereby, the molding compound
encapsulates the entire first surface of the substrate, and the
pads on the first surface will not be polluted.
[0011] Still another objective of the present invention is to
provide a semiconductor device, which comprises a first package and
a second package. The first package is the semiconductor package as
described above. The second package is stacked on the first
package. In an embodiment, the size of the second package is the
same as that of the first package. Thus, only one mold is required
to perform both the molding processes for the second package and
the first package. Accordingly, the production cost will be
reduced.
[0012] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 shows a schematic diagram of a conventional
semiconductor device consisting of stacked packages;
[0014] FIG. 2 shows a flow chart of the method of making a
semiconductor device according to the present invention; and
[0015] FIGS. 3 to 8 show schematic step by step diagrams
illustrating the method of making a semiconductor device according
to the present invention.
DETAILED DESCRIPTION
[0016] Please refer to FIG. 2 showing a flow chart of the method of
making a semiconductor device according to the present invention.
Also refer to FIG. 3. In Step S201, a first substrate 31 is
provided. The first substrate 31 has a first surface 311, a second
surface 312, a plurality of first pads 313, and a plurality of
second pads 314. The first pads 313 are on the first surface 311,
and the second pads 314 are on the second surface 312. In Step
S202, a first chip 32 is attached to the first surface 311 of the
first substrate 31. In this embodiment, a first chip 32 is attached
to the first surface 311 of the first substrate 31. In Step S203, a
plurality of first connecting elements (such as a plurality of
first conductive wires 33) electrically connect the first chip 32
and the first surface 311 of the first substrate 31. In Step 204, a
plurality of first conductive bodies (such as a plurality of first
solder balls 34) are formed on the first pads 313 on the first
surface 311 of the first substrate 31. In this embodiment, the
first conductive bodies may be solder balls; however, it may be
realized that the first conductive bodies can be solder bumps, gold
stud bumps, or metal pins and each in a shape of pillar or column,
in addition to a shape of ball.
[0017] It should be noted that, in other applications, after Step
S201 is performed, Step S204 is performed and followed by Step S202
and Step S203. That is, the first conductive bodies (such as the
first solder balls) may be formed on the first pads 313 on the
first surface 311 of the first substrate 31 before the first chip
32 is attached to the first surface 311 of the first substrate 31.
Thereafter, the first conductive elements (such as the first
conductive wires 33) are formed for electrically connecting the
first chip 32 and the first surface 311 of the first substrate
31.
[0018] Please refer to FIG. 2 and FIG. 4. In Step S205, a first
molding compound 35 for encapsulating the first surface 311 of the
first substrate 31, the first chip 32, the first conductive wires
33, and the first solder balls 34. It should be noted that the
first molding compound 35 encapsulates the entire first surface 311
of the first substrate 31. In this embodiment, the top surface of
the first molding compound 35 is higher than the top of the first
solder balls 34; however, it may be realized that the top surface
of the first molding compound 35 can be at the same height with the
top of the first solder balls 34, or the top surface of the first
molding compound 35 can be lower than the top of the first solder
balls 34.
[0019] The included angle between the sidewall of the first molding
compound 35 and the first substrate 31 is about 85 to 95 degrees,
and preferably 90 degrees, because the draft angle is almost not
needed for the mold in the present invention. Furthermore, in the
present invention, a plurality of the first chips 32 may be
encapsulated with the first molding compound 35 and thereafter
divided into a plurality of packages having a shape like tofu.
Thereby, the top surface of the first molding compound 35 in the
packages will not have a mold insert gate mark.
[0020] Please refer to FIG. 2 and FIG. 5. In Step S206, a plurality
of second solder balls 36 are formed on the second pads 314 on the
second surface 312 of the first substrate 31. It should be noted
that this step is an optional step.
[0021] Please refer to FIG. 2 and FIG. 6. In Step S207, a part of a
border portion of the first molding compound 35 is removed, so that
the first molding compound 35 has at least two heights and one end
of each of the first solder balls 34 is exposed to make a first
package 3. The removal in this step may be accomplished by laser
cutting, chemical etching, cutting with a cutting tool, or cutting
with a water jet. In this step of this embodiment, the way of
cutting with a cutting tool is used to remove the upper part 351 of
the border portion of the first molding compound 35, and the lower
part 352 of the border portion is remained. The central portion 353
of the first molding compound 35 is not cut away and is entirely
remained.
[0022] Therefore, after the cutting, the molding compound 35 has a
first height H.sub.1, a second height H.sub.2, a central portion
353, a lower part 352 of a border portion, a first top surface 354,
and a second top surface 355. The first height Hi is the height of
the central portion 353 corresponding to the positions of the first
chip 32 and the first conductive wires 33. The second height
H.sub.2 is the height of the lower part 352 of the border portion
corresponding to the positions of the first solder balls 34. The
first height Hi is greater than the second height H.sub.2. The
first top surface 354 is corresponding to the first height H.sub.1,
that is, the first top surface 354 is the top surface of the
central portion 353. The first top surface 354 has a first surface
roughness. The second top surface 355 is corresponding to the
second height H.sub.2, that is, the second top surface 355 is the
top surface of the lower part 352 of the border portion. The second
top surface 355 has a second surface roughness. The first surface
roughness is different from the second surface roughness.
[0023] Please refer to FIG. 7 showing a top view of FIG. 6. The
second top surface 355 is a cutting surface and has a plurality of
cutting lines 37 after the cutting. In the embodiment, the upper
parts of the first solder balls 34 are removed along with the
removal of the upper part 351 of the border portion of the first
molding compound 35. Therefore, only the lower parts of the first
solder balls 34 are remained to form a hemispherical shape (as
shown in FIG. 6). Furthermore, all the part of the molding compound
35 and the parts of the first solder balls 34 included in the
second top surface 355 have the cutting lines 37. As shown in FIG.
7, the cutting lines 37 located at each of the four sides of the
second top surface 355 are substantially parallel, and the cutting
lines 37 located in each of the four corners of the second top
surface 355 perpendicularly cross each other, since the four
corners of the second top surface 355 are cut twice.
[0024] Please still refer to FIG. 6 showing a schematic diagram the
first package of the present invention. The first package 3
comprises a first substrate 31, a first chip 32, a plurality of
first connecting elements (such as a plurality of first conductive
wires 33), a plurality of first conductive bodies (such as a
plurality of first solder balls 34), a first molding compound 35,
and a plurality of second solder balls 36. The first substrate 31
has a first surface 311, a second surface 312, a plurality of first
pads 313 on the first surface 311, and a plurality of second pads
314 on the second surface 312. The first chip 32 is attached to the
first surface 311 of the first substrate 31. In this embodiment,
the first chip 32 is attached to the first surface 311 of the first
substrate 31. The first conductive wires 33 electrically connect
the first chip 32 and the first substrate 31. The first solder
balls 34 are in a hemispherical shape and disposed on the first
pads 313 of the first surface 311 of the first substrate 31. The
second solder balls 36 are disposed on the second pads 314 of the
second surface 312 of the first substrate 31.
[0025] The molding compound 35 encapsulates the first surface 311
of the first substrate 31, the first chip 32, the first conductive
wires 33, and the first solder balls 34. The molding compound 35
has a first height H.sub.1, a second height H.sub.2, a central
portion 353, a lower part 352 of a border portion, a first top
surface 354, and a second top surface 355. The first height Hi is
the height of the central portion 353 corresponding to the
positions of the first chip 32 and the first conductive wires 33.
The second height H.sub.2 is the height of the lower part 352 of
the border portion corresponding to the positions of the first
solder balls 34. The first height H.sub.1 is greater than the
second height Hz. The first top surface 354 is corresponding to the
first height H.sub.1, that is, the first top surface 354 is the top
surface of the central portion 353. The first top surface 354 has a
first surface roughness. The second top surface 355 is
corresponding to the second height H.sub.2, that is, the second top
surface 355 is the top surface of the lower part 352 of the border
portion. The second top surface 355 has a second surface roughness.
The first surface roughness is different from the second surface
roughness.
[0026] Please refer to FIG. 7. In this embodiment, the second top
surface 355 is a cutting surface and has a plurality of cutting
lines 37 after the cutting. Furthermore, all the part of the
molding compound 35 and the parts of the first solder balls 34
included in the second top surface 355 have the cutting lines 37.
As shown in FIG. 7, the cutting lines 37 located at each of the
four sides of the second top surface 355 are parallel, and the
cutting lines 37 located in each of the four corners of the second
top surface 355 perpendicularly cross each other, since the four
corners of the second top surface 355 are cut twice.
[0027] Please refer to FIG. 2 and FIG. 8. In Step S208, a second
package 4 is stacked on the first solder balls 34 and electrically
connected to the first solder balls 34, to make a semiconductor
device 5. The second package 4 may be any kind of semiconductor
packages. In this embodiment, the second package 4 comprises a
second substrate 41, a second chip 42, a plurality of second
conductive wires 43, a second molding compound 44, and a plurality
of third solder balls 45. The second substrate 41 has a first
surface 411 and a second surface 412. The second chip 42 is
attached to the first surface 411 of the second substrate 41. The
second conductive wires 43 electrically connect the second chip 42
and the second substrate 41. The second molding compound 44
encapsulates the first surface 411 of the second substrate 41, the
second chip 42, and the second conductive wires 43. The third
solder balls 45 are disposed on the second surface 412 of the
second substrate 41 and electrically connected to the first solder
balls 34.
[0028] In this embodiment, the size of the second molding compound
44 of the second package 4 is the same as that of the first molding
compound 35 of the first package 3. Thus, only one molding machine
is required to perform both the molding processes for the second
package 4 and the first package 3. As a result, the production cost
can be reduced. In addition, in the molding process for the first
package 3, the first molding compound encapsulates the entire first
surface 311 of the first substrate 31, and accordingly the pads on
the first surface 311 are not polluted.
[0029] Please still refer to FIG. 8, showing a schematic diagram of
the semiconductor device according to the present invention. The
semiconductor device 5 comprises a first package 3 and a second
package 4. The second package 4 is stacked on the first package 3.
The first package 3 comprises a first substrate 31, a first chip
32, a plurality of first connecting elements (such as a plurality
of first conductive wires 33), a plurality of first conductive
bodies (such as a plurality of first solder balls 34), a first
molding compound 35, and a plurality of second solder balls 36. The
first substrate 31 has a first surface 311, a second surface 312, a
plurality of first pads 313 on the first surface 311, and a
plurality of second pads 314 on the second surface 312. The first
chip 32 is attached to the first surface 311 of the first substrate
31. The first conductive wires 33 electrically connect the first
chip 32 and the first substrate 31. The first solder balls 34 are
in a hemispherical shape and disposed on the first pads 313 of the
first surface 311 of the first substrate 31.
[0030] The molding compound 35 encapsulates the first surface 311
of the first substrate 31, the first chip 32, the first conductive
wires 33, and the first solder balls 34. The molding compound 35
has a first height H.sub.1, a second height H.sub.2, a central
portion 353, a lower part 352 of a border portion, a first top
surface 354, and a second top surface 355. The first height H.sub.1
is the height of the central portion 353 corresponding to the
positions of the first chip 32 and the first conductive wires 33.
The second height H.sub.2 is the height of the lower part 352 of
the border portion corresponding to the positions of the first
solder balls 34. The first height Hi is greater than the second
height H.sub.2. The first top surface 354 is corresponding to the
first height H.sub.1, that is, the first top surface 354 is the top
surface of the central portion 353. The first top surface 354 has a
first surface roughness. The second top surface 355 is
corresponding to the second height H.sub.2, that is, the second top
surface 355 is the top surface of the lower part 352 of the border
portion. The second top surface 355 has a second surface roughness.
The first surface roughness is different from the second surface
roughness.
[0031] Please also refer to FIG. 7. In this embodiment, the second
top surface 355 is a cutting surface and has a plurality of cutting
lines 37 after the cutting. Furthermore, all the part of the
molding compound 35 and the parts of the first solder balls 34
included in the second top surface 355 have the cutting lines 37.
As shown in FIG. 7, the cutting lines 37 located at each of the
four sides of the second top surface 355 are parallel, and the
cutting lines 37 located in each of the four corners of the second
top surface 355 perpendicularly cross each other, since the four
corners of the second top surface 355 are cut twice.
[0032] The second package 4 comprises a second substrate 41, a
second chip 42, a plurality of second conductive wires 43, a second
molding compound 44, and a plurality of third solder balls 45. The
second substrate 41 has a first surface 411 and a second surface
412. The second chip 42 is attached to the first surface 411 of the
second substrate 41. The second conductive wires 43 electrically
connect the second chip 42 and the second substrate 41. The second
molding compound 44 encapsulates the first surface 411 of the
second substrate 41, the second chip 42, and the second conductive
wires 43. The third solder balls 45 are disposed on the second
surface 412 of the second substrate 41 and electrically connected
to the first solder balls 34.
[0033] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention.
* * * * *