U.S. patent application number 14/253690 was filed with the patent office on 2014-08-14 for substrate having a charged zone in an insulating buried layer.
This patent application is currently assigned to Soitec. The applicant listed for this patent is Soitec. Invention is credited to Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure, Mohamad A. Shaheen.
Application Number | 20140225182 14/253690 |
Document ID | / |
Family ID | 39952212 |
Filed Date | 2014-08-14 |
United States Patent
Application |
20140225182 |
Kind Code |
A1 |
Shaheen; Mohamad A. ; et
al. |
August 14, 2014 |
SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER
Abstract
A substrate comprises a base wafer, an insulating layer over the
base wafer, and a top semiconductor layer over the insulating layer
on a side thereof opposite the base wafer. The insulating layer
comprises a charge-confining layer confined on one or both sides
with diffusion barrier layers, wherein the charge-confining layer
has a density of charges in absolute value higher than 10.sup.10
charges/cm.sup.2. Alternatively, the insulating layer comprises
charge-trapping islands embedded therein, wherein the
charge-trapping islands have a total density of charges in absolute
value higher than 10.sup.10 charges/cm.sup.2.
Inventors: |
Shaheen; Mohamad A.;
(Portland, OR) ; Allibert; Frederic; (Grenoble,
FR) ; Gaudin; Gweltaz; (Grenoble, FR) ;
Lallement; Fabrice; (Grenoble, FR) ; Landru;
Didier; (Champ Pres Froges, FR) ; Landry; Karine;
(Grenoble, FR) ; Mazure; Carlos; (Bernin,
FR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Soitec |
Crolles Cedex |
|
FR |
|
|
Assignee: |
Soitec
Crolles Cedex
FR
|
Family ID: |
39952212 |
Appl. No.: |
14/253690 |
Filed: |
April 15, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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14027528 |
Sep 16, 2013 |
8735946 |
|
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14253690 |
|
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|
12865838 |
Aug 2, 2010 |
8535996 |
|
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PCT/IB2008/052203 |
Mar 13, 2008 |
|
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14027528 |
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Current U.S.
Class: |
257/324 |
Current CPC
Class: |
H01L 31/0248 20130101;
H01L 29/78603 20130101; H01L 29/7841 20130101; H01L 29/32
20130101 |
Class at
Publication: |
257/324 |
International
Class: |
H01L 29/786 20060101
H01L029/786 |
Claims
1. A substrate, comprising: a base wafer; an insulating layer over
the base wafer, the insulating layer comprising a charge-confining
layer confined on one or both sides with one or more diffusion
barrier layers, the charge-confining layer having a density of
charges in absolute value higher than 10.sup.10 charges/cm.sup.2;
and a top semiconductor layer over the insulating layer on a side
thereof opposite the base wafer.
2. The substrate of claim 1, wherein the insulating layer comprises
a material selected from the group consisting of silicon oxide,
silicon nitride, and a high k material.
3. The substrate of claim 1, wherein the charge-confining layer
comprises silicon nitride, and the one or more diffusion barrier
layers includes at least one diffusion barrier layer comprising
silicon oxide.
4. The substrate of claim 1, wherein the charge-confining layer
comprises silicon oxide, and the one or more diffusion barrier
layers includes at least one diffusion barrier layer comprising
silicon nitride.
5. The substrate of claim 1, wherein the insulating layer comprises
an oxide-nitride-oxide (ONO) structure.
6. The substrate of claim 1, wherein the charges are at least
partially provided by ions.
7. The substrate of claim 6, wherein the charges are negative and
the ions are selected from the group consisting of fluorine ions
and chlorine ions.
8. The substrate of claim 6, wherein the charges are positive and
the ions are selected from the group consisting of boron ions and
phosphorous ions.
9. The substrate of claim 1, wherein the charge-confining layer
comprises a doped charge-confining layer, and wherein the dopant is
selected from the group consisting of boron, phosphorour, chlorine
and fluorine.
10. The substrate of claim 1, wherein the charge-confining layer
has a thickness in a range extending from approximately 10
angstroms to approximately 1,000 angstroms.
11. The substrate of claim 1, wherein each of the one or more
diffusion barrier layers has a thickness in a range extending from
approximately 10 angstroms to approximately 500 angstroms.
12. The substrate of claim 1, wherein the charge-confining layer
comprises ions uniformly dispersed therein.
13. The substrate of claim 1, wherein the charge-confining layer
comprises ions concentrated around a determined depth within the
charge-confining layer.
14. A substrate, comprising: a base wafer; an insulating layer over
the base wafer, the insulating layer comprising charge-trapping
islands embedded therein, wherein the charge-trapping islands have
a total density of charges in absolute value higher than
10.sup.1.degree. charges/cm.sup.2; and a top semiconductor layer
over the insulating layer on a side thereof opposite the base
wafer.
15. The substrate of claim 14, wherein the charge-trapping islands
comprise silicon.
16. The substrate of claim 14, wherein the insulating layer has a
thickness in a range extending from approximately 10 angstroms to
approximately 5,000 angstroms.
17. The substrate of claim 14, wherein the insulating layer
comprises a material selected from the group consisting of silicon
oxide, silicon nitride, and a high k material.
18. The substrate of claim 14, wherein the charges are at least
partially provided by ions.
19. The substrate of claim 8, wherein the charges are negative and
the ions are selected from the group consisting of fluorine ions
and chlorine ions.
20. The substrate of claim 14, wherein the charges are at least
partially provided by electrons.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of U.S. patent
application Ser. No. 14/027,528, filed Sep. 16, 2013, pending,
which is a continuation of U.S. patent application Ser. No.
12/865,838, filed Aug. 2, 2010 and issued on Sep. 17, 2013 as U.S.
Pat. No. 8,535,996, which is a national phase entry under 35 U.S.C.
.sctn.371 of International Patent Application PCT/IB2008/052203,
filed Mar. 13, 2008, published in English as International Patent
Publication WO 2009/112894 A1 on Sep. 17, 2009, the entire
disclosure of each of which is hereby incorporated herein by this
reference.
TECHNICAL FIELD
[0002] The invention relates to a substrate comprising a base
wafer, an insulating layer and a top semiconductor layer, that can
be used in electronic devices, notably in memories.
BACKGROUND
[0003] DRAM memory is typically made of one transistor and one
capacitor cell (1T1C). While the transistor functions as pass, the
capacitor is used for charge storage. The capacitor can be either a
trench configuration or a stacked capacitor. A certain novel class
of DRAM memories can be comprised of only one transistor, without
the need for a capacitor, and hence is referred to as capacitorless
DRAM, 1T, or 1T-RAM. Such memory types are usually based on
Semiconductor-on-Insulator (SeOI)-like substrates, where the
transistor, through its floating body characteristics, acts as both
control transitory and charge storage device. Examples of such type
are the "Floating Body Cell" (FBC), or the "zero-capacitor RAM"
(zRAM) though other variations exist.
[0004] A typical 1T memory is illustrated in FIG. 1.
[0005] The SeOI substrate comprises from its base to its top a base
wafer 10, an insulating layer 20 and a top semiconductor layer 30,
also called a "useful layer."
[0006] The memory device is made of transistors made on the
semiconductor useful layer 30. The source S and drain D are made in
the useful layer 30, whereas the gate G is deposited on an
insulating layer on the useful layer 30.
[0007] For a certain class of 1T memory that requires back-bias,
such as the FBC, an electrode E is also installed on the rear side
of the substrate, i.e., on the base wafer 10.
[0008] During operation of the 1T memory, charges (holes) are
injected from the channel near the drain region via impact
ionization into the body of the transistor. The presence of these
positive charges shifts the Vt of the transistor lower and changes
the current-voltage characteristics. This shift is used to detect
or "read" the state of the cell, being either "1" or "0."
[0009] 1T memory being a volatile memory, a periodic refresh is
carried out in order to restore charge, and hence programming
state, to the transistor. Charge is mainly lost through various
leakage mechanisms, and the rate of charge loss determines the
retention time of the memory cell. If such time is short, extensive
refreshing is needed resulting in high power consumption and poor
yield. Therefore, it is highly desirable to extend the retention
time of the cell, i.e., charge retention in the transistor as much
as practical. To that end, a rear electrode E can be used to apply
a negative voltage in order to keep the charges in the transistor
body as long as possible, e.g., near a back interface in the 1T
design.
[0010] However, the installation of the rear electrode E requires
additional processing and complex circuits that makes it
expensive.
[0011] There is thus a need for a SeOI-like substrate that allows
increasing the retention time of the 1T memories, at a lower
cost.
BRIEF SUMMARY
[0012] A first object of the invention is a substrate comprising
successively a base wafer, an insulating layer and a top
semiconductor layer, characterized in that the insulating layer
comprises at least a zone wherein the density of charges is in
absolute value higher than 10.sup.10 charges/cm.sup.2.
[0013] "Zone" is meant here either as the whole insulating layer
itself, or a layer forming part of the insulating layer, or
discrete islands embedded in the insulating layer.
[0014] According to a first embodiment of the invention, the
insulating layer is made of a material chosen among the group
consisting of silicon oxide, silicon nitride or high-k
materials.
[0015] According to a second embodiment, the insulating layer
comprises a charge-confining layer between two diffusion barrier
layers, wherein the charge-confining layer has a density of charges
in absolute value higher than 10.sup.10 charges/cm.sup.2.
Preferably, the charge-confining layer is made of silicon nitride
and the diffusion barrier layers are made of silicon oxide.
Alternatively, the charge-confining layer is made of silicon oxide
and the diffusion barrier layers are made of silicon nitride.
[0016] According to a third embodiment of the invention, the
insulating layer comprises charge-trapping islands, wherein the
charge-trapping islands have a total density of charges in absolute
value higher than 10.sup.10 charges/cm.sup.2. The insulating layer
is advantageously made of silicon oxide and the charge-trapping
islands are made of silicon.
[0017] The charges comprised in the insulating layer are preferably
at least partially provided by ions. A first possibility is that
the density of charges is negative and the ions are chosen among
the group consisting of fluorine and chlorine ions. A second
possibility is that the density of charges is positive and the ions
are chosen among the group consisting of boron and phosphor
ions.
[0018] A second object of the invention is a semiconductor
structure comprising a 1TRAM memory, comprising a floating body
region on an insulating layer, wherein the insulating layer
comprises a zone exhibiting a density of charges in absolute value
higher than 10.sup.10 charges/cm.sup.2.
[0019] A third object of the invention relates to a process for
manufacturing a substrate comprising successively a base wafer, an
insulating layer and a top semiconductor layer, characterized in
that it includes the step of charging at least a zone of the
insulating layer so that the zone exhibits a density of charges in
absolute value higher than 10.sup.10 charges/cm.sup.2.
[0020] According to a first embodiment of the process, the charging
step comprises doping the insulating layer.
[0021] According to another embodiment, the charging step comprises
implanting ions in the insulating layer through the top
semiconductor layer.
[0022] Alternatively, the process comprises the steps of: [0023]
forming the insulating layer on the base wafer or on a donor wafer;
[0024] bonding the base wafer and the donor wafer, the insulating
layer being at an interface; and the charging step is carried out
before the bonding step.
[0025] The charging step may comprise an electron bombardment of
the insulating layer, or a plasma treatment of the insulating
layer.
[0026] Alternatively, the step of forming the insulating layer
comprises forming a first diffusion barrier layer, a
charge-confining layer and a second diffusion barrier layer.
[0027] The charging step can comprise a plasma activation of the
charge-confining layer.
[0028] In a variant, the charging step comprises growing a doped
charge-confining layer, wherein the dopant is chosen among the
group consisting of boron, phosphor, chlorine and fluorine, and the
concentration of the dopant is higher than 10.sup.10/cm.sup.2.
[0029] The charge-confining layer is preferably made of silicon
nitride and the diffusion barrier layers are made of silicon
oxide.
[0030] According to another embodiment of the invention, the
process comprises, prior to the bonding step, forming
charge-trapping islands in the insulating layer. For instance, the
charge-trapping islands are made of silicon.
[0031] A fourth object of the invention is a process for charging
the insulating layer of a substrate comprising successively a base
substrate, an insulating layer and a top semiconductor layer,
characterized in that the insulating layer comprises atomic species
with a density higher than 10.sup.10 atoms/cm.sup.2, wherein the
atomic species are able to change into ions under injection of
charged carriers into the insulating layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Other characteristics, objects, and advantages of the
invention will appear clearer in reading the description below,
which is illustrated by the following figures:
[0033] FIG. 1 shows a 1T memory according to the prior art;
[0034] FIG. 2 illustrates the steps for making a SeOI substrate
with the SMART CUT.RTM. process;
[0035] FIG. 3 illustrates a first embodiment of the SeOI-like
substrate according to the invention;
[0036] FIG. 4 illustrates a second embodiment; and
[0037] FIG. 5 illustrates a third embodiment of the invention.
DETAILED DESCRIPTION
[0038] The general idea of the invention is to replace a rear
electrode with a charge located in an SeOI-like structure, under an
interface between a useful layer and an insulating layer. A
negatively charged insulating layer plays the same role as the rear
electrode, i.e., creating a negative voltage in the SeOI structure
for retaining the holes near the insulating layer.
[0039] Conversely, a positively charged insulating layer is able to
retain electrons, in certain types of 1TRAM, which utilize PMOS
transistors and hence electron charge.
Standard Structure
[0040] A standard substrate of the SeOI type is provided. Such a
structure comprises a base wafer 1, an insulating layer 2 and a top
layer 3.
[0041] The base wafer 1 can made of a bulk or composite
material.
[0042] The insulating layer 2 is made of a material having
electrically insulating properties. "Insulating layer" is meant in
this text as a single layer or a stack of different materials
having dielectric properties.
[0043] The insulating layer 2 is usually an oxide, such as silicon
oxide (SiO.sub.2). In this case, it is usually called "BOX" (Buried
Oxide layer).
[0044] The insulating layer 2 can also made of silicon nitride, an
oxide-nitride combination, or of a "high-k" material, such as
hafnium oxide.
[0045] The thickness of the insulating layer is typically between
10 and 5000 angstroms.
[0046] The top semiconductor layer 3, also called "useful" or
"active" layer, is made of a semiconductor material, such as
silicon.
[0047] Such a SeOI substrate can be made by a SMART CUT.RTM.
process, or by any other possible process.
[0048] The SMART CUT.RTM. process is described in detail in U.S.
Pat. No. 5,374,564.
[0049] Referring to FIG. 2, it typically comprises the following
steps: [0050] a) Providing a base wafer 1 and a donor wafer 4 made
of a semiconductor material; [0051] b) Oxidizing one or both of the
wafers--preferably the donor wafer 4, thus creating the insulating
layer 2 on the donor wafer 4; [0052] c) Implanting ions in the
donor wafer 4 in order to create a weakness zone 40 at a depth
corresponding to the thickness of the active layer 3; [0053] d)
Bonding the donor wafer 4 to the base wafer 1 with the insulating
layer 2 at the interface; and [0054] e) Splitting the donor wafer 4
according to the weakness zone 40, thus, transferring the top layer
3 to the base wafer 1.
[0055] The insulating layer 2 has a density of charges in absolute
value higher than 10.sup.10 charges/cm.sup.2, for example, higher
than 10.sup.11 charges/cm.sup.2.
[0056] This charge can be measured using a pseudo-MOS technique or
mercury-FET measurement.
[0057] The density of charges is positive when the charges are
positive (such as holes); the density of charges is negative when
the charges are negative (such as electrons).
[0058] It must be noted that the buried oxide layer in a
conventional SeOI-like substrate is usually slightly charged but
this charge is minimized in order to avoid electrical losses in the
base wafer, as explained, for example, in application US
2006/0166451.
[0059] In the following description, it is assumed that the charges
that have to be retained near the insulating layer are holes (i.e.,
positive) and thus that the insulating layer has to be negatively
charged. Other retention modes such as in the transistor body or
near the top channel can benefit from a similar approach.
[0060] However, the invention applies conversely to the problem of
retaining electrons near the insulating layer using a positively
charged insulating layer.
First Embodiment
Charged BOX Layer
[0061] In this embodiment, the charged zone is the insulating layer
itself.
[0062] The insulating layer 2 is preferably made of silicon oxide:
it can thus be called "BOX."
[0063] Referring to FIG. 3, the charged BOX layer 2 typically
comprises ions such as chlorine or fluorine.
[0064] If the BOX layer 2 is intended to be positively charged, it
comprises ions such as boron or phosphor.
[0065] Provided that the process targets a full activation of the
ions, the density of ions is similar to the density of charges.
[0066] The ions can be spread uniformly within the BOX layer.
[0067] Alternatively, they can be concentrated around a determined
depth inside the BOX layer.
[0068] The ions can be implanted in the insulating layer after
forming the SeOI substrate (through the top layer 3), or before the
bonding of the donor wafer and the base wafer.
[0069] During the implantation step, ions are implanted inside the
insulating layer. The skilled person is able to adjust the
parameters of implantation (namely dose and energy of the ions) in
order to obtain an implantation profile with a maximum
concentration at a determined depth, inside the insulating
layer.
[0070] Implant energies can be in the range of 1 keV to 300 keV,
for example, 10 keV-100 keV, and the dose can be in the range of
10.sup.13 to 10.sup.17 atoms/cm.sup.2.
[0071] Typically, one type of species is implanted, but more than
one can be used if specific chemical compounds are needed.
[0072] Alternatively, a plasma treatment can be carried out on the
insulating layer 2 before bonding the donor wafer 4 (FIG. 2) and
the base wafer 1.
[0073] The conditions of such a plasma treatment are typically: a
power between 300 W and 1 kW, for instance 535 W, a pressure
between 10 and 500 mT, typically about 50 mT, a flow from 100 sccm
to 300 sccm, preferably about 200 sccm, a temperature of between
23.degree. C. and 30.degree. C., preferably 27.degree. C., and a
process time from 3 seconds to 60 seconds, typically about 30
seconds.
[0074] Alternatively, electron bombardment of the layer 2, in the
configuration where it is a surface layer of a wafer, directly
before bonding, can impart negative charge to this layer 2.
Second Embodiment
The Charged Zone is a Charge-Confining Layer Between Diffusion
Barrier Layer(s)
[0075] In reference to FIG. 4, the SeOI substrate can
advantageously comprise an insulating layer 2 comprised of a
charge-confining layer 5, confined on one or both sides with
diffusion barrier layers 6 made of a material that is able to
prevent the diffusion of ions or charges within the substrate.
[0076] To prevent diffusion and hence dissipation of the charge,
both top and bottom barrier layers 6 are needed.
[0077] For instance, a charge-confining layer 5 made of silicon
oxide is between two barrier layers 6 made of silicon nitride. This
configuration is particularly useful when the negative ions are
fluorine, which diffuse in SiO.sub.2.
[0078] Alternatively, the charge-confining layer 5 may be made of
silicon nitride and the barrier layers 6 are made of silicon
oxide.
[0079] This structure can be made by constructing the
charge-confining layer 5, and barrier layers 6, prior to bonding,
on either donor wafer 4 (FIG. 2) or base wafer 1.
[0080] The insulating layer 2 can be constructed fully on one wafer
before bonding, by depositing successively a first barrier layer 6,
the charge-confining layer 5, and a second barrier layer 6.
[0081] Alternatively, a first barrier layer 6 and the
charge-confining layer 5 can be deposited on one of the wafers, the
second barrier layer 6 being deposited on the other wafer. The
wafers are then bonded with the charge-confining layer 5 at an
interface.
[0082] The implication of either arrangement is the use of
oxide-to-silicon bonding versus oxide-to-oxide bonding.
[0083] The barrier layers 6 can be made by thin film deposition
such as LPCVD or PECVD with thicknesses in the range of 10
angstroms to 500 angstroms.
[0084] The charge-confining layer 5 is preferably formed, prior to
bonding, by plasma activation of a layer deposited on a barrier
layer.
[0085] Alternatively, the charge-confining layer 5 can be formed by
depositing a doped layer of oxide or nitride on a wafer having a
deposited insulating layer (namely the first barrier layer 6), by a
technique such as LPCVD (low pressure chemical vapor deposition),
or PECVD (plasma enhanced chemical vapor deposition), prior to
bonding to a second wafer with a top insulating layer (namely the
second barrier layer 6).
[0086] The charged doped layer 5 is thus embedded in the two
insulating layers 6.
[0087] The dopant is chosen among boron, phosphor, chlorine and
fluorine, with a dopant concentration higher than
10.sup.10/cm.sup.2, for example, higher than
10.sup.11/cm.sup.2.
[0088] The thickness of the charge-confining layer 5 can be on the
order of 10 angstroms to 1000 angstroms.
[0089] The stack 6, 5, 6 of FIG. 4 is also known as "ONO"
("Oxide-Nitride-Oxide"). It is, for instance, used in a certain
type of 1T memory, named "SOONO" (Silicon-On-ONO), and also in
non-volatile Flash memories; however, in this case this stack is
not a buried insulating layer but is a floating-gate insulating
layer and it is not charged.
Third Embodiment
The Charged Zone Consists of Embedded Charge-Trapping Islands
[0090] As compared to the second embodiment where the charge is
uniformly distributed in the charge-confining layer 5, in this
third embodiment, the charge is localized in islands 7 embedded in
the insulating layer 2. This configuration is shown in FIG. 4.
[0091] The islands 7 can be formed by implantation of the desired
ion, such as chlorine or fluorine, into the insulating layer 2 with
some critical dose that may be followed by an anneal during which
precipitation and formation of nuclei of the Si--F (for example)
phase is formed.
[0092] This implantation step can be carried out before or after
bonding, and implies the same doses as in the first embodiment.
[0093] Alternatively, silicon can be implanted in an insulating
layer made of SiO.sub.2 or Si.sub.3N.sub.4, thus forming
charge-trapping islands 7 made of silicon.
[0094] Also, growth of a doped charge layer followed by annealing
is more suitable due to control of dopant concentration directly
through thin film deposition.
[0095] If the islands 7 are not charged while they are formed, they
can be charged later. For example, it is possible to inject
electrons in the islands 7, either by applying a high voltage to
the structure or bombarding it with electrons.
[0096] Another possibility is to implant ions in the islands 7.
Fourth Embodiment
Ferroelectric Material
[0097] According to a fourth embodiment of the invention, the
insulating layer of the SeOI substrate comprises a ferroelectric
material, such as oxides of lead and zirconium and/or titanium
Pb(Zr.sub.x, Ti.sub.1-x)O.sub.3 with x between 0 and 1.
[0098] Alternatively, the insulating layer is made of a stack of
such ferroelectric materials.
[0099] Indeed, ferroelectric materials have the property of
exhibiting a spontaneous dipole moment and, hence, to create a
permanent electric field in the substrate.
[0100] The electric field must be oriented such as to accumulate
holes at the interface between the insulating layer and the top
layer.
Fifth Embodiment
Electrically Active Defects in the Insulating Layer
[0101] Another possibility is to create electrically active defects
in or at the insulating layer, for instance, defects resulting in a
charge density of interface traps (DITs) between the insulating
layer and the adjacent layer.
[0102] Following the fabrication of the structure of the substrate,
additional electrical charge may be injected into the insulating
layer--for instance, by implantation, or by applying an electrical
field by means of electrode plates put into close contact with the
substrate. The charge may thus be trapped by the atomic species,
which become ions according to the above example. Such charge
injection may, for instance, be applied in order to tune the charge
level.
[0103] In principle, such an SeOI substrate is expected to have a
permanent density of charges during the whole life duration of the
FBC memory.
[0104] However, it must be noted that, depending on the techniques
used, the charges in the insulating layer might be dissipated, for
example, during the fabrication of the transistor on the SeOI
substrate.
[0105] Indeed, the fabrication process involves thermal treatments
at higher temperatures--typically at 600.degree. C. or
greater--such that the charges are dissipated.
[0106] In such a case also, charge injection as described above may
be used for tuning the charge level and, for example, restoring the
initial charge level.
[0107] For example, the atomic species that had been implanted into
the insulating layer may become neutral, but remain in the
insulating layer.
[0108] The insulating layer thus keeps a feature (i.e., the
presence of atomic species) that distinguishes it from the known
SeOI substrates, and is able to be charged again, after the
fabrication of the transistor.
[0109] The SeOI substrate with a charged insulating layer that has
been described above can be used for making a 1TRAM memory. To that
end, the source and drain of the transistor are made in the top
semiconductor layer, whereas the gate is deposited on an insulating
layer on the top semiconductor layer.
[0110] If necessary, i.e., if the charges of the insulating layer
have been dissipating during the fabrication of the transistor, a
step of charging again the insulating layer can be carried out.
[0111] This 1T device then comprises an insulating layer whose
density of charges is substantially permanent during the whole
lifetime of the device.
[0112] Also, the charged insulating layer and the SeOI substrate
are generally provided before the devices are formed in the top
layer, but it is also possible, for instance, in the case of 3D
integration of devices, to first form the device in an initial
substrate and then form the SeOI substrate of the invention by
transferring a top portion of this initial substrate onto a base
wafer, with the charged insulating layer being positioned in
between.
[0113] The SeOI substrate with a charged insulating layer that has
been described above can also be used for other type of
applications, like, for instance, as a substrate for receiving or
comprising image sensor devices. As mentioned in U.S. Pat. No.
5,227,313, for such an application it is usual to dope, for
instance, with boron, the top layer of a SeOI substrate in order to
form electrical potential that will drive the photogenerated
charges toward the sensor itself. But the formation of appropriate
boron concentration profile across the thickness of the top layer
could be problematic. For instance, it should be taken into account
diffusion of the dopant that will occur during the sensor devices'
manufacturing steps that involve exposure of the substrate to
relatively high temperatures. This problem could be advantageously
solved by replacing the boron doping, or completing a reduced boron
doping of the top layer by the charged insulating layer according
to the invention. In that case, the type of charge would be
selected to drive away the photogenerated charges from the top
layer/insulating layer interface toward the active elements of the
image sensor devices. In "backside lighting" applications, the base
wafer of the SeOI substrate could be selected to be transparent
(e.g., made of glass or quartz); or it can be eliminated after the
formation of the sensor devices, as described in U.S. Pat. No.
5,244,817.
* * * * *