U.S. patent application number 14/170295 was filed with the patent office on 2014-05-29 for flip chip interconnection structure.
This patent application is currently assigned to STATS ChipPAC, Ltd.. The applicant listed for this patent is STATS ChipPAC, Ltd.. Invention is credited to Rajendra D. Pendse.
Application Number | 20140145340 14/170295 |
Document ID | / |
Family ID | 26884225 |
Filed Date | 2014-05-29 |
United States Patent
Application |
20140145340 |
Kind Code |
A1 |
Pendse; Rajendra D. |
May 29, 2014 |
Flip Chip Interconnection Structure
Abstract
A flip chip interconnection structure is formed by mechanically
interlocking joining surfaces of a first and second element. The
first element, which may be a bump on an integrated circuit chip,
includes a soft, deformable material with a low yield strength and
high elongation to failure. The surface of the second element,
which may for example be a substrate pad, is provided with
asperities into which the first element deforms plastically under
pressure to form the mechanical interlock.
Inventors: |
Pendse; Rajendra D.;
(Fremont, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STATS ChipPAC, Ltd. |
Singapore |
|
SG |
|
|
Assignee: |
; STATS ChipPAC, Ltd.
Singapore
SG
|
Family ID: |
26884225 |
Appl. No.: |
14/170295 |
Filed: |
January 31, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13175694 |
Jul 1, 2011 |
8697490 |
|
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14170295 |
|
|
|
|
10849947 |
May 20, 2004 |
7994636 |
|
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13175694 |
|
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|
|
09802664 |
Mar 9, 2001 |
6815252 |
|
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10849947 |
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60188570 |
Mar 10, 2000 |
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Current U.S.
Class: |
257/762 ;
257/750; 257/766; 438/622 |
Current CPC
Class: |
H01L 23/53228 20130101;
H01L 2224/81385 20130101; H01L 2224/81193 20130101; H01L 2224/13147
20130101; H01L 24/83 20130101; H01L 21/76838 20130101; H01L
2224/16237 20130101; H01L 2224/16225 20130101; H01L 2224/1411
20130101; H01L 24/90 20130101; Y10T 428/24917 20150115; H01L
2224/81194 20130101; H01L 2924/01079 20130101; H01L 2224/1134
20130101; H01L 2924/14 20130101; H01L 24/16 20130101; H01L
2224/13144 20130101; H01L 2224/17107 20130101; H01L 2224/13099
20130101; H01L 23/522 20130101; H01L 2224/81345 20130101; H01L
2224/1601 20130101; H01L 2924/01006 20130101; H01L 2224/83192
20130101; H01L 2224/838 20130101; H01L 2924/014 20130101; H01L
2924/01029 20130101; H01L 2924/01082 20130101; H01L 2224/16
20130101; H01L 23/53242 20130101; H01L 2224/16238 20130101; H05K
3/325 20130101; H01L 2224/16225 20130101; H01L 2224/13144 20130101;
H01L 2924/00 20130101; H01L 2224/16225 20130101; H01L 2224/13147
20130101; H01L 2924/00 20130101; H01L 2924/3512 20130101; H01L
2924/00 20130101; H01L 2224/16 20130101; H01L 2924/00012
20130101 |
Class at
Publication: |
257/762 ;
438/622; 257/766; 257/750 |
International
Class: |
H01L 23/522 20060101
H01L023/522; H01L 23/532 20060101 H01L023/532; H01L 21/768 20060101
H01L021/768 |
Claims
1. A method of making a semiconductor device, comprising: providing
a semiconductor die; forming an interconnect structure over the
semiconductor die; providing a substrate including an interconnect
pad; and bonding the interconnect structure over the semiconductor
die and interconnect pad by deforming the interconnect structure
around the interconnect pad.
2. The method of claim 1, further including maintaining a vertical
separation between the semiconductor die and substrate.
3. The method of claim 1, further including deforming the
interconnect structure to reduce relative movement between the
semiconductor die and substrate.
4. The method of claim 1, further including deforming the
interconnect structure about 25 micrometers.
5. The method of claim 1, further including forming a width of the
interconnect pads to be less than a width of the interconnect
structure.
6. The method of claim 1, further including depositing an adhesive
resin between the semiconductor die and substrate.
7. A method of making a semiconductor device, comprising: providing
a semiconductor die; providing a substrate including an
interconnect pad; and forming an interconnect structure over the
semiconductor die and around the interconnect pad.
8. The method of claim 7, further including maintaining a vertical
separation between the semiconductor die and substrate.
9. The method of claim 7, further including deforming the
interconnect structure into a surface of the interconnect pad to
reduce relative movement between the semiconductor die and
substrate.
10. The method of claim 7, wherein the interconnect structure
includes gold, copper, or nickel.
11. The method of claim 7, further including deforming the
interconnect structure about 25 micrometers.
12. The method of claim 7, further including forming a width of the
interconnect pad to be less than a width of the interconnect
structure.
13. The method of claim 7, further including depositing an adhesive
resin between the semiconductor die and substrate.
14. A semiconductor device, comprising: a semiconductor die; an
interconnect structure formed over the semiconductor die; and a
substrate including an interconnect pad, the interconnect structure
deformed onto the interconnect pad.
15. The semiconductor device of claim 14, further including a
vertical separation maintained between the semiconductor die and
substrate.
16. The semiconductor device of claim 14, wherein the interconnect
structure is deformed about 25 micrometers.
17. The semiconductor device of claim 14, wherein the deformation
of the interconnect structure occurs along a sidewall of the
interconnect structure.
18. The semiconductor device of claim 14, wherein the interconnect
structure includes gold, copper, or nickel.
19. The semiconductor device of claim 14, wherein a width of the
interconnect pad is less than a width of the interconnect
structure.
20. A semiconductor device, comprising: a substrate; an
interconnect pad formed over the substrate; and an interconnect
structure deformed over the interconnect pad.
21. The semiconductor device of claim 20, further including: a
semiconductor die disposed over the substrate; and a vertical
separation maintained between the semiconductor die and
substrate.
22. The semiconductor device of claim 20, wherein the interconnect
structure is deformed about 25 micrometers.
23. The semiconductor device of claim 20, wherein the deformation
of the interconnect structure occurs along a sidewall of the
interconnect structure.
24. The semiconductor device of claim 20, wherein the interconnect
structure includes gold, copper, or nickel.
25. The semiconductor device of claim 20, wherein a width of the
interconnect pad is less than a width of the interconnect
structure.
Description
CLAIM OF DOMESTIC PRIORITY
[0001] The present application is a continuation of U.S. patent
application Ser. No. 13/175,694, filed Jul. 1, 2011, which is a
continuation of U.S. patent application Ser. No. 10/849,947, now
U.S. Pat. No. 7,994,636, filed May 20, 2004, which is a division of
U.S. patent application Ser. No. 09/802,664, now U.S. Pat. No.
6,815,252, filed Mar. 9, 2001, which claims the benefit of U.S.
Provisional Application No. 60/188,570, filed Mar. 10, 2000, all of
which applications are incorporated herein by reference.
FIELD OF THE INVENTION
[0002] This invention relates to flip chip interconnection
structures and, more particularly, to an interconnect structure
formed by mechanical deformation and interlocking of asperities
between the surfaces to be joined.
BACKGROUND OF THE INVENTION
[0003] Flip chip interconnection between an integrated circuit (IC)
chip and a substrate is commonly performed in electronic package
assembly. In the most common form of such interconnection bumps on
the IC chip are metallurgically joined to pads formed on the
substrate, usually by melting of the bump material. While this
approach provides robust connections, it is difficult to reduce the
pitch of the interconnection due to the risk of bridging (i.e.,
shorting between adjacent connections) during the melting and
solidification processes. In an alternative approach the attachment
is made using a particulate film or paste, whereby conductive
particles in the paste or film together with the shrinkage force of
a resin effect an electrical connection. This approach lends itself
to reduction of interconnection pitch but suffers from limited long
term reliability owing to the susceptibility of the particulate
interconnection to degrade over time.
SUMMARY OF THE INVENTION
[0004] In one general aspect the invention features a method of
making a semiconductor device comprising the steps of providing a
semiconductor die, forming an interconnect structure over the
semiconductor die, providing a substrate including an interconnect
pad, and bonding the interconnect structure over the semiconductor
die and interconnect pad by deforming the interconnect structure
around the interconnect pad.
[0005] In another embodiment, the present invention is a method of
making a semiconductor device comprising the steps of providing a
semiconductor die, providing a substrate including an interconnect
pad, and forming an interconnect structure over the semiconductor
die and around the interconnect pad.
[0006] In another embodiment, the present invention is a
semiconductor device comprising a semiconductor die and an
interconnect structure formed over the semiconductor die. A
substrate includes an interconnect pad. The interconnect structure
is deformed onto the interconnect pad.
[0007] In another embodiment, the present invention is a
semiconductor device comprising a substrate and an interconnect pad
formed over the substrate. An interconnect structure is deformed
over the interconnect pad.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIGS. 1A, 1B are diagrammatic sketches in a sectional view
showing an illustrative embodiment according to the invention of
steps in the formation of an assembly having a chip interconnection
structure according to the invention;
[0009] FIGS. 2A, 2B are diagrammatic sketches in a sectional view
showing a second illustrative embodiment according to the invention
of steps in the formation of an assembly having a chip
interconnection structure according to the invention;
[0010] FIGS. 3A, 3B are diagrammatic sketches in a sectional view
showing a third illustrative embodiment according to the invention
of steps in the formation of an assembly having a chip
interconnection structure according to the invention;
[0011] FIGS. 4A, 4B are diagrammatic sketches in a sectional view
showing a fourth illustrative embodiment according to the invention
steps in the formation of an assembly having a chip interconnection
structure according to the invention;
[0012] FIG. 5 is a diagrammatic sketch in a sectional view showing
an alternative shape for an interconnection bump useful according
to the invention; and
[0013] FIG. 6 is a diagrammatic sketch in a sectional view showing
another alternative shape for an interconnection bump useful
according to the invention.
DETAILED DESCRIPTION OF THE DRAWINGS
[0014] With reference to FIGS. 1A, 1B a flip chip interconnection
structure generally designated 10 is shown schematically including
a first member 12 and a second member 14. The first member 12 is
preferably a bump formed on the IC chip and the second member 14 is
preferably a lead or pad formed on the substrate. The first member
12 further preferably comprises a soft, deformable material with a
low yield strength and high elongation to failure. The second
member 14 further preferably includes a substrate pad with a
conventional plated surface finish, and is characterized by having
asperities 16, which are shown exaggerated in the Figs. for
purposes of illustration. The scale of the asperities is generally
in the order about 1 .mu.m-25 .mu.m. The bump is a generally
compliant material, that is to say, a material that, in the
particular bump as shaped, undergoes a plastic deformation greater
than about 25 .mu.m under a force equivalent to a vertical load of
about 250 grams. Gold can be a particularly useful material for the
bumps according to the invention.
[0015] The interconnection is accomplished by compressing the first
member 12 and the second member 14 against one another to cause
plastic flow of first member 12 into asperities 16. The height and
soft nature of first member 12 allows considerable deformation to
occur even after the connection is effected thus allowing for other
bump/pad pairs with poor planarity to be joined with equal success.
The force and temperature requirements necessary to effect the
interconnection are significantly lower than needed for
conventional thermo-compression bonds that require metallurgical
diffusion of the mating materials. These reduced requirements
greatly reduce damage that might otherwise occur on the chip,
particularly when the number of connections to be effected
simultaneously is large.
[0016] A second embodiment is schematically shown in FIGS. 2A, 2B.
A macroscopic interlocking configuration generally designated 20 is
formed by plastic flow of the material of first member 22 around a
side wall 24 and edge 26 of a second member or trace 28. Preferably
the flow of the material of first member 22 is around the side wall
24 and does not cause material flow into a region between adjacent
traces but rather in the normal direction within the same plane.
The interlocking configuration 20 provides for an increased area of
interlocked surfaces without significantly increasing the bonding
force, thereby providing a more robust connection. Further the
additional displacement perpendicular to the chip surface provides
greater tolerance to poor co-planarity of multiple mating surface.
Finally, the interlocking along a plane perpendicular to the chip
surface in addition to the usual interlocking parallel to the chip
surface provides for protection against relative movement between
the die and the substrate in a perpendicular direction.
[0017] A third embodiment is shown in FIGS. 3A, 3B and includes an
interconnection generally designated 30. The interconnection 30 is
formed by plastic flow of the material of a first member 32 around
a second member 34. The second member 34 includes a smaller width
than that of the first member 32 which allows for plastic flow of
the material of first member 32 around both sides 36 and 38 of the
second member 34.
[0018] A fourth embodiment is shown in FIGS. 4A, 4B and includes an
interconnection generally designated 40. The lead geometry of a
second element 42 is shown to be wedge shaped to take advantage of
what represents the most typical "undercut" lead shape in actual
substrates that are fabricated by the subtractive etching method.
The interconnection 40 is formed by plastic flow of the material of
a first element 44 around the second element 42. The shown geometry
removes the restriction of minimum trace width and more
specifically the minimum width of a plateau 46 necessary for
conventional wire bonding applications. It is contemplated that the
interconnection 40 could alternatively be formed by bonding
directly on a via pad or through a via hole down to the next lower
layer on the substrate.
[0019] In embodiments as described above with reference to FIGS.
2A, 2B, 3A, 3B, 4A, 4B, the macroscopic interlocking configuration
allows for formation of the interconnect using a lower force, for
example lower by a factor of 2, as compared with embodiments as
described above with reference to FIGS. 1A, 1B. Use of lower force
of compression can result in less damage to chips during
processing.
[0020] In preferred embodiments, an adhesive resin is preferably
applied in a space between the chip and the substrate such that the
compressive force supplied by the cured resin further improves the
long-term retention of the electrical connection. The adhesive
resin is preferably applied before the mating surfaces are bonded,
and is cured concomitantly with the formation of the
interconnection. The applied interconnection force helps displace
the resin material away from the mating surfaces to allow the
formation of the desired mechanically interlocked connection.
Alternatively, the resin can be applied after the interconnection
using an underfill process.
[0021] In the disclosed preferred embodiments, the material of the
first members 12, 22, 32 and 44 is preferably Cu, electroless NiAu
or Au. The substrate material is preferably single-sided FR5
laminate or 2-sided BT-resin laminate.
[0022] The bumps may have various configurations other than one
shown in the Figs. above having a generally rectangular section
before compression and deformation; two particularly useful ones
are shown diagrammatically in FIGS. 5 and 6. FIG. 5 shows a
"stepped" shape, in which the portion of the bump adjacent the chip
(the "base") is wider than the portion (the "tip") that will be
compressed against the pad on the substrate. FIG. 6 shows a "stud
bump" configuration, in which the base has a peripherally rounded
profile that is wider than the tip. Either of these constructs can
provide improved compliance of the bump with the asperities on the
substrate, owing to the thinner tip dimension, and also provide
good structural stability owing to the wider profile of the
base.
[0023] The second member may be a lead or a pad, as described
above, and a bump may be interconnected to a conventional solder
pad that is electrically connect to a via hole; but in some
embodiments the second member itself includes a via hole. According
to this embodiment of the invention an interconnection structure
can be formed directly between the bump and the via hole, by
compressing the bump directly against conductive material in and at
the margin of the via hole, rather than compressing the bump onto a
pad, such as a solder pad, formed at some distance away from the
via hole and connected to it. This results in a more efficient use
of the area on the chip. Where the opening in the via hole is
generally smaller than the tip of the bump, then the bump can be
pressed directly onto the via hole, and becomes deformed into the
via hole to form the interconnection; in effect, the via hole works
as the asperity in this construct where the bump is smaller than
the via hole, then the bump can be offset, so that the bond is
formed at a portion of the rim of the via opening.
* * * * *