U.S. patent application number 14/054839 was filed with the patent office on 2014-02-06 for method for fabricating an aperture.
This patent application is currently assigned to UNITED MICROELECTRONICS CORP.. The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Feng-Yi Chang, Chih-Wen Feng, Ching-Pin Hsu, Jiunn-Hsiung Liao, Yi-Po Lin, Shui-Yen Lu, Shang-Yuan Tsai.
Application Number | 20140038399 14/054839 |
Document ID | / |
Family ID | 47293541 |
Filed Date | 2014-02-06 |
United States Patent
Application |
20140038399 |
Kind Code |
A1 |
Chang; Feng-Yi ; et
al. |
February 6, 2014 |
METHOD FOR FABRICATING AN APERTURE
Abstract
A method for fabricating an aperture is disclosed. The method
includes the steps of: forming a hard mask containing carbon on a
surface of a semiconductor substrate; and using a non-oxygen
element containing gas to perform a first etching process for
forming a first aperture in the hard mask. Before forming the hard
mask, a gate which includes a contact etch stop layer and a
dielectric layer is formed on the semiconductor substrate.
Inventors: |
Chang; Feng-Yi; (Tainan
City, TW) ; Lin; Yi-Po; (Tainan City, TW) ;
Liao; Jiunn-Hsiung; (Tainan City, TW) ; Tsai;
Shang-Yuan; (Kaohsiung City, TW) ; Feng;
Chih-Wen; (Tainan City, TW) ; Lu; Shui-Yen;
(Hsinchu County, TW) ; Hsu; Ching-Pin; (Tainan
City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsin-Chu City |
|
TW |
|
|
Assignee: |
UNITED MICROELECTRONICS
CORP.
Hsin-Chu City
TW
|
Family ID: |
47293541 |
Appl. No.: |
14/054839 |
Filed: |
October 16, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13156319 |
Jun 8, 2011 |
8592321 |
|
|
14054839 |
|
|
|
|
Current U.S.
Class: |
438/585 |
Current CPC
Class: |
H01L 21/76816 20130101;
H01L 21/308 20130101; H01L 21/31144 20130101; H01L 21/31122
20130101; H01L 21/76802 20130101 |
Class at
Publication: |
438/585 |
International
Class: |
H01L 21/308 20060101
H01L021/308 |
Claims
1. A method for fabricating an aperture, comprising: forming a hard
mask containing amorphous carbon on a surface of a semiconductor
substrate; and using a non-oxygen element containing gas to perform
a first etching process for forming a first aperture in the hard
mask, wherein the non-oxygen element containing gas consists of
H.sub.2 and N.sub.2.
2. The method of claim 1, wherein after forming the hard mask
comprises: forming a dielectric anti-reflective coating, a bottom
anti-reflective coating, and a patterned resist on the hard mask;
using the patterned resist to perform a second etching process for
forming a second aperture in the bottom anti-reflective coating and
the dielectric anti-reflective coating; and using the patterned
resist to perform the first etching process for forming the first
aperture in the hard mask.
3. The method of claim 1, further comprising forming agate
structure on the semiconductor substrate before forming the hard
mask, wherein the gate structure comprises a contact etch stop
layer and a dielectric layer thereon.
4. The method of claim 3, wherein the gate structure comprises a
polysilicon gate or a metal gate.
5. The method of claim 3, further comprising using the first
aperture to define a rectangular slot opening along the horizontal
axis of the gate structure.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a Continuation Application of
U.S. patent application Ser. No. 13/156,319, which was filed on
Jun. 8, 2011, the entire contents of which are incorporated herein
by this reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention relates to a method for fabricating an
aperture, and more particularly, to a method for fabricating an
aperture in a hard mask while preventing the occurrence of a bowing
profile on a sidewall of the hard mask.
[0004] 2. Description of the Prior Art
[0005] The trend towards micro-miniaturization, or the ability to
fabricate semiconductor devices with features smaller than 0.1
micrometers, has presented difficulties when attempting to form
narrow diameter, deep (high aspect ratio) contact holes in a
dielectric layer, to expose underlying conductive regions.
[0006] The conventional approach of fabricating contact holes
typically involves providing a semiconductor substrate with a
plurality of semiconductor devices thereon, in which the
semiconductor devices includes MOS transistors or resistors. At
least a dielectric layer and a hard mask are then formed on the
semiconductor substrate to cover the semiconductor devices, and a
patterned resist is used to perform a series of pattern transfer
processes to form a contact hole in the hard mask and the
dielectric layer.
[0007] The conventional method typically uses an oxygen containing
gas for performing the aforementioned pattern transfer process,
which causes severe indentation with respect to the central region
of the sidewall and ultimately produces a bowing profile.
Unfortunately, metal deposited in the contact hole thereafter is
likely to seal the entrance of the hole before filling the
expanding bowing portion of the contact hole. As a result, a seam
is formed relative to the central region of the deposited metal,
which degrades the electrical connection of the device and affects
the overall performance.
SUMMARY OF THE INVENTION
[0008] It is an objective of the present invention to provide a
method for resolving the issue of bowing profile in the contact
hole fabricated by conventional technique.
[0009] According to a preferred embodiment of the present
invention, a method for fabricating an aperture is disclosed. The
method includes the steps of: forming a hard mask containing carbon
on a surface of a semiconductor substrate; and using a non-oxygen
element containing gas to perform a first etching process for
forming a first aperture in the hard mask.
[0010] Another aspect of the present invention provides a method
for fabricating an aperture. The method includes the steps of:
forming a hard mask and a dielectric anti-reflective coating (DARC)
on a semiconductor substrate; forming a first bottom
anti-reflective coating (BARC) on the DARC; forming a first
aperture in the first BARC and portion of the DARC; forming a
second BARC on the DARC and filling the first aperture; forming a
second aperture in the second BARC and portion of the DARC; and
using a non-oxygen element containing gas to perform an etching
process to transfer the first aperture and the second aperture to
the hard mask for forming a plurality of third apertures.
[0011] Another aspect of the present invention provides a method
for fabricating an aperture, which includes the steps of: forming a
hard mask and a dielectric anti-reflective coating (DARC) on a
semiconductor substrate; forming a first bottom anti-reflective
coating (BARC) on the DARC; etching the first BARC, the DARC, and
the hard mask for forming a first aperture in the hard mask;
forming a second BARC on the DARC to fill the first aperture; and
etching the second BARC, the DARC, and the hard mask to forma
second aperture in the hard mask, wherein the step of etching the
hard mask comprises using a non-oxygen element containing gas.
[0012] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIGS. 1-3 illustrate a method for fabricating an aperture
according to a preferred embodiment of the present invention.
[0014] FIGS. 4-5 illustrate a method for fabricating an aperture
according to another embodiment of the present invention.
[0015] FIGS. 6-11 illustrate a method for fabricating an aperture
according to another embodiment of the present invention.
DETAILED DESCRIPTION
[0016] Please refer to FIGS. 1-3, which illustrate a method for
fabricating an aperture according to a preferred embodiment of the
present invention. As shown in FIG. 2, a semiconductor substrate
60, such as a substrate composed of monocrystalline silicon,
gallium arsenide (GaAs) or other known semiconductor material is
provided. A standard metal-oxide semiconductor (MOS) transistor
fabrication is performed to form at least one MOS transistor (not
shown) or other semiconductor devices on the semiconductor
substrate 60. The MOS transistor could be a PMOS transistor, an
NMOS transistor, or a CMOS transistor, and the MOS transistor could
also include typical transistor structures including a gate
structure, a spacer, a lightly doped drain, a source/drain regions
and/or salicides. The gate structure could be a polysilicon gate or
a metal gate fabricated from a high-k first or high-k last
processes. As these processes are well known to those skilled in
the art, the details thereof are omitted for the sake of
brevity.
[0017] A contact etch stop layer (CESL) 34 composed of nitrides is
then deposited on the MOS transistors, in which the depth of the
contact etch stop layer 34 is about 850 Angstroms. The contact etch
stop layer 34 could be formed selectively, and the contact etch
stop layer 34 could be formed to provide stress to the device
underneath. For instance, the contact etch stop layer 34 could be a
SiC layer providing tensile stress for NMOS transistors, or a SiN
layer providing compressive stress for PMOS transistors. If a STI
or non-transistor device is disposed underneath, the contact etch
stop layer could be a composite contact etch stop layer consisting
of tensile CESL and compressive CESL, and a buffer layer is further
inserted between the tensile CESL and the compressive CESL.
[0018] An interlayer dielectric layer (ILD) 36 is formed on the
surface of the contact etch stop layer 34. In this embodiment, the
interlayer dielectric layer 36 is preferably composed of three
layers, including a dielectric layer deposited by sub-atmospheric
pressure chemical vapor deposition (SACVD), a phosphosilicate glass
(PSG) layer, and a tetraethylorthosilicate (TEOS) layer. The depth
of the entire interlayer dielectric layer 36 is a few thousand
Angstroms (preferably approximately 3150 Angstroms); the depth of
the dielectric layer is around several thousands of Angstroms
(preferably 250 Angstroms); the depth of the PSG layer is between
1000 Angstroms to 3000 Angstroms (preferably 1900 Angstroms); and
the depth of the TEOS layer is between 100 Angstroms to 2000
Angstroms (preferably 1000 Angstroms). In addition to being a
composite material layer, the interlayer dielectric layer 36 could
also be a single material layer, and in addition to the
aforementioned materials, the interlayer dielectric layer 36 could
also include undoped silicate glass (USG), borophosposilicate glass
(BPSG), low-k dielectric material such as porous dielectric
material, SiC, SiON, or any combination thereof.
[0019] A hard mask 44 is then formed on the surface of the
interlayer dielectric layer 36. According to a preferred embodiment
of the present invention, the hard mask 44 is composed of a carbon
containing material such as amorphous carbon, and is preferably
selected from an advanced pattern film (APF) fabricated by Applied
Materials Inc., in which the depth of the hard mask 44 is between
1000 Angstroms to 5000 Angstroms, and preferably 2000 Angstroms. A
dielectric anti-reflective coating (DARC) 46 and a bottom
anti-reflective coating (BARC) 48 are then deposited on the surface
of the hard mask 44. In this embodiment, the DARC 46 is preferably
composed of a silicon oxynitride (SiON) layer and an oxide layer,
in which the depth of the DARC 46 is approximately 250 Angstroms,
and the depth of the BARC 48 is approximately 1020 Angstroms. The
DARC 46 and the BARC 48 are formed selectively, and in addition to
inorganic materials, these two layers 46 and 48 could also be
composed of organic materials by a spin-coating process.
[0020] A plurality of pattern transfer processes is then performed
on the above stacked film to form an aperture penetrating the BARC
48, the DARC 46, the hard mask 44, the interlayer dielectric layer
36, and the contact etch stop layer 34 to expose the MOS transistor
underneath, such as the source/drain region of the MOS transistor.
For example, a patterned resist 54 adapted for a wavelength of
approximately 193 nm is formed on the aforementioned stacked film
to expose a portion of the upper surface of the BARC 48, in which
the depth of the patterned resist 54 is approximately 1800
Angstroms. A descum process is performed thereafter by using a gas
containing CO and O.sub.2 to remove excessive particles produced
from the exposure and development process.
[0021] Next, as shown in FIG. 2, the patterned resist 54 is used as
a mask to perform a pattern transfer process on the BARC 48.
Preferably, an etching gas containing CF.sub.4 and CH.sub.2F.sub.2
is utilized to remove a portion of the BARC 48 and the DARC 46 for
transferring the aperture pattern of the patterned resist 54 to the
BARC 48 and the DARC 46 and exposing the hard mask 44
underneath.
[0022] As shown in FIG. 3, another pattern transfer is performed by
using the patterned resist 54 as a mask and non-oxygen element
containing gas as an etching gas to partially remove the hard mask
44. This transfers the aperture in the BARC 48 and the DARC 46 to
the hard mask 44 for forming a patterned hard mask. In this
embodiment, the non-oxygen element containing etching gas utilized
is selected from a group consisting of H.sub.2, N.sub.2, He,
NH.sub.3, CH.sub.4, and C.sub.2H.sub.4. It should also be noted
that, as the non-oxygen element containing gas is used to pattern
the hard mask 44, the patterned resist 54 and the BARC 48 above the
hard mask 44 are also removed simultaneously to form an aperture 56
in the hard mask 44.
[0023] Next, the patterned hard mask 44 is used as a mask to
perform an etching process on the ILD 36 and the CESL 34, such as
using a gas containing C.sub.4F.sub.6, O, and Ar to partially
remove the ILD 36, thereby transferring the aperture 56 to the ILD
36 and the CESL 34. This completes the fabrication of an aperture
according to a preferred embodiment of the present invention.
[0024] As current fabrication processes typically cannot obtain a
desirable aperture pattern from one single pattern transfer process
due to smaller pitch, a two exposure and two development (2P2E)
approach is often employed to form desirable aperture patterns.
Please refer to FIGS. 4-5, which illustrate perspective views of
applying the aforementioned method for forming apertures to a
current 2P2E process according to another embodiment of the present
invention.
[0025] As shown in FIG. 4, after the aperture 56 is formed in the
hard mask 44 of FIG. 3, another BARC 62 and a patterned resist 64
may be formed on the DARC 46, in which the BARC 62 preferably fills
the aperture 56 entirely.
[0026] As shown in FIG. 5, an etching process is performed by first
using the patterned resist 64 as a mask to partially remove the
BARC 62 and the DARC 46 for exposing the hard mask 44 underneath.
Next, another etching process is carried out by using a non-oxygen
element containing gas to etch the hard mask 44. This transfers the
aperture of the BARC 62 and the DARC 46 to the hard mask 44 for
forming a patterned hard mask. After stripping the patterned resist
62, the BARC 62 and the DARC 46, an etching process is carried out
by using the patterned hard mask 44 directly as a mask to partially
remove the ILD 36 and the CESL 34.
[0027] Please refer to FIGS. 6-11, which illustrate perspective
views of applying the aforementioned method of forming apertures to
a 2P2E process according to another embodiment of the present
invention. As shown in FIG. 6, a semiconductor substrate 80 is
provided, in which at least one semiconductor device (not shown) is
formed on the semiconductor substrate 80. The semiconductor device
could be a MOS transistor, such as a PMOS transistor, an NMOS
transistor, or a CMOS transistor, or devices of other types.
[0028] A CESL 82, an ILD 84, a hard mask 86, a DARC 88, a first
BARC 90, and a patterned resist 92 are sequentially formed on the
semiconductor device. The materials of the CESL 82, the ILD 84, the
hard mask 86, the DARC 88, and the first BARC 90 could be analogous
to the ones disclosed in the aforementioned embodiments; the
details are therefore omitted for the sake of brevity.
[0029] Next, a pattern transfer process is performed by using the
patterned resist 92 as a mask and using an etching gas containing
CF.sub.4 and CH.sub.2F.sub.2 to partially remove the first BARC 90
and a portion of the DARC 88. In this embodiment, this etching
process preferably removes only half the thickness of the DARC 88
while not exposing any of the hard mask 86 underneath. After
stripping the patterned resist 92 and the remaining first BARC 90,
as shown in FIG. 7, a first aperture 94 is formed in the DARC
88.
[0030] As shown in FIG. 8, a second BARC 96 and a patterned resist
98 are sequentially formed on the DARC 88, in which the second BARC
96 preferably fills the first aperture 94 in the DARC 88. Next, as
shown in FIG. 9, another pattern transfer process is performed by
using the patterned resist 98 as a mask to partially remove the
second BARC 90 and half the thickness of the DARC 88 while not
exposing any of the hard mask 86 underneath. After stripping the
patterned resist 98 and the remaining second BARC 96, a second
aperture 100 is formed in the DARC 88.
[0031] As shown in FIG. 10, an etching process is first carried out
to remove the remaining DARC 88 under the first aperture 94 and the
second aperture 100 to expose the hard mask 86, and another etching
process is performed by using the remaining DARC 88 as a mask to
form a plurality of third apertures 102 in the hard mask 66.
Similar to the aforementioned embodiment for etching the hard mask
86, this embodiment also uses a non-oxygen element containing gas
to partially remove the hard mask 86 for forming the third
apertures 102, in which the non-oxygen element gas utilized is
selected from a group consisting of H.sub.2, N.sub.2, He, NH.sub.3,
CH.sub.4, and C.sub.2H.sub.4.
[0032] Next, as shown in FIG. 11, an etching process is conducted
by using the remaining DARC 88 as a mask, or first removing the
remaining DARC 88 and using the patterned hard mask 86 as a mask to
transfer the third apertures 102 in the hard mask 86 to the ILD 86
and the CESL 82. This completes the fabrication of apertures
according to the embodiment of the present invention. It should be
noted that the apertures formed through the aforementioned
embodiments are not limited to circular apertures, but could also
be formed along the horizontal axis of the gate to form rectangular
slot openings; and, after metals are filled into these rectangular
slot openings, rectangular contact plugs are formed.
[0033] Overall, the present invention uses a non-oxygen element
containing gas to etch a hard mask of a stacked film for forming
desirable aperture patterns. According to a preferred embodiment of
the present invention, the hard mask is preferably selected from an
advanced pattern film (APF) fabricated by Applied Materials Inc.,
and the non-oxygen element gas is selected from a group consisting
of H.sub.2, N.sub.2, He, NH.sub.3, CH.sub.4, and C.sub.2H.sub.4. As
conventional methods of using CO/O.sub.2/CO.sub.2 based etching gas
typically cause issues such as side etching in the hard mask and
aperture shrinkage, the present invention specifically uses a
non-oxygen element containing gas for conducting the etching
process to maintain an adequate hard mask profile and critical
dimension uniformity. Moreover, as critical dimensions decrease,
the approach of the present invention also maintains a consistent
vertical profile of the aperture and prevents problems such as hole
distortion.
[0034] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *