U.S. patent application number 13/969370 was filed with the patent office on 2013-12-19 for device with mos device including a secondary metal and pvd tool with target for making same.
This patent application is currently assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.. The applicant listed for this patent is TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.. Invention is credited to Shih-Chieh Chang, Kei-Wei Chen, Ying-Lang Wang.
Application Number | 20130334581 13/969370 |
Document ID | / |
Family ID | 47555191 |
Filed Date | 2013-12-19 |
United States Patent
Application |
20130334581 |
Kind Code |
A1 |
Chang; Shih-Chieh ; et
al. |
December 19, 2013 |
Device with MOS Device Including a Secondary Metal and PVD Tool
with Target for Making Same
Abstract
A device includes a substrate and a metal-oxide-semiconductor
(MOS) device. The MOS device includes a gate dielectric over the
substrate, a gate electrode over the gate dielectric, a
source/drain region adjacent the gate dielectric, and a
source/drain silicide over and contacting the source/drain region.
The source/drain silicide comprises silicon, nickel, and a
secondary metal. A ratio of a volume percentage of the secondary
metal to a volume percentage of the silicon in the source/drain
silicide is between about 0.005 and about 0.1. The secondary metal
has a density between about 5,000 kg/m.sup.3 and about 15,000
kg/m.sup.3.
Inventors: |
Chang; Shih-Chieh; (Taipei
City, TW) ; Wang; Ying-Lang; (Tai-Chung, TW) ;
Chen; Kei-Wei; (Tainan City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
Hsin-Chu |
|
TW |
|
|
Assignee: |
TAIWAN SEMICONDUCTOR MANUFACTURING
COMPANY, LTD.
Hsin-Chu
TW
|
Family ID: |
47555191 |
Appl. No.: |
13/969370 |
Filed: |
August 16, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13188182 |
Jul 21, 2011 |
8551193 |
|
|
13969370 |
|
|
|
|
Current U.S.
Class: |
257/288 ;
204/298.13 |
Current CPC
Class: |
H01L 21/823418 20130101;
C23C 14/3414 20130101; H01L 29/45 20130101; H01L 21/28518 20130101;
H01L 29/665 20130101; H01L 21/28052 20130101; H01L 29/456 20130101;
C23C 14/14 20130101; H01L 21/2855 20130101 |
Class at
Publication: |
257/288 ;
204/298.13 |
International
Class: |
H01L 29/45 20060101
H01L029/45; C23C 14/14 20060101 C23C014/14 |
Claims
1. A device comprising: a substrate; a metal-oxide-semiconductor
(MOS) device comprising: a gate dielectric over the substrate; a
gate electrode over the gate dielectric; a source/drain region
adjacent the gate dielectric; and a source/drain silicide over and
contacting the source/drain region, wherein the source/drain
silicide comprises silicon, nickel, and a secondary metal, and
wherein a ratio of a volume percentage of the secondary metal to a
volume percentage of the silicon in the source/drain silicide is
between about 0.005 and about 0.1, and wherein the secondary metal
has a density between about 5,000 kg/m.sup.3 and about 15,000
kg/m.sup.3.
2. The device of claim 1, wherein the secondary metal is selected
from the group consisting essentially of zinc, molybdenum,
ruthenium, and combinations thereof.
3. The device of claim 2, wherein the secondary metal comprises
zinc.
4. The device of claim 2, wherein the secondary metal comprises
molybdenum.
5. The device of claim 2, wherein the secondary metal comprises
ruthenium.
6. The device of claim 1, wherein the nickel has a volume
percentage greater than about 90 percent.
7. The device of claim 1, wherein the gate electrode comprises a
polysilicon gate and the substrate is a silicon-on-insulator
substrate.
8. A device comprising: a silicon-containing substrate; isolation
regions in the silicon-containing substrate; a
metal-oxide-semiconductor (MOS) device adjacent to the isolation
regions, the MOS device comprising: a gate dielectric over the
silicon-containing substrate; a gate electrode over the gate
dielectric; a source/drain region adjacent the gate dielectric; and
a source/drain silicide over and contacting the source/drain
region, wherein the source/drain silicide comprises silicon,
nickel, and a secondary metal, and wherein a ratio of a volume
percentage of the secondary metal to a volume percentage of the
silicon in the source/drain silicide is between about 0.005 and
about 0.1, and wherein the secondary metal has a density between
about 5,000 kg/m.sup.3 and about 15,000 kg/m.sup.3.
9. The device of claim 8, further comprising a gate silicide over
and contacting the gate electrode, wherein the gate silicide
comprises nickel and the secondary metal.
10. The device of claim 8, further comprising a gate silicide over
and contacting the gate electrode, wherein the gate silicide
comprises nickel and the secondary metal.
11. The device of claim 10, wherein the secondary metal is selected
from the group consisting essentially of zinc, molybdenum,
ruthenium, and combinations thereof.
12. The device of claim 10, wherein the secondary metal comprises
zinc, and wherein a total volume of zinc in the source/drain
silicide region is between about 1 percent and about 10 percent of
a total volume of nickel and zinc in the source/drain silicide
region.
13. The device of claim 10, wherein the secondary metal comprises
molybdenum, and wherein a total volume of molybdenum in the
source/drain silicide region is between about 1 percent and about
10 percent of a total volume of nickel and molybdenum in the
source/drain silicide region.
14. The device of claim 10, wherein the secondary metal comprises
ruthenium, and wherein a total volume of ruthenium in the
source/drain silicide region is between 1 percent and about 10
percent of a total volume of nickel and ruthenium in the
source/drain silicide region.
15. A physical vapor deposition (PVD) tool comprising: a chamber
capable of being vacuumed; a target installed in the chamber,
wherein the target comprises nickel and a secondary metal, and
wherein the secondary metal is selected from the group consisting
essentially of zinc, molybdenum, ruthenium, and combinations
thereof; and a pedestal configured to hold a semiconductor wafer
thereon.
16. The PVD tool of claim 15, where in the target, a volume
percentage of nickel is greater than about 90 percent, and wherein
a volume percentage of the secondary metal is between about 1
percent and about 10 percent.
17. The PVD tool of claim 15 being configured to sputter the nickel
and the secondary metal from the target, and allow elements
sputtered from the target to deposit on the wafer.
18. The PVD tool of claim 15, wherein the secondary metal comprises
zinc.
19. The PVD tool of claim 15, wherein the secondary metal comprises
molybdenum.
20. The PVD tool of claim 15, wherein the secondary metal comprises
ruthenium.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of co-pending U.S. patent
application Ser. No. 13/188,182, filed on Jul. 21, 2011, entitled
"Nickel Alloy Target Including a Secondary Metal," which
application is hereby incorporated herein by reference.
BACKGROUND
[0002] Complementary metal-oxide-semiconductor (CMOS) devices
comprise source regions, drain regions, and gate electrodes, which
are often formed of silicon-containing materials. To reduce the
contact resistance between the silicon-containing source/drain
regions and the silicon-containing gate electrodes, metal silicides
may be formed atop the source/drain regions and the gate electrodes
prior to the formation of various metal layers comprising
conductive interconnect lines and vias. The most commonly used
metal silicides are nickel silicide and cobalt silicide, typically
formed by a self-aligned silicide (salicide) process.
[0003] In a salicide process, a thin layer of metal is blanket
deposited by physical vapor deposition (PVD) over a semiconductor
wafer, specifically over exposed source/drain regions and gate
electrodes. The wafer is then subjected to one or more annealing
steps, for example, at a temperature of 250.degree. C. or higher.
The annealing process causes the metal to selectively react with
the exposed silicon of the source/drain regions and the gate
electrodes, thereby forming metal silicide regions. The process is
referred to as a self-aligned silicidation process because the
silicide layer is formed where the metal material directly contacts
the silicon source/drain regions and the gate electrode. Following
the formation of the silicide regions, the un-reacted metal is
removed. An interconnect process is then performed to provide
conductive paths, such as by forming via holes through a deposited
interlayer dielectric and filling the via holes with a conductive
material, e.g., tungsten or copper.
[0004] For sub-65 nm technologies, nickel is widely used to form
silicides. A problem of the nickel silicide is its poor thermal
stability, and the tendency of forming agglomeration. The
resistivity of the resulting silicide is increased as a result of
the agglomeration. To improve the thermal stability of nickel
silicides, platinum may be added to the nickel silicide. To add
platinum, the target that is used in the PVD is added with
platinum, which may have a percentage between about 5 percent and
about 10 percent. The improvement in the thermal stability of the
silicides as a result of adding platinum, however, is still not
satisfactory, and the thermal stability of the silicides needs to
be improved further.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] For a more complete understanding of the embodiments, and
the advantages thereof, reference is now made to the following
descriptions taken in conjunction with the accompanying drawings,
in which:
[0006] FIG. 1 illustrates a perspective view of a target in
accordance with an embodiment, which may be using in a physical
vapor deposition (PVD) tool;
[0007] FIG. 2 schematically illustrates the PVD tool and the target
installed therein;
[0008] FIGS. 3 an 4 are cross-sectional views of intermediate
stages in the manufacturing of silicide regions of a
metal-oxide-semiconductor (MOS) device in accordance with an
embodiment; and
[0009] FIG. 5 illustrates experiment results, wherein the sheet
resistances of different alloys are illustrated as a function of
annealing temperatures.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
[0010] The making and using of the embodiments of the disclosure
are discussed in detail below. It should be appreciated, however,
that the embodiments provide many applicable inventive concepts
that can be embodied in a wide variety of specific contexts. The
specific embodiments discussed are merely illustrative, and do not
limit the scope of the disclosure.
[0011] A target for a physical vapor deposition (PVD) process and
the silicides formed using the target are provided in accordance
with an embodiment. The variations of the embodiment are then
discussed. Throughout the various views and illustrative
embodiments, like reference numbers are used to designate like
elements.
[0012] FIG. 1 illustrates a schematic perspective view of target
20, which may be used for PVD processes. In an embodiment, target
20 has a circular top-view shape (or any other applicable shape
such as square and rectangle), and may have diameter D between
about 15 inches and about 20 inches. It is realized, however, that
the dimensions recited throughout the description are merely
examples, and may be changed.
[0013] Target 20 may include nickel, with the volume percentage of
nickel in target 20 being greater than about 90 percent. The volume
percentage of nickel may also be between about 90 percent and about
99 percent. In addition, target 20 includes an additional metal(s)
(referred to as a secondary metal hereinafter). The secondary metal
may have densities ranging from about 5,000 kg/m.sup.3 to 15,000
kg/m.sup.3. In addition, the secondary metal may have a diffusivity
that is higher than the diffusivity of nickel, wherein the
diffusivity is measured as the diffusivity of the secondary metal
in silicon. With a high diffusivity, and hence smaller chance to
form agglomeration, the secondary metal has good thermal stability
during silicide processes, in which the metal layers formed using
target 20 react with silicon to form silicide regions.
[0014] In some embodiments, the secondary metal includes a metal
selected from the group consisting essentially of zinc, molybdenum,
ruthenium, and combinations thereof. Target 20 may thus be an alloy
of nickel and one or more of zinc, molybdenum, and ruthenium. The
density of nickel is 8,800 kg/m.sup.3. The density of zinc is 7,135
kg/m.sup.3. The density of molybdenum is 10,188 kg/m.sup.3. The
density of ruthenium is 12,370 kg/m.sup.3. The secondary metal in
target 20 may have a volume percentage between about 1 percent and
about 10 percent. In the case a single one (but not all) of zinc,
molybdenum, and ruthenium is included in target 20, the single
secondary metal has a volume percentage between about 1 percent and
about 10 percent, or between about 4 percent and about 6 percent.
In the embodiments wherein more than one of zinc, molybdenum, and
ruthenium is used in target 20, the secondary metals have a total
volume percentage between about 1 percent and about 10 percent, or
between about 4 percent and about 6 percent.
[0015] FIG. 2 illustrates a schematic cross-sectional view of
production tool 30, which may be a PVD tool, although production
tool 30 may also be used for other deposition methods. Production
tool 30 includes chamber 32 that is capable of being vacuumed, so
that a vacuum environment is generated in chamber 32. Target 20 is
installed in chamber 32. Wafer 34 is placed on pedestal 36, which
may be an electrostatic chuck (E-Chuck) configured to hold wafer 34
in place. Wafer 34 may be a semiconductor wafer for forming
integrated circuits. In the PVD process, the metal atoms in target
20 may be sputtered off, and deposited on the surface of wafer 34.
The energy source for sputtering target 20 may be a DC voltage
source 35, although a radio frequency (RF) energy source may also
be used.
[0016] FIGS. 3 and 4 are cross-sectional views of intermediate
stages in a silicidation process performed on wafer 34 as shown in
FIG. 2. Referring to FIG. 3, wafer 34 comprises
metal-oxide-semiconductor (MOS) device 40, which may be formed on
silicon-containing substrate 42. Silicon-containing substrate 42
may be a bulk silicon substrate, or may have a silicon-on-insulator
structure. Source and drain regions 44 (referred to as source/drain
regions hereinafter) are formed, and may comprise silicon. Source
and drain regions 44 may, or may not, comprise nickel and/or the
secondary metal. MOS device 40 may be adjacent to isolation regions
46, which may be shallow trench isolation (STI) regions. A gate
stack comprising gate dielectric 48 and gate electrode 50 is formed
over substrate 42. Gate electrode 50 may be a metal gate or a
polysilicon gate.
[0017] Using production tool 30 as in FIG. 2, metal layer 52 (FIG.
3) may be deposited on MOS device 40, wherein metal layer 52 is in
contact with source and drain regions 44. The materials of metal
layer 52 are sputtered off from target 20 (FIG. 2), and hence metal
layer 52 includes nickel and the secondary metal. In addition,
metal layer 52 may have a composition (the percentages of nickel
and the secondary metal) close to the composition of target 20,
although the compositions of nickel and the secondary metal may be
slightly different from that of target 20.
[0018] Referring to FIG. 4, an annealing is performed, forming
source/drain silicide regions 54 over and contacting source/drain
regions 44. In the embodiments wherein gate electrode 50 is a
polysilicon gate, gate silicide 56 is also formed. The annealing
may be performed at a temperature over about 400.degree. C.,
although a lower temperature may be used, providing the quality of
the resulting silicide regions is not compromised. The annealing
process may be performed using thermal annealing, flash annealing,
laser annealing, and the like. In an exemplary embodiment, the
annealing process comprises two steps. The first step includes a
first annealing at a relatively low temperature. In the first step,
a portion of metal layer 52 (FIG. 3) reacts with silicon to form a
silicide. This silicide typically has a higher resistivity than in
the structure as shown in FIG. 4. Un-reacted metal layer 52 is then
removed. The second step includes a second annealing to convert the
high-resistive silicide to a low-resistive silicide. In an
exemplary embodiment, the first annealing is performed at about
300.degree. C. to about 400.degree. C., while the second annealing
is performed at about 700.degree. C.
[0019] It is observed that in the silicidation process, although
silicon is added into nickel and the secondary metal, the addition
of silicon does not affect the relative ratio of nickel to the
secondary metal. Alternatively stating, in silicide regions 54 and
56, the volume percentage of nickel among nickel and the secondary
metal remains the same as the volume percentage of nickel in metal
layer 52. The volume percentage of nickel among nickel and the
secondary metal may be expressed as:
PNi=(VNi/(VNi+VSM))*100% (Eq. 1)
Wherein PNi is the volume percentage of nickel among nickel and the
secondary metal, VNi is the total volume of nickel in the
respective silicide regions 54 and 56, and VSM is the total volume
of the secondary metal.
[0020] Similarly, in silicide regions 54 and 56, the volume
percentage of the secondary metal among nickel and the secondary
metal remains the same as the volume percentage of the secondary
metal in metal layer 52. The volume percentage of the secondary
metal among nickel and the secondary metal may be expressed as:
PSM=(VSM/(VNi+VSM))*100% (Eq. 1)
wherein PSM is the volume percentage of the secondary metal among
nickel and the secondary metal. Accordingly, in silicide regions 54
and 56, the volume percentage of nickel among nickel and the
secondary metal may be between about 90 percent and about 99
percent, while the volume percentage of the secondary metal among
nickel and the secondary metal may be between about 1 percent and
about 10 percent.
[0021] The composition of silicide regions 54 and 56 may also be
expressed as Si.sub.xNi.sub.yM.sub.z, wherein letter "M" represents
the secondary metal, and letters "x," "y," and "z" represent the
volume percentages of silicon, nickel, and the secondary metal,
respectively. In an embodiment, ratio z/x is between about 0.005
and about 0.1.
[0022] After the formation of silicide regions 54 and 56, the
remaining components of MOS device 40 are formed. The formation
process includes forming contact etch stop layer (CESL) 60 over
silicide regions 54 and 56, forming inter-layer dielectric (ILD) 62
over CESL 60, forming contact openings (occupied by contact plugs
64) in ILD 62 and CESL 60, and filling the contact openings with a
metallic material such as tungsten to form contact plugs 64.
[0023] In the embodiments, due to the addition of the secondary
metal, the resulting silicide regions 54 and 56 may have a
significantly improved thermal stability at temperatures higher
than about 600.degree. C. FIG. 5 illustrates experimental results,
wherein the sheet resistances of various sample silicide regions
are illustrated. The samples are formed on silicon wafers. The
experimental results indicate that when the annealing temperatures
are higher than 600.degree. C., the silicide regions formed using
nickel and the secondary metal (comprising zinc, molybdenum, or
ruthenium) have sheet resistances significantly lower than the
silicide region formed by adding other metals such as tantalum,
titanium. Especially, when zinc is added into nickel, the resulting
nickel-and-zinc-containing silicides, when annealed at 700.degree.
C., have a sheet resistance substantially equal to or smaller than
the sheet resistances of all other silicides that are formed under
different temperatures ranging from 50.degree. C. to 700.degree. C.
This indicates that at 700.degree. C., no agglomeration is formed
in the silicides comprising nickel and zinc. Furthermore, under
scanning electron microscope (SEM), the silicide regions formed
with zinc, molybdenum, or ruthenium added (to 5 percent) also show
that substantially no agglomeration is formed.
[0024] An embodiment device includes a substrate, a
metal-oxide-semiconductor (MOS) device comprises a gate dielectric
over the substrate, a gate electrode over the gate dielectric, a
source/drain region adjacent the gate dielectric, and a
source/drain silicide over and contacting the source/drain region,
wherein the source/drain silicide comprises silicon, nickel, and a
secondary metal, and wherein a ratio of a volume percentage of the
secondary metal to a volume percentage of the silicon in the
source/drain silicide is between about 0.005 and about 0.1, and
wherein the secondary metal has a density between about 5,000
kg/m.sup.3 and about 15,000 kg/m.sup.3.
[0025] An embodiment device includes a silicon-containing
substrate, isolation regions in the silicon-containing substrate, a
metal-oxide-semiconductor (MOS) device adjacent to the isolation
regions. The MOS device comprises a gate dielectric over the
silicon-containing substrate, a gate electrode over the gate
dielectric, a source/drain region adjacent the gate dielectric, and
a source/drain silicide over and contacting the source/drain
region, wherein the source/drain silicide comprises silicon,
nickel, and a secondary metal, and wherein a ratio of a volume
percentage of the secondary metal to a volume percentage of the
silicon in the source/drain silicide is between about 0.005 and
about 0.1, and wherein the secondary metal has a density between
about 5,000 kg/m.sup.3 and about 15,000 kg/m.sup.3.
[0026] An embodiment physical vapor deposition (PVD) tool includes
a chamber capable of being vacuumed, a target installed in the
chamber, wherein the target comprises nickel and a secondary metal,
and wherein the secondary metal is selected from the group
consisting essentially of zinc, molybdenum, ruthenium, and
combinations thereof, and a pedestal configured to hold a
semiconductor wafer thereon.
[0027] Although the embodiments and their advantages have been
described in detail, it should be understood that various changes,
substitutions and alterations can be made herein without departing
from the spirit and scope of the embodiments as defined by the
appended claims. Moreover, the scope of the present application is
not intended to be limited to the particular embodiments of the
process, machine, manufacture, and composition of matter, means,
methods and steps described in the specification. As one of
ordinary skill in the art will readily appreciate from the
disclosure, processes, machines, manufacture, compositions of
matter, means, methods, or steps, presently existing or later to be
developed, that perform substantially the same function or achieve
substantially the same result as the corresponding embodiments
described herein may be utilized according to the disclosure.
Accordingly, the appended claims are intended to include within
their scope such processes, machines, manufacture, compositions of
matter, means, methods, or steps. In addition, each claim
constitutes a separate embodiment, and the combination of various
claims and embodiments are within the scope of the disclosure.
* * * * *