U.S. patent application number 13/367989 was filed with the patent office on 2013-08-08 for salicide formation using a cap layer.
This patent application is currently assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.. The applicant listed for this patent is Ching-Hua CHU, Chih-Hsun LIN, Mei-Hsuan LIN, Ling-Sung WANG. Invention is credited to Ching-Hua CHU, Chih-Hsun LIN, Mei-Hsuan LIN, Ling-Sung WANG.
Application Number | 20130200442 13/367989 |
Document ID | / |
Family ID | 48902166 |
Filed Date | 2013-08-08 |
United States Patent
Application |
20130200442 |
Kind Code |
A1 |
LIN; Mei-Hsuan ; et
al. |
August 8, 2013 |
SALICIDE FORMATION USING A CAP LAYER
Abstract
A semiconductor device having a source feature and a drain
feature formed in a substrate. The semiconductor device having a
gate stack over a portion of the source feature and over a portion
of the drain feature. The semiconductor device further having a
first cap layer formed over substantially the entire source feature
not covered by the gate stack, and a second cap layer formed over
substantially the entire drain feature not covered by the gate
stack. A method of forming a semiconductor device including forming
a source feature and drain feature in a substrate. The method
further includes forming a gate stack over a portion of the source
feature and over a portion of the drain feature. The method further
includes depositing a first cap layer over substantially the entire
source feature not covered by the gate stack and a second cap layer
over substantially the entire drain feature not covered by the gate
stack.
Inventors: |
LIN; Mei-Hsuan; (Tainan
City, TW) ; LIN; Chih-Hsun; (Tainan City, TW)
; CHU; Ching-Hua; (Kaohsiung City, TW) ; WANG;
Ling-Sung; (Tainan City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
LIN; Mei-Hsuan
LIN; Chih-Hsun
CHU; Ching-Hua
WANG; Ling-Sung |
Tainan City
Tainan City
Kaohsiung City
Tainan City |
|
TW
TW
TW
TW |
|
|
Assignee: |
TAIWAN SEMICONDUCTOR MANUFACTURING
COMPANY, LTD.
Hsinchu
TW
|
Family ID: |
48902166 |
Appl. No.: |
13/367989 |
Filed: |
February 7, 2012 |
Current U.S.
Class: |
257/288 ;
257/E21.438; 257/E29.255; 438/300 |
Current CPC
Class: |
H01L 21/0262 20130101;
H01L 29/41783 20130101; H01L 29/4975 20130101; H01L 21/28052
20130101; H01L 21/28568 20130101; H01L 21/02631 20130101; H01L
21/2855 20130101; H01L 21/28518 20130101; H01L 29/4933 20130101;
H01L 29/7848 20130101; H01L 29/66507 20130101; H01L 21/02425
20130101; H01L 29/665 20130101; H01L 21/28556 20130101; H01L
21/02617 20130101; H01L 21/02381 20130101; H01L 21/02532 20130101;
H01L 21/28097 20130101; H01L 29/7845 20130101 |
Class at
Publication: |
257/288 ;
438/300; 257/E29.255; 257/E21.438 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 21/336 20060101 H01L021/336 |
Claims
1. A semiconductor device comprising: a substrate having a source
feature and a drain feature therein configured to enhance charge
mobility; a gate stack over a portion of the source feature and a
portion of the drain feature; a first salicide layer over
substantially the entire source feature not covered by the gate
stack, wherein the first salicide layer has a germanium
concentration less than about 3% by weight; and a second salicide
layer over substantially the entire drain feature not covered by
the gate stack, wherein the second salicide layer has a germanium
concentration less than about 3% by weight.
2. The semiconductor device of claim 1, wherein the first salicide
layer and the second salicide layer comprise at least one of
nickel, cobalt, titanium or platinum.
3. The semiconductor device of claim 1, wherein the first salicide
layer and the second salicide layer have a thickness ranging from
about 120 Angstroms to about 300 Angstroms.
4. The semiconductor device of claim 1, further comprising
electrical contacts connected to the first salicide layer and the
second salicide layer.
5. The semiconductor device of claim 1, further comprising a gate
salicide layer over a top surface of the gate stack.
6. The semiconductor device of claim 1, wherein the source feature
and the drain feature comprise silicon germanium.
7. The semiconductor device of claim 1, wherein the source feature
and the drain feature are substantially free of silicon.
8. The semiconductor device of claim 1, wherein the source feature
and the drain feature are configured to increase hole mobility.
9. A method of forming a semiconductor device comprising: forming a
source feature and a drain feature in a substrate; forming a gate
stack over a portion of the source feature and a portion of the
drain feature; depositing a first cap layer comprising silicon over
substantially the entire source feature not covered by the gate
stack; and depositing a second cap layer comprising silicon over
substantially the entire drain feature not covered by the gate
stack.
10. The method of claim 9, wherein the depositing the first cap
layer and the depositing the second cap layer comprise epitaxially
growing a silicon layer.
11. The method of claim 9, wherein the depositing the first cap
layer and the depositing the second cap layer comprises continuing
deposition until the first cap layer and the second cap layer each
have a thickness ranging from about 5 Angstroms to about 10
Angstroms.
12. The method of claim 9, further comprising depositing a metal
layer over the gate stack, the first cap layer and the second cap
layer.
13. The method of claim 12, wherein the depositing the metal layer
comprises depositing a layer comprising at least one of nickel,
cobalt, titanium, or platinum.
14. The method of claim 12, wherein the depositing the metal layer
comprises continuing deposition until the metal layer has a
thickness ranging from about 200 Angstroms to about 400
Angstroms.
15. The method of claim 12, further comprising after depositing the
metal layer, annealing the semiconductor device at a temperature
ranging from about 450 C to about 800 C to form a salicide
layer.
16. The method of claim 15, wherein the annealing the semiconductor
device continues for a duration of about 1 minute to about 10
minutes.
17. The method of claim 15, wherein the annealing the semiconductor
device continues until the salicide layer has a thickness ranging
from about 250 Angstroms to about 300 Angstroms.
18. The method of claim 15, further comprising after the annealing
the semiconductor device, removing an unreacted portion of the
metal layer.
19. The method of claim 18, wherein the removing the unreacted
portion of the metal layer comprises etching.
20. A semiconductor device comprising: a substrate having a source
feature and a drain feature therein; a gate stack over a portion of
the source feature and over a portion of the drain feature, wherein
the gate stack comprises: a first cap layer over substantially the
entire source feature not covered by the gate stack, wherein the
first cap layer has a thickness ranging from about 5 Angstroms to
about 10 Angstroms; a second cap layer over substantially the
entire drain feature not covered by the gate stack, wherein the
second cap layer has a thickness ranging from about 5 Angstroms to
about 10 Angstroms; and a metal layer over the gate stack, the
first cap layer and the second cap layer, wherein the metal layer
comprises nickel and has a thickness ranging from about 200
Angstroms to about 400 Angstroms.
Description
BACKGROUND
[0001] Many semiconductor devices use metal-silicon compounds
called silicdes to enhance conductivity between source and drain
features and conductive lines. Salicides are self-aligned
silicides. Self-aligned refers to a manufacturing technique where a
gate electrode region of a transistor is used as a mask for doping
the source and drain. Some techniques for forming salicides over
source and drain features include depositing a metal layer over a
surface of a semiconductor assembly including the source and drain
features. The assembly is then annealed to form a salicide in a
reaction between silicon atoms in the source and drain features and
metal atoms in the metal layer. The unreacted metal is then removed
using an etching process.
[0002] The reaction to form salicide consumes silicon atoms in the
source and drain features. If the source and drain features have an
insufficient amount of silicon at a surface interface with the
metal layer, in some instances, the salicide is also etched through
during the etching process to remove unreacted metal. Etching
through the salicide creates openings that can form short circuits
when metal contacts are deposited on the source and drain features.
Additionally, in situations where silicon atoms are unevenly
concentrated in the source and drain features, voids can form in
the salicide and cause the semiconductor device to malfunction.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] One or more embodiments are illustrated by way of example,
and not by limitation, in the figures of the accompanying drawings,
wherein elements having the same reference numeral designations
represent like elements throughout. It is emphasized that, in
accordance with standard practice in the industry various features
may not be drawn to scale and are used for illustration purposes
only. In fact, the dimensions of the various features in the
drawings may be arbitrarily increased or reduced for clarity of
discussion.
[0004] FIG. 1 is a side view diagram of a semiconductor device
including cap layers, according to one ore more embodiments.
[0005] FIG. 2 is a flowchart of a method of forming a salicide
layer in a semiconductor device including cap layers, according to
one or more embodiment.
[0006] FIGS. 3A-3G are side view diagrams of a semiconductor device
during various stages of the method of FIG. 2.
DETAILED DESCRIPTION
[0007] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the invention. Specific examples of components and arrangements are
described below to simplify the present disclosure. These are of
course, merely examples and are not intended to be limiting.
[0008] FIG. 1 is a side view diagram of a semiconductor device 100
according to an embodiment. Semiconductor device 100 includes a
substrate 102 having source and drain features 104 in substrate
102. Semiconductor device 100 includes a gate stack 106 and
optional spacers 108 over substrate 102. Semiconductor device 100
further includes cap layers 110 over at least a portion of source
and drain features 104.
[0009] In some embodiments, substrate 102 is silicon. In some
embodiments, substrate 102 is silicon germanium, gallium arsenide,
germanium or other suitable semiconductor material. In some
embodiments, substrate 102 is a semiconductor on insulator such as
silicon on insulator
[0010] Source and drain features 104 are areas of higher charge
mobility within substrate 102. In some embodiments, source and
drain features 104 have higher hole mobility than substrate 102. In
some embodiments, source and drain features 104 have higher
electron mobility than substrate 102. In some embodiments, source
and drain features 104 are doped with p-type dopants, such as boron
or BF.sub.2; or n-type dopants, such as phosphorous or arsenic. In
some embodiments, source and drain features 104 comprise silicon
germanium. In some embodiments, source and drain features 104 are
substantially silicon free.
[0011] Gate stack 106 includes a gate electrode 106a over an
optional a gate dielectric 106b. In some embodiments, gate
electrode 106a comprises polysilicon. In some embodiments, gate
electrode 106a comprises molybdenum, aluminum, copper or other
suitable conductive material. In some embodiments, optional gate
dielectric 106b comprises silicon dioxide. In some embodiments,
optional gate dielectric 106b comprises a high k dielectric, such
as hafnium silicate, zirconium silicate, hafnium dioxide, zirconium
dioxide, or other suitable dielectric material.
[0012] In some embodiments, source and drain features 104 and gate
stack 106 collectively form a transistor. In some embodiments,
where source and drain features 104 are selected to enhance hole
mobility, source and drain features 104 and gate stack 106
collectively form a p-type metal oxide semiconductor (PMOS)
transistor. In some embodiments, where source and drain features
104 are selected to enhance electron mobility, source and drain
features 104 and gate stack 106 collectively form an n-type metal
oxide semiconductor (NMOS) transistor.
[0013] In some embodiments, semiconductor device 100 optionally
includes spacers 108 along sidewalls of gate stack 106. In some
embodiments, spacers 108 comprise silicon dioxide, silicon nitride,
silicon oxynitride or other suitable material. In some embodiments,
spacers 108 comprise non-conductive material.
[0014] Cap layers 110 are over source and drain features 104
extending beyond gate stack 106 and optional spacers 108. In at
least some embodiments, cap layers 110 extend over substantially
all of source and drain features 104 extending beyond gate stack
106 and optional spacers 108. Cap layers 110 comprise silicon. In
some embodiments, cap layers 110 have a thickness ranging from
about 5 Angstroms to about 10 Angstroms. This range, in some
embodiments, is narrower, e.g., from 5 Angstroms to 10
Angstroms.
[0015] In the reaction to form a salicide layer (FIG. 3G) over
source and drain features 104, silicon is consumed. In some
embodiments, where source and drain features 104 do not comprise
sufficient silicon concentrations, the salicide layer formed over
source and drain features 104 is insufficiently thick to prevent
etching through the salicide layer and prevent exposing source and
drain features 104 during removal of unreacted metal. Exposing
source and drain features 104 creates short circuits when
metallized features, e.g., vias, are formed in contact with source
and drain features 104. Cap layers 110 provide sufficient silicon
atoms to form the salicide layer over source and drain features 104
to a thickness sufficient to avoid etching through the salicide
layer. The inclusion of cap layers 110 in semiconductor device 100,
thus acts to increase the yield of a production process by reducing
the number of semiconductor devices that are defective due to short
circuits.
[0016] Cap layers 110 also provide substantially uniform silicon
concentration over source and drain features 104. In some instances
where the salicide layer is formed with variations in silicon
concentration, voids form in the salicide layer thereby increasing
resistance to current flow. Increased resistance causes
semiconductor device 100 to perform below acceptable standards. Cap
layers 110 avoid the formation of voids in the salicide through the
substantially uniform distribution of silicon, thereby increasing
production yield.
[0017] FIG. 2 is a process flow diagram of a method 200 of forming
a semiconductor device 300, according to one or more embodiments.
Method 200 begins with forming source and drain features 104 in
substrate 102, gate stack 106 and optionally spacers 108 over
substrate 102 in operation 202. In some embodiments, source and
drain features 104 are formed by ion implantation, including tilted
ion implantation. In some embodiments, source and drain features
104 are formed by doping, annealing or other suitable processes.
Gate stack 106 and optional spacers 108 are formed using methods
known in the art including gate last processes. FIG. 3A is a side
view diagram of semiconductor device 300 following formation of
source and drain features 104, gate stack 106 and optionally
spacers 108.
[0018] Method 200 continues with optional operation 204, in which a
photoresist layer 112 (FIG. 3B) is deposited over substrate 102. In
some embodiments, outer boundaries of source and drain features 104
are defined by isolation features, another gate stack, or other
features over substrate 102 of semiconductor device 300. If the
outer boundaries of source and drain features 104 are defined by
another feature, photoresist layer 112 is eliminated, according to
some embodiments. In some embodiments, spin-on deposition, physical
vapor deposition, or other suitable deposition process deposits
photoresist layer 112 over substrate 102.
[0019] Method 200 continues with optional operation 206, in which
photoresist layer 112 is patterned and etched. In some embodiments,
if the outer boundaries of source and drain features 104 are
defined by other features photoresist layer 112 is eliminated. If
operation 204 is not used, operation 206 is likewise omitted. In
some embodiments, ultraviolet light passing through a mask patterns
photoresist layer 112. In some embodiments, thermal energy or other
suitable patterning processes are used to pattern photoresist layer
112. In some embodiments, patterned photoresist layer 112 is etched
using a wet etching process. In other embodiments, the etching
process is a dry etching process, a plasma etching process, a
reactive ion etching process, or other suitable etching process.
FIG. 3C is a side view diagram of semiconductor device 300
following patterning and etching of photoresist layer 112.
[0020] In operation 208 of method 200, cap layers 110 are deposited
over source and drain features 104. In some embodiments, cap layers
110 are deposited using an epitaxial growth process. In some
embodiments, cap layers 110 are deposited by sputtering, atomic
layer deposition, or other suitable deposition processes. In some
embodiments, deposition continues until cap layers 110 have a
thickness ranging from about 5 Angstroms to about 10 Angstroms.
FIG. 3D is a side view diagram of semiconductor device 300
following deposition of cap layers 110.
[0021] Following deposition of cap layers 110, optional photoresist
layer 112 is removed. In some embodiments, photoresist layer 112 is
removed using plasma ashing. In some embodiments, photoresist layer
112 is removed using etching or other suitable removal
processes.
[0022] In operation 210, a metal layer 114 (FIG. 3E) is deposited
over substrate 102. In some embodiments, metal layer 114 is
deposited using physical vapor deposition. In some embodiments,
metal layer 114 is deposited using chemical vapor deposition,
atomic layer deposition, electron beam evaporation, sputtering, or
other suitable deposition process. In some embodiments, metal layer
114 comprises nickel, cobalt, titanium, platinum, or other suitable
metal material. In some embodiments, the deposition process
continues until metal layer 114 has a thickness ranging from about
200 Angstroms to about 400 Angstroms. This range, in some
embodiments, is narrower, e.g., from 200 Angstroms to 400
Angstroms. FIG. 3E is a side view diagram of semiconductor device
300 following deposition of metal layer 114.
[0023] Method 200 continues with operation 212, in which
semiconductor device 300 is heated during an annealing process. The
annealing process causes metal atoms in metal layer 114 to react
with silicon atoms in cap layers 110 and in source and drain
features 104 to create the salicide layer. In some embodiments,
during the annealing process semiconductor device 300 is heated to
a temperature ranging from about 200 C to about 800 C. This range,
in some embodiments, is narrower, e.g., from 200 C to 800 C. In
some embodiments, the annealing process continues for a duration
ranging from about 1 minute to about 10 minutes.
[0024] In some embodiments, the annealing process tunes the
resistivity of the salicide layer. Generally, the higher the
annealing temperature and the longer the annealing duration, the
lower the resistivity of the resulting salicide layer because of
the formation of larger grains in the salicide layer. If the metal
of metal layer 114 and the silicon of cap layers 110 react to form
different compounds, tailoring the annealing process allows
selective formation of a desired salicide compound. For example,
when the metal of metal layer 114 is nickel, the desired salicide
compound is NiSi, instead of materials with a higher resistivity
such as Ni.sub.2Si or NiSi.sub.2. In order to obtain the highest
concentration of NiSi in the salicide layer, the annealing process
takes place at a temperature of about 200 C to about 500 C for a
duration of about one minute.
[0025] FIG. 3F is a side view diagram of semiconductor device 300
following the annealing process. The annealing process causes metal
layer 114 to react with silicon to form salicide layer 116. In some
embodiments, salicide layer 116 has a thickness ranging from about
120 Angstroms to about 300 Angstroms. This range, in some
embodiments, is narrower, e.g., from 120 Angstroms to 300
Angstroms. In some embodiments, gate electrode 106a contains
silicon, e.g., polysilicon, and the annealing process causes metal
layer 114 to react with silicon atoms of gate electrode 106a to
form a salicide layer over gate stack 106 as well as over source
and drain features 104.
[0026] If the temperature of semiconductor device 300 is lowered
below a temperature needed for metal layer 114 to react with
silicon, the salicide forming reaction ceases, but unreacted metal
remains in metal layer 114. In operation 214, unreacted metal in
metal layer 114 is removed. In some embodiments, the unreacted
metal is removed using an etching process such as wet etching, dry
etching, reactive ion etching, plasma etching, or another suitable
etching process. FIG. 3G is a side view diagram of semiconductor
device 300 following removal of the unreacted metal.
[0027] The inclusion of cap layers 110 helps to form salicide
layers 116 with sufficient thickness, to prevent the process
removing metal layer 114 in operation 214 from also exposing source
and drain features 104 through portions of salicide layers 116. In
some embodiments where the source and drain features 104 include
silicon germanium, the inclusion of cap layers 110 also aids in
forming salicide layers 116 having reduced amounts of germanium
within the salicide layers. In some embodiments, a germanium
concentration within salicide layers 116 is less than about 3% by
weight. Using conventional techniques which do not include cap
layers 110, a germanium concentration within conventional salicide
layers ranges from about 13% by weight to about 17% by weight.
[0028] Following formation of salicide layers 116, electrical
contacts are connected to salicide layers 116 and electrically
connected to an interconnect structure to incorporate semiconductor
device 300 into a circuit. Including cap layers 110 in the
formation of semiconductor device 300 increases production yield
over formation processes in which cap layers 110 are omitted.
[0029] One aspect of this description relates to a semiconductor
device having a source feature and a drain feature formed in a
substrate. The semiconductor device having a gate stack formed over
a portion of the source feature and formed over a portion of the
drain feature. The semiconductor device further having a first
salicide layer over substantially all of the source feature not
covered by the gate stack, and a second salicide layer over
substantially all of the drain feature not covered by the gate
stack. The first salicide layer and the second salicide layer have
a germanium concentration less than about 3% by weight.
[0030] Another aspect of this description relates to a method of
making a semiconductor device including forming a source feature
and a drain feature in a substrate. The method further including
forming a gate stack over a portion of the source feature and over
a portion of the drain feature. The method further including
depositing a first cap layer over substantially the entire source
feature not covered by the gate stack, and depositing a second cap
layer over substantially the entire drain feature not covered by
the gate stack.
[0031] Still another aspect of this description relates to a
semiconductor device having a source feature and a drain feature
formed in a substrate. The semiconductor device having a gate stack
formed over a portion of the source feature and formed over a
portion of the drain feature, where the gate stack includes a gate
electrode layer and a gate dielectric layer. The semiconductor
device further having a first cap layer formed over substantially
all of the source feature not covered by the gate stack, and a
second cap layer formed over substantially all of the drain feature
not covered by the gate stack, where the first cap layer and the
second cap layer each have a thickness ranging from about 5
Angstroms to about 10 Angstroms. The semiconductor device further
having a metal layer over the gate stack, the first cap layer and
the second cap layer. The metal layer comprising nickel and having
a thickness ranging from about 200 Angstroms to about 400
Angstroms.
[0032] It will be readily seen by one of ordinary skill in the art
that the disclosed embodiments fulfill one or more of the
advantages set forth above. After reading the foregoing
specification, one of ordinary skill will be able to affect various
changes, substitutions of equivalents and various other embodiments
as broadly disclosed herein. It is therefore intended that the
protection granted hereon be limited only by the definition
contained in the appended claims and equivalents thereof.
* * * * *