U.S. patent application number 13/773896 was filed with the patent office on 2013-06-27 for semiconductor package.
The applicant listed for this patent is Chi-Chih Chu, Cheng-Yi Weng. Invention is credited to Chi-Chih Chu, Cheng-Yi Weng.
Application Number | 20130161816 13/773896 |
Document ID | / |
Family ID | 44186454 |
Filed Date | 2013-06-27 |
United States Patent
Application |
20130161816 |
Kind Code |
A1 |
Chu; Chi-Chih ; et
al. |
June 27, 2013 |
SEMICONDUCTOR PACKAGE
Abstract
The present invention relates to a semiconductor package. The
semiconductor package includes a substrate, at least one chip, a
plurality of conductive elements, a plurality of first conductors
and a molding compound. The substrate has a plurality of first pads
and a solder mask. The first pads are exposed to a first surface of
the substrate, and the material of the first pads is copper. The
solder mask is disposed on the first surface, contacts the first
pads directly, and has at least on opening so as to expose part of
the first pads. The chip is mounted on the first surface of the
substrate. The conductive elements electrically connect the chip
and the substrate. The first conductors are disposed on the first
pads. The molding compound is disposed on the first surface of the
substrate, and encapsulates the chip, the conductive elements and
part of the first conductors. Whereby, the solder mask contacts the
first pads directly, and thus results in higher bonding strength,
so as to avoid the bridge between the first conductors caused by
the first conductors permeating into the interface between the
solder mask and the first pads.
Inventors: |
Chu; Chi-Chih; (Kaohsiung,
TW) ; Weng; Cheng-Yi; (Kaohsiung, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Chu; Chi-Chih
Weng; Cheng-Yi |
Kaohsiung
Kaohsiung |
|
TW
TW |
|
|
Family ID: |
44186454 |
Appl. No.: |
13/773896 |
Filed: |
February 22, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12818422 |
Jun 18, 2010 |
8405212 |
|
|
13773896 |
|
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Current U.S.
Class: |
257/738 |
Current CPC
Class: |
H01L 2924/181 20130101;
H01L 2224/73265 20130101; H01L 2924/181 20130101; H01L 23/49816
20130101; H01L 24/48 20130101; H01L 2924/00014 20130101; H01L
2924/15331 20130101; H01L 2224/48227 20130101; H01L 2924/00014
20130101; H01L 23/3128 20130101; H01L 2924/15311 20130101; H01L
2224/45015 20130101; H01L 2924/00 20130101; H01L 2224/48225
20130101; H01L 2924/00012 20130101; H01L 2224/32225 20130101; H01L
2224/48227 20130101; H01L 2224/32225 20130101; H01L 2224/32225
20130101; H01L 2924/00012 20130101; H01L 2224/48227 20130101; H01L
2224/45099 20130101; H01L 2924/207 20130101; H01L 2924/00014
20130101; H01L 2224/73265 20130101; H01L 24/73 20130101; H01L
2224/73265 20130101; H01L 2924/15311 20130101 |
Class at
Publication: |
257/738 |
International
Class: |
H01L 23/498 20060101
H01L023/498 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 31, 2009 |
TW |
098146112 |
Claims
1. A semiconductor package, comprising: a substrate comprising a
top surface, a pad, an anti-oxidation layer, and a solder mask,
wherein the pad is disposed adjacent to the top surface of the
substrate, the solder mask overlies and directly contacts a part of
the pad and defines a solder mask opening so as to expose a
remaining part of the pad, and the anti-oxidation layer is disposed
over the remaining part of the pad exposed by the solder mask
opening; a chip mounted on the substrate; a plurality of conductive
elements electrically connecting the chip and the substrate; a
conductor disposed over the anti-oxidation layer; and a molding
compound disposed over the top surface of the substrate, wherein
the molding compound comprises a first top surface and a second top
surface, a first height of the first top surface of the molding
compound is different from a second height of the second top
surface of the molding compound, and a top end of the conductor is
exposed adjacent to the second top surface of the molding
compound.
2. The semiconductor package of claim 1, wherein the anti-oxidation
layer is a plating layer.
3. The semiconductor package of claim 2, wherein a width of the
plating layer is smaller than a width of the pad.
4. The semiconductor package of claim 1, wherein the conductor is a
solder ball having a hemispherical shape.
5. The semiconductor package of claim 1, wherein the first top
surface of the molding compound overlies the chip and the
conductive elements, and the first height is greater than the
second height.
6. The semiconductor package of claim 1, wherein the top end of the
conductor is substantially coplanar with the second top surface of
the molding compound.
7. The semiconductor package of claim 1, wherein the pad comprises
copper.
8. A semiconductor package, comprising: a substrate comprising a
top surface, a pad, and a solder mask, wherein the pad is disposed
adjacent to the top surface of the substrate, and the solder mask
defines a solder mask opening that partially exposes the pad to
define a covered portion and an uncovered portion of the pad; a
conductor disposed over the uncovered portion of the pad; and a
molding compound disposed over the top surface of the substrate,
wherein the molding compound comprises a first top surface and a
second top surface, the second top surface of the molding compound
is recessed below the first top surface of the molding compound,
and a top end of the conductor is exposed adjacent to the second
top surface of the molding compound.
9. The semiconductor package of claim 8, wherein the solder mask
directly contacts the covered portion of the pad.
10. The semiconductor package of claim 8, wherein the covered
portion of the pad is adjacent to a periphery of the pad.
11. The semiconductor package of claim 8, wherein the substrate
further comprises an anti-oxidation layer disposed over the
uncovered portion of the pad.
12. The semiconductor package of claim 11, wherein the
anti-oxidation layer is inwardly recessed from a periphery of the
pad.
13. The semiconductor package of claim 11, wherein a top surface of
the anti-oxidation layer is recessed below a top surface of the
solder mask.
14. The semiconductor package of claim 8, wherein a width of the
solder mask opening at a top surface of the solder mask is
substantially the same as a width of the solder mask opening
adjacent to the pad.
15. A semiconductor package, comprising: a substrate comprising a
top surface, a pad, and an anti-oxidation layer, wherein the pad is
disposed adjacent to the top surface of the substrate, and the
anti-oxidation layer is disposed over a central part of the pad
while a peripheral part of the pad is exposed by the anti-oxidation
layer; a chip disposed over the top surface of the substrate; a
conductor disposed over the anti-oxidation layer; and a molding
compound disposed over the top surface of the substrate, wherein
the molding compound comprises a first top surface and a second top
surface, the second top surface of the molding compound is recessed
below the first top surface of the molding compound, and a top end
of the conductor is exposed adjacent to the second top surface of
the molding compound.
16. The semiconductor package of claim 15, wherein the substrate
further comprises a solder mask disposed adjacent to the top
surface of the substrate, and the solder mask directly contacts the
peripheral part of the pad.
17. The semiconductor package of claim 16, wherein the solder mask
defines a solder mask opening that exposes the anti-oxidation
layer.
18. The semiconductor package of claim 16, wherein a top surface of
the anti-oxidation layer is recessed below a top surface of the
solder mask.
19. The semiconductor package of claim 15, wherein the
anti-oxidation layer is a plating layer that comprises at least one
of gold and nickel.
20. The semiconductor package of claim 15, wherein the top end of
the conductor is substantially coplanar with the second top surface
of the molding compound.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a divisional of U.S. application Ser. No. 12/818,422
filed Jun. 18, 2010, which claims the benefit of Taiwan Application
Serial No. 098146112 filed Dec. 31, 2009, the disclosures of which
are incorporated herein by reference in their entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor package,
and more particularly to a semiconductor package which can avoid
solder bridge.
[0004] 2. Description of the Related Art
[0005] FIGS. 1 to 4 show schematic views of a method for making a
conventional semiconductor package. As shown in FIG. 1, a substrate
11 is provided. The substrate 11 has a first surface 111, a second
surface 112, a plurality of first pads 113, a plurality of second
pads 114, a Ni/Au plating layer 115 and a solder mask 116. The
first pads 113 are exposed to the first surface 111. The second
pads 114 are exposed to the second surface 112. The Ni/Au plating
layer 115 is formed on the entire upper surface of the first pad
113. The solder mask 116 contacts the Ni/Au plating layer 115
directly, and has at least one opening so as to expose part of the
Ni/Au plating layers 115. Then, a chip 12 is mounted on the
substrate 11, and a plurality of conductive elements (for example,
a plurality of wires 13) are formed so as to electrically connect
the chip 12 and the first surface 111 of the substrate 11. Then, a
plurality of first conductors (for example, a plurality of first
solder balls 14) are formed on the Ni/Au plating layer 115.
[0006] As shown in FIG. 2, a molding compound 15 is formed on the
first surface 111 of the substrate 11, so as to encapsulate the
chip 12, the wires 13 and the first solder balls 14. As shown in
FIG. 3, a plurality of second solder balls 16 are formed on the
second pads 114, and the second solder balls 16 are reflowed. As
shown in FIG. 4, part of a periphery area of the molding compound
15 is removed, so that the molding compound 15 has at least two
heights, and one end of the first solder balls 14 is exposed. Thus,
the conventional semiconductor package 1 is formed.
[0007] The conventional semiconductor package 1 has the following
disadvantages. First, the solder mask 116 contacts the Ni/Au
plating layer 115 directly, however the solder mask 116 and the
Ni/Au plating layer 115 has low bonding strength, therefore
delamination between the solder mask 116 and the Ni/Au plating
layer 115 occurs easily. Moreover, the Ni/Au plating layer 115
disposed on the first solder balls 14 is encapsulated by the
molding compound 15, and when the second solder balls 16 are
reflowed, the first solder balls 14 expand because of high
temperature. Meanwhile, the first solder balls 14 extrude to
adjacent elements and protrude to the interface between the solder
mask 116 and the Ni/Au plating layer 115 which has low bonding
strength. As a result, it leads to the bridge between the first
solder balls 14, as shown in area A of FIGS. 3 to 5, and the yield
rate of the semiconductor package is decreased.
[0008] Therefore, it is necessary to provide a semiconductor
package to solve the above problems.
SUMMARY OF THE INVENTION
[0009] The present invention is directed to a semiconductor
package. The semiconductor package comprises a substrate, at least
one chip, a plurality of conductive elements, a plurality of first
conductors and a molding compound. The substrate has a first
surface, a second surface, a plurality of first pads and a solder
mask. The first pads are exposed to the first surface, and the
material of the first pads is copper. The solder mask directly
contacts the first pads, and has at least one opening so as to
expose part of the first pads. The chip is mounted on the
substrate. The conductive elements electrically connect the chip
and the substrate. The first conductors are disposed on the first
pads. The molding compound is disposed on the first surface of the
substrate, and encapsulates the chip, the conductive elements and
the first conductors. The molding compound has a first top surface
and a second top surface. The horizontal level of the first top
surface is different from that of the second top surface, and one
end of the first conductors is exposed. A top surface of the
exposed first conductors is level with the second top surface of
the molding compound.
[0010] The present invention is further directed to a semiconductor
package. The semiconductor package comprises a substrate, at least
one chip, a plurality of conductive elements, a plurality of first
conductors and a molding compound. The substrate has a first
surface, a second surface, a plurality of first pads and a solder
mask. The first pads are exposed to the first surface, and the
material of the first pads is copper. The solder mask directly
contacts the first pads, and has at least one opening so as to
expose part of the first pads. The chip is mounted on the
substrate. The conductive elements electrically connect the chip
and the substrate. The first conductors are disposed on the first
pads. The molding compound is disposed on the first surface of the
substrate, and encapsulates the chip, the conductive elements and
part of the first conductors. The molding compound has a first
surface and a plurality of blind holes. The blind holes open at the
first surface of the molding compound, and expose part of the first
conductors.
[0011] Whereby, the solder mask contacts the first pads directly,
and thus results in higher bonding strength, so as to avoid the
bridge between the first conductors caused by the first conductors
permeating into the interface between the solder mask and the first
pads.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIGS. 1 to 4 are schematic views of a method for making a
conventional semiconductor package;
[0013] FIG. 5 is a partially enlarged photograph of FIG. 4;
[0014] FIG. 6 is a cross-sectional view of a semiconductor package
according to a first embodiment of the present invention; and
[0015] FIG. 7 is a cross-sectional view of a semiconductor package
according to a second embodiment of the present invention.
DETAILED DESCRIPTION
[0016] FIG. 6 shows a cross-sectional view of a semiconductor
package according to a first embodiment of the present invention.
The semiconductor package 2 comprises a substrate 21, at least one
chip 22, a plurality of conductive elements (for example, a
plurality of wires 23), a plurality of first conductors (for
example, a plurality of first solder balls 24), a molding compound
25 and a plurality of second solder balls 26. The substrate 21 has
a first surface 211, a second surface 212, a plurality of first
pads 213, a plurality of second pads 214, a solder mask 216 and an
anti-oxidation layer 217.
[0017] The first pads 213 are exposed to the first surface 211, and
the material of the first pads 213 is copper. The second pads 214
are exposed to the second surface 212. The solder mask 216 contacts
the first pads 213 directly, and has at least one opening so as to
expose part of the first pads 213. The anti-oxidation layer 217 is
disposed on the first pads 213 exposed to the opening of the solder
mask 216. That is, the anti-oxidation layer 217 does not completely
cover the entire upper surface of the first pad 213. In the
embodiment, the anti-oxidation layer 217 is a Ni/Au plating layer.
However, in other applications, the anti-oxidation layer 217 can be
an organic solderability preservative (OSP), and the anti-oxidation
layer 217 does not exist in the final structure. Therefore, the
present invention can avoid the first pads 213 from oxidizing after
being exposed in the air, and thus the yield rate of the
semiconductor package is increased.
[0018] The chip 22 is mounted on the substrate 21. In the
embodiment, the chip 22 is adhered to the solder mask 216. In the
present invention, the form of the chip 22 has no limitation. The
wires 23 electrically connect the chip 22 and the substrate 21. The
first solder balls 24 are disposed on the first pads 213,
preferably, the first solder balls 24 are hemispheres. The second
solder balls 26 are disposed on the second pads 214.
[0019] The molding compound 25 is disposed on the first surface 211
of the substrate 21, and encapsulates the chip 22, the wires 23 and
the first solder balls 24. The molding compound 25 has a first top
surface 251 and a second top surface 252, the horizontal level of
the first top surface 251 is different from that of the second top
surface 252, and one end of the first solder balls 24 is exposed. A
top surface of the exposed first solder balls 24 is level with the
second top surface 252 of the molding compound 25.
[0020] The molding compound 25 has a first height H.sub.1 and a
second height H.sub.2, the first height H.sub.1 is the height from
the first top surface 251 to the solder mask 216, the second height
H.sub.2 is the height from the second top surface 252 to the solder
mask 216, and the first height H.sub.1 is greater than the second
height H.sub.2.
[0021] FIG. 7 shows a cross-sectional view of a semiconductor
package according to a second embodiment of the present invention.
The semiconductor package 3 comprises a substrate 31, at least one
chip 32, a plurality of conductive elements (for example, a
plurality of wires 33), a plurality of first conductors (for
example, a plurality of first solder balls 34), a molding compound
35 and a plurality of second solder balls 36. The substrate 31 has
a first surface 311, a second surface 312, a plurality of first
pads 313, a plurality of second pads 314, a solder mask 316 and an
anti-oxidation layer 317.
[0022] The first pads 313 are exposed to the first surface 311, and
the material of the first pads 313 is copper. The second pads 314
are exposed to the second surface 312. The solder mask 316 contacts
the first pads 313 directly, and has at least one opening so as to
expose part of the first pads 313. The anti-oxidation layer 317 is
disposed on the first pads 313 exposed to the opening of the solder
mask 316, preferably, the anti-oxidation layer 317 is an organic
solderability preservative (OSP) or a Ni/Au plating layer.
Therefore, the present invention can avoid the first pads 313 from
oxidizing after being exposed in the air, and thus the yield rate
of the semiconductor package is increased.
[0023] The chip 32 is mounted on the substrate 31. In the
embodiment, the chip 32 is adhered to the solder mask 316. In the
present invention, the form of the chip 32 has no limitation. The
wires 33 electrically connect the chip 32 and the substrate 31. The
first solder balls 34 are disposed on the first pads 313. The
second solder balls 36 are disposed on the second pads 314. The
molding compound 35 is disposed on the first surface 311 of the
substrate 31, and encapsulates the chip 32, the wires 33 and part
of the first solder balls 34. The molding compound 35 has a first
surface 351 and a plurality of blind holes 352. The blind holes 352
open at the first surface 351 of the molding compound 35, and
expose part of the first solder balls 34.
[0024] Therefore, the solder masks 216, 316 contact the first pads
213, 313 directly, and thus results in higher bonding strength, so
as to avoid the bridge between the first conductors (the first
solder balls 24, 34) caused by the first conductors (the first
solder balls 24, 34) permeating into the interface between the
solder masks 216, 316 and the first pads 213, 313.
[0025] While several embodiments of the present invention have been
illustrated and described, various modifications and improvements
can be made by those skilled in the art. The embodiments of the
present invention are therefore described in an illustrative but
not restrictive sense. It is intended that the present invention
should not be limited to the particular forms as illustrated, and
that all modifications which maintain the spirit and scope of the
present invention are within the scope defined by the appended
claims.
* * * * *