U.S. patent application number 13/672088 was filed with the patent office on 2013-03-14 for fabrication method for carrier substrate, printed circuit board using the same, and fabrication method thereof.
This patent application is currently assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD.. The applicant listed for this patent is SAMSUNG ELECTRO-MECHANICS CO., LTD.. Invention is credited to Suk Won LEE, Chang Gun Oh, Keung Jin Sohn.
Application Number | 20130062112 13/672088 |
Document ID | / |
Family ID | 44186070 |
Filed Date | 2013-03-14 |
United States Patent
Application |
20130062112 |
Kind Code |
A1 |
LEE; Suk Won ; et
al. |
March 14, 2013 |
FABRICATION METHOD FOR CARRIER SUBSTRATE, PRINTED CIRCUIT BOARD
USING THE SAME, AND FABRICATION METHOD THEREOF
Abstract
A method for fabricating a carrier substrate, a method for
fabricating a printed circuit board using the carrier substrate and
related printed circuit board. The method for fabricating the
carrier substrate includes: providing an insulating base material
with a copper foil layer formed on at least one surface thereof;
stacking a metal layer having a length shorter than that of the
copper foil layer on the copper foil layer; and forming an
insulating layer on the metal layer.
Inventors: |
LEE; Suk Won; (Bucheon,
KR) ; Sohn; Keung Jin; (Seongnam, KR) ; Oh;
Chang Gun; (Hwaseong, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SAMSUNG ELECTRO-MECHANICS CO., LTD.; |
Suwon |
|
KR |
|
|
Assignee: |
SAMSUNG ELECTRO-MECHANICS CO.,
LTD.
Suwon
KR
|
Family ID: |
44186070 |
Appl. No.: |
13/672088 |
Filed: |
November 8, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12805586 |
Aug 6, 2010 |
8344261 |
|
|
13672088 |
|
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Current U.S.
Class: |
174/266 ;
29/852 |
Current CPC
Class: |
Y10T 428/2839 20150115;
H05K 3/007 20130101; Y10T 29/49126 20150115; H05K 2203/0228
20130101; Y10T 29/49128 20150115; Y10T 428/12583 20150115; H05K
3/0097 20130101; Y10T 29/49156 20150115; Y10T 29/49165 20150115;
Y10T 428/12569 20150115; Y10T 29/49155 20150115; H05K 3/428
20130101; H05K 2203/1536 20130101 |
Class at
Publication: |
174/266 ;
29/852 |
International
Class: |
H01K 3/10 20060101
H01K003/10; H05K 1/11 20060101 H05K001/11 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 24, 2009 |
KR |
10-2009-0130841 |
Claims
1. A method for fabricating a carrier substrate, the method
comprising: providing an insulating base material with a copper
foil layer formed on at least one surface thereof; stacking a metal
layer having a length shorter than that of the copper foil layer on
the copper foil layer; and forming an insulating layer on the metal
layer.
2. The method of claim 1, wherein the metal layer is made of at
least one selected from the group consisting of gold (Au), silver
(Ag), zinc (Zn), palladium (Pd), ruthenium (Ru), nickel (Ni),
rhodium (Rh), a lead (Pb) /tin (Sn) alloy, and a nickel (Ni)/gold
(Au) alloy.
3. The method of claim 1, further comprising stacking a second
copper foil layer on the insulating layer after the formation of
the insulating layer.
4. The method of claim 1, further comprising compressing the
insulating layer after the formation of the insulating layer.
5. A method for fabricating a printed circuit board, the method
comprising: providing a carrier substrate including an insulating
base material with a copper foil layer formed on at least one
surface thereof, a metal layer formed on the cooper layer and
having a length shorter than that of the copper foil layer, and an
insulating layer formed on the metal layer; forming a first circuit
layer including a via having an upper land provided on the
insulating layer and a first circuit pattern providing on a first
face of the insulating layer; separating the carrier substrate and
the insulating layer; and forming a second circuit layer including
a second circuit pattern formed on a second face of the insulating
layer, having a line width smaller than a minimum diameter of the
via, and connected with the via.
6. The method of claim 5, wherein the separating of the carrier
substrate and the insulating layer is performed by cutting an inner
side of an end portion of the metal layer.
7. The method of claim 5, wherein the via is formed such that its
diameter becomes smaller toward the second circuit pattern from the
upper land.
8. The method of claim 5, wherein the metal layer is made of at
least one selected from the group consisting of gold (Au), silver
(Ag), zinc (Zn), palladium (Pd), ruthenium (Ru), nickel (Ni),
rhodium (Rh), a lead (Pb) /tin (Sn) alloy, and a nickel (Ni)/gold
(Au) alloy.
9. The method of claim 5, further comprising stacking a second
copper foil layer on the insulating layer after the formation of
the insulating layer.
10. The method of claim 5, further comprising compressing the
insulating layer after the formation of the insulating layer.
11. The method of claim 5, wherein the forming of the first circuit
layer comprises: forming a via hole at the insulating layer;
forming a first plated seed layer on the insulating layer and the
via hole; forming a first dry film pattern for the formation of the
upper land and a second dry film pattern for the formation of the
first circuit pattern on the first plated seed layer; and
performing electroplating to form the first circuit layer.
12. The method of claim 11, wherein the forming of the first and
second dry film patterns comprises: forming a dry film resist on
the first plated seed layer; and exposing and developing the first
film resist.
13. The method of claim 11, further comprising: forming a first
circuit pattern; removing first and second dry film patterns; and
removing the first plated seed layer.
14. The method of claim 5, wherein the forming of the second
circuit layer comprises: forming a second plated seed layer on the
second face and the via; forming a third dry film pattern for the
formation of the second circuit pattern on the second plated seed
layer; and performing electroplating to form the second circuit
pattern.
15. The method of claim 14, wherein the forming of the third dry
film pattern comprises: forming a dry film resist on the second
plated seed layer; and exposing and developing the dry film
resist.
16. The method of claim 14, further comprising: removing the third
dry film pattern; and removing the second plated seed layer, after
the formation of the second circuit pattern.
17. A printed circuit board comprising: a first circuit layer
provided on an insulating layer and comprising a via having an
upper land and a first circuit pattern provided on a first face of
the insulating layer; and a second circuit layer provided on a
second face of the insulating layer and comprising a second circuit
pattern having a line width smaller than a minimum diameter of the
via, and connected with the via.
18. The printed circuit board of claim 17, wherein the via has a
shape such that its diameter becomes smaller toward the second
circuit pattern from the upper land.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a U.S. divisional application filed
under 37 CFR 1.53(b) claiming priority benefit of U.S. Ser. No.
12/805,586 filed in the United States on Aug. 6, 2010, which claims
earlier priority benefit to Korean Patent Application No.
10-2009-0130841 filed with the Korean Intellectual Property Office
on Dec. 24, 2009, the disclosures of which are incorporated herein
by reference.
BACKGROUND
[0002] 1. Field
[0003] The present invention relates to a carrier substrate, a
fabrication method thereof, a printed circuit board using the same,
and a fabrication method thereof, and more particularly, to a
carrier substrate without a land in a via and a core in the
substrate, a fabrication method thereof, a printed circuit board
using the same, and a fabrication method thereof.
[0004] 2. Description of the Related Art
[0005] A printed circuit board (PCB) is used to allow the
components of an electronic device to be mounted thereon and for
wirings. The PCB is configured such that a thin plate made of
copper or the like is attached on one surface of a phenol resin
insulating plate or an epoxy resin insulating plate and is
subsequently etched according to the wiring patterns of circuits
(i.e., corroded so as to be removed while leaving circuits in
lines) to form required circuits and a hole is formed to allow
components to be attached and mounted thereon.
[0006] PCBs include a single sided PCB with wirings formed only on
one side of an insulating substrate, a double-sided PCB with
wirings formed on both sides of an insulating layer, and a
multi-layer PCB with wirings formed on multiple layers. In the
past, component elements and circuit patterns are simple to fit
onto the single side PCB, but recently, as circuits have become
increasingly complicated and the demands placed on a circuit having
high density have grown, double-sided PCBs or multi-layer PCBs are
generally used.
[0007] The multi-layer PCB is configured by alternately stacking
circuit layers and insulating layers. This structure needs a via to
electrically connect the inner circuit layer and the outer circuit
layer through the insulating layer. The manufacturing of the
multilayer PCB through a build-up process necessarily accompanies a
process of forming a via hole in the insulating layer stacked on
the inner circuit layer, which can be electrically connected with
the outer circuit layer.
[0008] In this case, a land is necessarily formed at a portion
connected with an upper circuit layer through the via hole for a
stable electrical connection between the layers. The land is
designed in consideration of a processing error in mechanical
processing to form the via, an error of exposing facilities used
for forming the upper circuit layer, and deformation of a raw
material in use during a process. The deviation in the facilities,
materials, and processes is unavoidable, so the designing of a land
has been considered natural in order to increase productivity and a
processing yield.
[0009] However, advancements in the electronic industry have
promoted the development of high-integrated semiconductors and
accelerated the reduction in size of electronic components, so, in
line with this, PCBs on which the electronic components are to be
mounted are now required to be smaller, thinner, and more highly
integrated. To this end, efforts to make the wirings of PCBs finer,
and to reduce the space of the via have continued, but the presence
of the land restricts the high integration of PCBs. Also, a
matching force of laser facilities for forming the via has been
improved to enhance interlayer matching of the highly integrated
substrate, and new high-matching exposure facilities have been
developed to form fine circuits, but improvements of these
facilities require a great deal of time and, basically, these
facilities have a limitation in that they cannot completely remove
a land.
SUMMARY
[0010] An aspect of the present invention provides a carrier
substrate without having a land in a via and a core in the
substrate to allow for the formation of a fine circuit pattern and
make the substrate thinner and having a landless via hole that can
be easily connected with the circuit pattern which is connected
with the via, a fabrication method thereof, a printed circuit board
using the same, and a fabrication method thereof.
[0011] According to an aspect of the present invention, there is
provided a method for fabricating a carrier substrate, including:
providing an insulating base material with a copper foil layer
formed on at least one surface thereof; stacking a metal layer
having a length shorter than that of the copper foil layer on the
copper foil layer; and forming an insulating layer on the metal
layer.
[0012] The metal layer may be made of at least one selected from
the group consisting of gold (Au), silver (Ag), zinc (Zn),
palladium (Pd), ruthenium (Ru), nickel (Ni), rhodium (Rh), a lead
(Pb)/tin (Sn) alloy, and a nickel (Ni)/gold (Au) alloy.
[0013] The method may further include: stacking a second copper
foil layer on the insulating layer after the formation of the
insulating layer.
[0014] The method may further include: compressing the insulating
layer after the formation of the insulating layer.
[0015] According to another aspect of the present invention, there
is provided a carrier substrate including: an insulating base
material with a copper foil layer formed on at least one surface
thereof; a metal layer formed on the cooper layer and having a
length shorter than that of the copper foil layer; and an
insulating layer formed on the metal layer.
[0016] The metal layer may be made of at least one selected from
the group consisting of gold (Au), silver (Ag), zinc (Zn),
palladium (Pd), ruthenium (Ru), nickel (Ni), rhodium (Rh), a lead
(Pb) /tin (Sn) alloy, and a nickel (Ni)/gold (Au) alloy.
[0017] The carrier substrate may further include: a second copper
foil layer formed on the insulating layer.
[0018] According to another aspect of the present invention, there
is provided a method for fabricating a printed circuit board (PCB),
including: providing a carrier substrate including an insulating
base material with a copper foil layer formed on at least one
surface thereof, a metal layer formed on the cooper layer and
having a length shorter than that of the copper foil layer, and an
insulating layer formed on the metal layer; forming a first circuit
layer including a via having an upper land provided on the
insulating layer and a first circuit pattern providing on a first
face of the insulating layer; separating the carrier substrate and
the insulating layer; and forming a second circuit layer including
a second circuit pattern formed on a second face of the insulating
layer, having a line width smaller than a minimum diameter of the
via, and connected with the via.
[0019] The separating of the carrier substrate and the insulating
layer may be performed by cutting an inner side of an end portion
of the metal layer.
[0020] The via may be formed such that its diameter becomes smaller
toward the second circuit pattern from the upper land.
[0021] The metal layer may be made of at least one selected from
the group consisting of gold (Au), silver (Ag), zinc (Zn),
palladium (Pd), ruthenium (Ru), nickel (Ni), rhodium (Rh), a lead
(Pb) /tin (Sn) alloy, and a nickel (Ni)/gold (Au) alloy.
[0022] The method may further include: stacking a second copper
foil layer on the insulating layer after the formation of the
insulating layer.
[0023] The method may further include: compressing the insulating
layer after the formation of the insulating layer.
[0024] The forming of the first circuit layer may include: forming
a via hole at the insulating layer; forming a first plated seed
layer on the insulating layer and the via hole; forming a first dry
film pattern for the formation of the upper land and a second dry
film pattern for the formation of the first circuit pattern on the
first plated seed layer; and performing electroplating to form the
first circuit layer.
[0025] The forming of the first and second dry film patterns may
include: forming a dry film resist on the first plated seed layer;
and exposing and developing the first film resist.
[0026] The method may further include: forming a first circuit
pattern; removing first and second dry film patterns; and removing
the first plated seed layer.
[0027] The forming of the second circuit layer may include: forming
a second plated seed layer on the second face and the via; forming
a third dry film pattern for the formation of the second circuit
pattern on the second plated seed layer; and performing
electroplating to form the second circuit pattern.
[0028] The forming of the third dry film pattern may include:
forming a dry film resist on the second plated seed layer; and
exposing and developing the dry film resist.
[0029] The method may further include: removing the third dry film
pattern; and removing the second plated seed layer, after the
formation of the second circuit pattern.
[0030] According to another aspect of the present invention, there
is provided a printed circuit board (PCB) including: a first
circuit layer provided on an insulating layer and comprising a via
having an upper land and a first circuit pattern provided on a
first face of the insulating layer; and a second circuit layer
provided on a second face of the insulating layer and comprising a
second circuit pattern having a line width smaller than a minimum
diameter of the via, and connected with the via.
[0031] The via may have a shape such that its diameter becomes
smaller toward the second circuit pattern from the upper land.
BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The above and other aspects, features and other advantages
of the present invention will be more clearly understood from the
following detailed description taken in conjunction with the
accompanying drawings, in which:
[0033] FIGS. 1A to 1D are sequential sectional views schematically
showing a carrier substrate and its fabrication process according
to an exemplary embodiment of the present invention;
[0034] FIGS. 2A to 2G are sequential sectional views schematically
showing a printed circuit board (PCB) fabricated by using the
carrier substrate, and its fabrication process according to an
exemplary embodiment of the present invention; and
[0035] FIGS. 3A and 3B are schematic plan views for explaining the
advantage of removing a lower land of the PCB according to an
exemplary embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
[0036] Exemplary embodiments of the present invention will now be
described in detail with reference to the accompanying drawings.
The invention may, however, be embodied in many different forms and
should not be construed as being limited to the embodiments set
forth herein. Rather, these embodiments are provided so that this
disclosure will be thorough and complete, and will fully convey the
scope of the invention to those skilled in the art. In the
drawings, the shapes and dimensions may be exaggerated for clarity,
and the same reference numerals will be used throughout to
designate the same or like components.
[0037] A carrier substrate and fabrication method thereof according
to an exemplary embodiment of the present invention will now be
described with reference to FIGS. 1a to 1h.
[0038] With reference to FIG. 1A, a carrier substrate 10 according
to an exemplary embodiment of the present invention includes an
insulating base material 11, metal layers 13a and 13b, and
insulating layers 14a and 14b.
[0039] Here, copper foil layers 12a and 12b are formed on at least
one surface of the insulating base material 11.
[0040] The metal layers 13a and 13b are provided on the copper foil
layers 12a and 12b, and in this case, the metal layers 13a and 13b
may be made of at least one selected from the group consisting of
gold (Au), silver (Ag), zinc (Zn), palladium (Pd), ruthenium (Ru),
nickel (Ni), rhodium (Rh), a lead (Pb) /tin (Sn) alloy, and a
nickel (Ni)/gold (Au) alloy. Here, the metal layers 13a and 13b are
shorter than the copper foil layers 12a and 12b.
[0041] The insulating layers 14a and 14b are formed on the metal
layers 13a and 13b, and second copper foil layers 15a and 15b are
provided on the insulating layers 14a and 14b.
[0042] As shown in FIG. 1 B, the copper foil layers 12a and 12b are
formed on at least one surface of the insulating base material
11.
[0043] Next, as shown in FIG. 1C, the metal layers 13a and 13b are
stacked on the copper foil layers 12a and 12b. Here, the metal
layers 13a and 13b are formed to have a length shorter than that of
the copper foil layers 12a and 12b. The metal layers 13a and 13b
are formed to be shorter than the copper foil layers 12a and 12b so
as to facilitate the separation of the carrier substrate 10 and the
insulating layers 14a and 14b after a build-up process is performed
by using the carrier substrate 10.
[0044] Thereafter, as shown in FIG. 1D, insulating layers 14a and
14b, as well as the second copper foil layers 15a and 15b, another
group of copper foil layers, are formed on the metal layers 13a and
13b and then compressed to form the carrier substrate 10 according
to an exemplary embodiment of the present invention as shown in
FIG. 1A.
[0045] Here, generally, the process of compressing the insulating
layers 14a and 14b is performed under the conditions of high
temperature and high pressure. Thus, preferably, the compressing
process is performed after the second copper foil layers 15a and
15b that can tolerate, without being deformed, the conditions of
the high temperature and high pressure are formed on the insulating
layers 14a and 14b.
[0046] A printed circuit board (PCB) fabricated by using the
carrier substrate and its fabrication process according to an
exemplary embodiment of the present invention will now be described
with reference to FIGS. 2A to 2H.
[0047] With reference to FIG. 2A, PCBs 100A and 100B according to
an exemplary embodiment of the present invention include first
circuit layers 30a and 30b, including vias 31a and 31b provided on
the insulating layers 14a and 14b and first circuit patterns 35a
and 35b provided on first faces of the insulating layers 14a and
14b, and second circuit layers 50a and 50b formed on second faces
of the insulating layers 14a and 14b and including second circuit
patterns 51a and 51b connected with the vias 31a and 31b.
[0048] Here, the vias 31a and 31b include upper lands 33a and 33b
and have a shape whose diameter is reduced toward the second
circuit patterns 51a and 51b starting from the upper lands 33a and
33b.
[0049] The second circuit patterns 51a and 51b have a line width
smaller than a minimum diameter of the vias 31a and 31b and are
connected with the vias 31a and 31b.
[0050] With reference to FIG. 2B, the carrier substrate 10, which
includes the insulating base material 11 with the copper foil
layers 12a and 12b formed on at least one surface thereof, the
metal layers 13a and 13b formed on the copper foil layers 12a and
12b and have a length shorter than that of the copper foil layers
12a and 12b, and the insulating layer 14a and 14b formed on the
metal layers 13a and 13b, is provided.
[0051] The metal layers 13a and 13b provided on the copper foil
layers 12a and 12b may be made of at least one selected from among
gold (Au), silver (Ag), zinc (Zn), palladium (Pd), ruthenium (Ru),
nickel (Ni), rhodium (Rh), a lead (Pb) /tin (Sn) alloy, and a
nickel (Ni)/gold (Au) alloy. Here, the metal layers 13a and 13b are
shorter than the copper foil layers 12a and 12b.
[0052] The insulating layers 14a and 14b are formed on the metal
layers 13a and 13b, and the second copper foil layers 15a and 15b,
another group of copper foil layers, are provided on the insulating
layers 14a and 14b.
[0053] With reference to FIG. 2C, after the second copper foil
layers 15a and 15b formed on at least one surface of the insulating
base material 11 are removed, via holes O and P are formed through
the insulating layers 14a and 14b. The via holes O and P may be
formed in various manners, and laser equipment is generally used
for a process of forming a high density (or highly integrated)
wiring. When the via holes O and P are formed by using the laser
equipment, the via holes O and P generated at the insulating layers
14a and 14b to which laser is input are larger than the via holes O
and P generated at the opposite insulating layers from which laser
is output.
[0054] Subsequently, first plated seed layers 20a and 20b are
formed on the insulating layers 14a and 14b and on the via holes O
and P. Subsequently, first dry film patterns 21a and 21b to be used
for forming the upper lands 33a and 33b as shown in FIG. 2D, and
second dry film patterns 25a and 25b to be used for forming the
first circuit patterns 35a and 35b are formed.
[0055] Here, the first dry film patterns 21a and 21b and the second
dry film patterns 25a and 25b may be formed by forming a dry film
resist (not shown) formed on the first plated seed layers 20a and
20b and then exposing and developing the dry film resist.
[0056] Thereafter, as shown in FIG. 2D, the first circuit layers
30a and 30b are formed on the first plated seed layers 20a and 20b
through electroplating (or electrodeposition)
[0057] Here, the first plated seed layers 20a and 20b, which may be
chemical copper plating layers formed through electroless plating,
serve as electrodes for the first circuit layers 30a and 30b formed
through electroplating afterward. Here, the first circuit layers
30a and 30b are formed through electroplating, but the method of
forming the first circuit layers 30a and 30b is not limited
thereto. For example, the first circuit layers 30a and 30b may be
formed through electroless plating without the first plated seed
layers 20a and 20b.
[0058] Here, the vias 31a and 31b include the upper lands 33a and
33b and have a shape such that their diameter diminishes toward the
second circuit patterns 51a and 51b as shown in FIG. 2A, which is
to be formed afterward, starting from the upper lands 33a and
33b.
[0059] After the first circuit layers 30a and 30b are formed, the
first dry film patterns 21a and 21b and the second dry film
patterns 25a and 25b are removed, and the first plated seed layers
20a and 20b formed at an area other than the area of the first
circuit layers 30a and 30b are also removed through flash etching
or the like.
[0060] Next, the carrier substrate 10 and the insulating layers 14a
and 14b are cut along a cut line in FIG. 2D. In this case, an inner
side of the end portions of the metal layers 13a and 13b is cut.
Because the metal layers 13a and 13b are shorter than the copper
foil layers 12a and 12b, the carrier substrate 10 and the
insulating layers 14a and 14b can be easily detached by cutting the
inner side of the end portions of the metal layers 13a and 13b as
shown in FIG. 2e.
[0061] In this manner, after the carrier substrate 10 is employed
and then the core removed, thus obtaining the PCBs 100A and 100B
which are thinner and smaller and have a reduced number of
layers.
[0062] Subsequently, as shown in FIG. 2F, the metal layers 13a and
13b are removed. Here, the metal layers 13a and 13b are made of a
metal different to that of the copper foil layers 12a and 12b
formed on at least one surface of the insulating base material 11.
Because the metal layers 13a and 13b are etched under different
conditions from the etching conditions of the copper foil layers
12a and 12b, they can also serve to protect the via holes O and
P.
[0063] Thereafter, as shown in FIG. 2G, the second plated seed
layers 40a and 40b are formed on the second face of the insulating
layers 14a and 14b and on the vias 31a and 31b, from which the
metal layers 13a and 13b have been removed. And then, the third dry
film patterns 41a, 41b, 45a and 45b to be used for forming the
second circuit patterns 51a and 51b of FIG. 2A are formed on the
second plated seed layers 40a and 40b of the second face.
[0064] Here, the third dry film patterns 41a, 41b, 45a, and 45b may
be formed by forming a dry film resist (not shown) on the second
plated seed layers 40a and 40b and then exposing and developing the
dry film resist.
[0065] Subsequently, as shown in FIG. 2A, the second circuit layers
50a and 50b are formed on the second plated seed layers 40a and 40b
through electroplating. Here, the second circuit layers 50a and 50b
have a line width smaller than a minimum diameter of the vias 31a
and 31b, and include second circuit patterns 51a and 51b connected
with the vias 31a and 31b.
[0066] Here, the second plated seed layers 40a and 40b, which may
be chemical copper plating layers formed through electroless
plating, serve as electrodes for the second circuit layers 50a and
50b formed through electroplating afterward. Here, the second
circuit layers 50a and 50b are formed through electroplating, but
the method of forming the second circuit layers 50a and 50b is not
limited thereto. For example, the second circuit layers 50a and 50b
may be formed through electroless plating without the second plated
seed layers 40a and 40b.
[0067] After the second circuit layers 50a and 50b are formed, the
third dry film patterns 41a, 41b, 45a, and 45b are removed, and the
second plated seed layers 40a and 40b formed at an area other than
the area of the second circuit layers 50a and 50b are also removed
through flash etching or the like to complete the PCBs 100A and
100B as shown in FIG. 2A.
[0068] The advantages of removing a lower land connected with a
semiconductor circuit as in the exemplary embodiment of the present
invention as described above will now be described briefly with
reference to FIGS. 3A and 3B.
[0069] With reference to FIG. 3A, in a PCB fabricated through the
related art method, when the pitch between vias V and V1 is 240
.quadrature.m, only one circuit pattern (C) is allowed to be formed
between the adjacent vias V and V1. In comparison, with reference
to FIG. 3B, when the vias 31a and 31b are formed through the method
according to the exemplary embodiment of the present invention, a
circuit can be designed such that the pitch between the vias 31a
and 31b is reduced in the same fine circuit and two second circuit
patterns 51a and 51b are formed between the vias 31a and 31b.
Accordingly, an electronic device can become compact and have a
high density, and in addition, the size of the PCB can be reduced
and the number of layers of the multi-layer substrate can be
reduced, thus lowering the fabrication cost of the PCB.
[0070] As set forth above, according to exemplary embodiments of
the invention, because there is no land at the via and core in the
substrate, because a circuit pattern connected with the via can be
formed to be finer, so the circuit pattern can be highly integrated
and the substrate can become thinner. Thus, a printed circuit board
(PCB) having a smaller size and reduced number of layers can be
fabricated.
[0071] Also, because a resist layer having an opening hole matched
with a via hole of the substrate is formed by using the
characteristics of a electrodeposited photosensitive resist, the
coreless PCB having a landless via can be fabricated through a
simpler fabrication process.
[0072] While the present invention has been shown and described in
connection with the exemplary embodiments, it will be apparent to
those skilled in the art that modifications and variations can be
made without departing from the spirit and scope of the invention
as defined by the appended claims.
* * * * *