U.S. patent application number 13/183468 was filed with the patent office on 2013-01-17 for testing electronic memories based on fault and test algorithm periodicity.
This patent application is currently assigned to SYNOPSYS INC.. The applicant listed for this patent is Aram HAKHUMYAN, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian. Invention is credited to Aram HAKHUMYAN, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian.
Application Number | 20130019130 13/183468 |
Document ID | / |
Family ID | 47519656 |
Filed Date | 2013-01-17 |
United States Patent
Application |
20130019130 |
Kind Code |
A1 |
HAKHUMYAN; Aram ; et
al. |
January 17, 2013 |
TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM
PERIODICITY
Abstract
Testing electronic memories based on fault and test algorithm
periodicity. A processor unit for testing an electronic memory
includes a built-in self-test (BIST) finite state machine, an
address generator, a data generator, a test algorithm generation
unit, a programmable test algorithm register, and a test algorithm
register control unit. A memory wrapper unit for testing an
electronic memory includes an operation decoder, a data comparator,
and an electronic memory under test. The method includes
constructing a fault periodic table having columns corresponding
with test mechanisms, and rows corresponding with fault families. A
first March test sequence and second March test sequence are
selected according to respective fault families and test
mechanisms, and applied to an electronic memory. The electronic
memory under test is determined to be one of acceptable and
unacceptable based on results of the first March test sequence and
the second March test sequence.
Inventors: |
HAKHUMYAN; Aram; (Yerevan,
AM) ; Harutyunyan; Gurgen; (Abovyan, AM) ;
Shoukourian; Samvel; (Yerevan, AM) ; Vardanian;
Valery; (Yerevan, AM) ; Zorian; Yervant;
(Santa Clara, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
HAKHUMYAN; Aram
Harutyunyan; Gurgen
Shoukourian; Samvel
Vardanian; Valery
Zorian; Yervant |
Yerevan
Abovyan
Yerevan
Yerevan
Santa Clara |
CA |
AM
AM
AM
AM
US |
|
|
Assignee: |
SYNOPSYS INC.
Mountain View
CA
|
Family ID: |
47519656 |
Appl. No.: |
13/183468 |
Filed: |
July 15, 2011 |
Current U.S.
Class: |
714/718 ;
714/E11.169; 714/E11.177 |
Current CPC
Class: |
G11C 29/18 20130101;
G11C 29/16 20130101; G11C 29/36 20130101; G11C 29/10 20130101; G11C
2029/0405 20130101; G06F 11/27 20130101 |
Class at
Publication: |
714/718 ;
714/E11.169; 714/E11.177 |
International
Class: |
G11C 29/12 20060101
G11C029/12; G06F 11/263 20060101 G06F011/263; G06F 11/27 20060101
G06F011/27 |
Claims
1. A processor unit for testing an electronic memory, the processor
unit comprising: a built-in self-test (BIST) finite state machine
that coordinates a plurality of BIST functions of the processor
unit; an address generator in communication with the BIST finite
state machine to generate addresses of memory cells for the
testing; a data generator in communication with the BIST finite
state machine that generates data patterns to be applied to the
electronic memory; a test algorithm generation unit that generates
March tests to be applied to the electronic memory; a programmable
test algorithm register in communication with the test algorithm
generation unit that stores one or more March elements generated by
the test algorithm generator unit; and a test algorithm register
control unit, coupled between the BIST finite state machine and the
programmable test algorithm register, that enables the BIST finite
state machine to determine presence of the one or more March
elements stored in the programmable test algorithm register.
2. The processor unit as claimed in claim Error! Reference source
not found., wherein the processor unit comprises an application
specific integrated circuit.
3. The processor unit as claimed in claim 1, wherein the test
algorithm generation unit comprises a fault periodic table unit and
a test algorithm template unit.
4. The processor unit as claimed in claim 3, wherein the fault
periodic table unit comprises a plurality of columns, each of the
plurality of columns corresponding to a functionality of a test
mechanism, and a plurality of rows, each of the plurality of rows
corresponding to a fault family.
5. The processor unit as claimed in claim 3, wherein the test
algorithm template unit comprises a sequence of test operations, an
initial value of a faulty memory cell, a final value of a faulty
memory cell upon completion of the sequence of test operations, and
a March test.
6. The processor unit as claimed in claim 1, wherein the data
generator comprises a programmable background pattern register, a
predefined background pattern register, and a multiplexer
responsive to a pattern type command from the BIST finite state
machine to select the test data output from one of the programmable
background pattern register and the predefined background pattern
register.
7. The processor unit as claimed in claim 1, wherein the
programmable test algorithm register comprises at least one March
element descriptor and a plurality of March operation
descriptors.
8. The processor unit as claimed in claim Error! Reference source
not found., wherein the March element descriptor comprises a
plurality of sub-fields indicating marker, pattern type, addressing
mode, addressing type, addressing direction, and number of
operations.
9. The processor unit as claimed in claim 7, wherein the plurality
of March operation descriptors comprises an inverse pattern
sub-field and opcode sub-fields.
10. The processor unit as claimed in claim 7, wherein the plurality
of March operation descriptors comprises one or more of a
memory-enable operation code, a memory-read operation code, and a
memory-write operation code.
11. The processor unit as claimed in claim 1, wherein the test
algorithm register control unit enables configuration of the
address generator and the data generator prior to test operation
execution, and provides to the BIST finite state machine control
over the programmable test algorithm register.
12. The processor unit as claimed in claim 1, wherein the BIST
finite state machine extends over a sequence of states that
comprises an idle state wherein the BIST finite state machine
awaits an external signal to start performing the plurality of BIST
functions, a reset state wherein the BIST finite state machine
resets a plurality of registers within the processor unit, and into
which state the BIST finite state machine enters upon exiting the
idle state, a check state wherein the BIST finite state machine
checks the one or more March elements stored in the programmable
test algorithm register, and into which state the BIST finite state
machine enters upon exiting the reset state, an exec state wherein
the BIST finite state machine executes the one or more March
elements checked in the check state, and into which state the BIST
finite state machine enters upon exiting the check state, a shift
state wherein the BIST finite state machine shifts the programmable
test algorithm register to a next sequential element, and into
which state the BIST finite state machine enters upon exiting the
exec state if the next sequential element is included in the
programmable test algorithm register, a roll state wherein the BIST
finite state machine shifts the programmable test algorithm
register to a starting position, and into which state the BIST
finite state machine enters upon exiting the exec state if the next
sequential element is excluded in the programmable test algorithm
register, a done state wherein the BIST finite state machine awaits
the de-assertion of the external signal indicating start of the
plurality of BIST functions, into which state the BIST finite state
machine enters upon exiting the roll state, and from which state
the BIST finite state machine enters the idle state upon the
de-assertion of the external signal.
13. A memory wrapper unit for testing an electronic memory, the
memory wrapper unit comprising: an operation decoder that
interprets an operation code; a data comparator that compares a
test data output with a data output from the electronic memory
under test; and the electronic memory under test being in
communication with the operation decoder and the data
comparator.
14. The memory wrapper unit as claimed in claim 13, wherein the
operation decoder comprises a programmable operations register, a
predefined operations register, and a multiplexer responsive to an
operation code command to select a memory control signal to be
transmitted to the electronic memory from one of the programmable
operations register and the predefined operations register.
15. The memory wrapper unit as claimed in claim 14, wherein the
programmable operations register comprises a table that maps
programmable codes to operations on the electronic memory under
test.
16. The memory wrapper unit as claimed in claim 13, wherein the
operation code is received from a built-in self-test (BIST) finite
state machine in a processor unit.
17. The memory wrapper unit as claimed in claim 13, wherein the
test data output is received from a data generator in a processor
unit.
18. The memory wrapper unit as claimed in claim 13, wherein the
electronic memory under test is in communication with an address
generator and a data generator comprised in a processor unit.
19. A method of testing an electronic memory, the method
comprising: constructing a fault periodic table having a plurality
of columns and a plurality of rows, each of the plurality of
columns corresponding with a functionality of a test mechanism of a
plurality of test mechanisms, and each of the plurality of rows
corresponding with a fault family of a plurality of fault families;
selecting a first March test sequence according to a first fault
family of the plurality of fault families and a first test
mechanism of the plurality of test mechanisms; applying the first
March test sequence to the electronic memory; selecting a second
March test sequence according to a second fault family of the
plurality of fault families and a second test mechanism of the
plurality of test mechanisms; applying the second March test
sequence to the electronic memory; and determining if the
electronic memory under test is one of acceptable and unacceptable
based on results of the first March test sequence and the second
March test sequence.
20. The method as claimed in claim 19, wherein the test mechanism
comprises one or more of a background pattern, an addressing mode,
an addressing type, and concurrency of operations within the test
mechanism.
21. The method as claimed in claim 19, wherein the electronic
memory is tested for the plurality of fault families.
22. The method as claimed in claim 21, wherein the electronic
memory is unacceptable based on failure of one or more of the first
March test sequence and the second March test sequence.
23. The method as claimed in claim 19, wherein the results are used
to extend the fault periodic table by creating a new fault
family.
24. The method as claimed in claim 19, wherein the results are used
to extend the fault periodic table by creating another test
mechanism.
25. The method as claimed in claim 19, wherein the first March test
sequence and the second March test sequence each represent a March
test.
26. The method as claimed in claim 25, wherein the March test is
generated by: writing a final value of a faulty memory cell along
an arbitrary order of addresses, executing a sequence of test
operations along the increasing order of the addresses, executing a
logical opposite of the sequence of test operations along the
increasing order of the addresses, executing the sequence of test
operations along a decreasing order of the addresses, executing the
logical opposite of the sequence of test operations along the
decreasing order of the addresses, and reading the final value of
the faulty memory cell along the arbitrary order of the
addresses.
27. The method as claimed in claim 26, wherein the March test is
executed if an initial value of the faulty memory cell equals the
final value of the faulty memory cell and if a first operation of
the sequence of test operations is a read operation.
28. The method as claimed in claim 26, wherein the March test is
one of (W(A1)); (TO); (.about.TO); (TO); (.about.TO); (R(A1)),
(W(A1)); (TO); (.about.TO); (TO); (.about.TO); (R(A1)), (W(A1));
(TO); (.about.TO); (TO); (.about.TO); (R(A1)), and (W(A1)); (TO);
(.about.TO); (TO); (.about.TO); (R(A1)).
29. The method as claimed in claim 25, wherein the March test is
generated by: writing a final value of a faulty memory cell along
an arbitrary order of addresses, reading the final value of the
faulty memory cell to execute a sequence of test operations along
the increasing order of the addresses, reading a logical opposite
of the final value of the faulty memory cell to execute a logical
opposite of the sequence of test operations along the increasing
order of the addresses, reading the final value of the faulty
memory cell to execute the sequence of test operations along a
decreasing order of the addresses, reading the logical opposite of
the final value of the faulty memory cell to execute the logical
opposite of the sequence of test operations along the decreasing
order of the addresses, and reading the final value of the faulty
memory cell along the arbitrary order of the addresses.
30. The method as claimed in claim 28, wherein the March test is
executed if an initial value of the faulty memory cell equals the
final value of the faulty memory cell and if a first operation of
the sequence of test operations is other than a read operation.
31. The method as claimed in claim 29, wherein the March test is
one of (W(A1)); (R(A1), TO); (R(.about.A1), .about.TO); (R(A1),
TO); (R(.about.A1), .about.TO); (R(A1)), and (W(A1)); (R(A1), TO);
(R(.about.A1), .about.TO); (R(A1), TO); (R(.about.A1), .about.TO);
(R(A1)), and (W(A1)); (R(A1), TO); (R(.about.A1), .about.TO);
(R(A1), TO); (R(.about.A1), .about.TO); (R(A1)), and (W(A1));
(R(A1), TO); (R(.about.A1), .about.TO); (R(A1), TO); (R(.about.A1),
.about.TO); (R(A1)).
32. The method as claimed in claim 25, wherein the March test is
generated by: writing a final value of a faulty memory cell along
an arbitrary order of addresses, reading the final value of the
faulty memory cell to subsequently write an initial value of the
faulty memory cell and execute a sequence of test operations along
the increasing order of the addresses, reading a logical opposite
of the final value of the faulty memory cell to subsequently write
a logical opposite of the initial value of the faulty memory cell
and execute a logical opposite of the sequence of test operations
along the increasing order of the addresses, reading the final
value of the faulty memory cell to subsequently write the initial
value of the faulty memory cell and execute the sequence of test
operations along a decreasing order of the addresses, reading the
logical opposite of the final value of the faulty memory cell to
subsequently write the logical opposite of the initial value of the
faulty memory cell and execute the logical opposite of the sequence
of test operations along the decreasing order of the addresses, and
reading the final value of the faulty memory cell along the
arbitrary order of the addresses.
33. The method as claimed in claim 30, wherein the March test is
executed if the initial value of the faulty memory cell is unequal
to the final value of the faulty memory cell.
34. The method as claimed in claim 32, wherein the March test is
one of (W(A1)); (R(A1), W(A2), TO); (R(.about.A1), W(.about.A2),
.about.TO); (R(A1), W(A2), TO)); (R(.about.A1), W(.about.A2),
.about.TO); (R(A1)), (W(A1)); (R(A1), W(A2), TO); (R(.about.A1),
W(.about.A2), .about.TO); (R(A1), W(A2), TO)); (R(.about.A1),
W(.about.A2), .about.TO); (R(A1)), (W(A1)); (R(A1), W(A2), TO);
(R(.about.A1), W(.about.A2), .about.TO); (R(A1), W(A2), TO));
(R(.about.A1), W(.about.A2), .about.TO); (R(A1)), (W(A1)); (R(A1),
W(A2), TO); (R(.about.A1), W(.about.A2), .about.TO); (R(A1), W(A2),
TO)); (R(.about.A1), W(.about.A2), .about.TO); (R(A1)).
Description
TECHNICAL FIELD
[0001] Embodiments of the disclosure relate to testing of
electronic memories based on fault and test algorithm
periodicity.
BACKGROUND
[0002] Electronic memories can suffer from faults in a variety of
modes. For example, in a stuck-at fault (SAF), a memory cell can
remain constant at logical 0 or logical 1. In another example of a
failure mode, in a deceptive read destructive fault (DRDF), a
memory cell can flip state during a read operation but return an
original correct value. Similarly, there are numerous other failure
modes.
[0003] A built-in self-test (BIST) allows an electronic memory to
be tested. The electronic memory can be subjected to the BIST
either periodically, upon power-up, in response to an external
signal or condition, or under other circumstances. A BIST test
algorithm in the BIST typically comprises many elements, referred
to as March elements. A March element includes a sequence of
operations, for example write-0, write-1, and read-1, which are
applied to a given memory cell before proceeding to a next memory
cell. The BIST can proceed from memory cell to memory cell in an
increasing order of addresses, or in a decreasing order of
addresses, or in some arbitrary order of addresses. A sequence of
March elements is defined as a March test.
[0004] There exists a notation that describes the March test as
follows. A complete March test is delimited by a `{ . . . }`
parenthesis pair whereas a March element is delimited by a `( . . .
)` parenthesis pair. The March element can include a plurality of
following operations, with notations as indicated: Increase address
order, notated by . Decrease address order, notated by . (1) Move
through a sequence of addresses in an arbitrary manner, notated by
. (2) Write logical 0, write logical 1, read logical 0, read
logical 1, notated respectively by w0, w1, r0 and r1. As an example
of notation, the March test {(w0), (r0, w1), (r1,w0)} instructs to
write 0 to memory addresses in some arbitrary or pre-defined
sequence, then to each memory cell in the increasing order of
addresses read 0 and write 1 before going to the next memory cell,
and finally to each memory cell in the decreasing order of
addresses read 1 and write 0 before going to the next memory cell.
It is the convention that when symbols and appear in one formula,
the symbols represent address sequences that are exact reverses of
each other. It is also convention that .about.X represents logical
opposite of a value represented by Boolean variable X.
[0005] A typical apparatus for BIST includes a finite state machine
(BIST-FSM), an address generator, a data generator, and a
programmable test algorithm register (TAR). The TAR holds
information relating to the March elements, namely an addressing
direction, an addressing type, an addressing mode, an operation
code (that is, a sequence of read or write operations to be applied
to each memory cell) and a pattern type (that is, a code that
represents data to be written to the memory cells). The contents of
the TAR are referred to as test algorithm, and are generated using
a software tool that resides outside the BIST. The data generator
creates patterns of data to be written to the memory cells during
the test. Test data created by the data generator is referred to as
a background pattern (BP). The BP can be pre-defined or programmed.
The address generator creates signals along an address bus that
locate address of a memory cell to be tested and thereby makes the
memory cell ready for read or write.
[0006] Upon triggering of the BIST, the BIST-FSM of the apparatus
reads data from the TAR, and thereby selects the addressing type,
the addressing sequence, the code corresponding to the background
data pattern, and the sequence of read or write operations. Based
on the pattern type, the data generator generates the test data.
Based upon the addressing direction, the addressing sequence and
the addressing mode, the address generator selects the memory cell
to be tested. Based upon the operation code, the test data is
applied to the memory cell to be tested. The test algorithms, that
is, the contents of the TAR that specify the March tests, are
generated using a software tool that resides outside the BIST.
[0007] Hence, there is a need for a way to automatically generalize
March tests to detect additional kinds of faults.
SUMMARY
[0008] An example of a processor unit for testing an electronic
memory includes a built-in self-test (BIST) finite state machine
that coordinates a plurality of BIST functions of the processor
unit, an address generator in communication with the BIST finite
state machine to generate addresses of memory cells for the
testing, a data generator in communication with the BIST finite
state machine that generates data patterns to be applied to the
electronic memory, a test algorithm generation unit that generates
March tests to be applied to the electronic memory, a programmable
test algorithm register in communication with the test algorithm
generation unit that stores one or more March elements generated by
the test algorithm generator unit, and a test algorithm register
control unit, coupled between the BIST finite state machine and the
programmable test algorithm register, that enables the BIST finite
state machine to determine presence of the one or more March
elements stored in the programmable test algorithm register.
[0009] An example of a memory wrapper unit for testing an
electronic memory includes an operation decoder, a data comparator,
and the electronic memory. The operation decoder interprets an
operation code. The data comparator compares a test data output
with a data output from the electronic memory under test. The
electronic memory under test is in communication with the operation
decoder and the data comparator.
[0010] An example of a method of testing an electronic memory
includes constructing a fault periodic table having a plurality of
columns and a plurality of rows. Each of the plurality of columns
corresponds with a functionality of a test mechanism of a plurality
of test mechanisms, and each of the plurality of rows corresponds
with a fault family of a plurality of fault families. The method
also includes selecting a first March test sequence according to a
first fault family of the plurality of fault families and a first
test mechanism of the plurality of test mechanisms, and applying
the first March test sequence to the electronic memory. The method
further includes selecting a second March test sequence according
to a second fault family of the plurality of fault families and a
second test mechanism of the plurality of test mechanisms, and
applying the second March test sequence to the electronic memory.
Moreover, the method includes determining if the electronic memory
under test is one of acceptable and unacceptable based on results
of the first March test sequence and the second March test
sequence.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] In the accompanying figures, similar reference numerals may
refer to identical or functionally similar elements. These
reference numerals are used in the detailed description to
illustrate various embodiments and to explain various aspects and
advantages of the present disclosure.
[0012] FIGS. 1A-1C illustrate March test algorithms used for
testing an electronic memory, in accordance with one
embodiment;
[0013] FIG. 2 is a schematic representation of a process by which a
March test that detects one fault is generalized to other March
tests that detect other faults, in accordance with one
embodiment;
[0014] FIG. 3A is an illustrative example of a process by which a
March test is generalized, in accordance with one embodiment;
[0015] FIG. 3B is an exemplary illustration of an addressing order
and sequence of read and write operations associated with a
plurality of March tests, in accordance with one embodiment;
[0016] FIG. 4 is an exemplary illustration of a fault periodic
table, in accordance with one embodiment;
[0017] FIG. 5 is a block diagram of a built-in self-test processor
unit, in accordance with one embodiment;
[0018] FIG. 6 is a state diagram illustrating a plurality of states
assumed by a built-in self-test processor unit, in accordance with
one embodiment;
[0019] FIG. 7A illustrates a programmable test algorithm register
in a built-in self-test processor unit, in accordance with one
embodiment;
[0020] FIG. 7B illustrates fields of a programmable test algorithm
register, in accordance with one embodiment;
[0021] FIG. 8 is a block diagram of a memory wrapper unit, in
accordance with one embodiment;
[0022] FIG. 9 is an exemplary illustration of functioning of an
operation decoder in a memory wrapper unit, in accordance with one
embodiment; and
[0023] FIG. 10 is a flow diagram illustrating a method of testing
an electronic memory, in accordance with one embodiment.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0024] In the following detailed description of the preferred
embodiments, reference is made to the accompanying drawings which
form a part hereof, and in which are shown by way of illustration
specific embodiments in which the invention may be practiced. It is
to be understood that other embodiments may be utilized and
structural changes may be made without departing from the scope of
the present invention.
[0025] The present disclosure determines that properties of faults
are periodic functions of lengths of a sequence of test operations
that identifies a fault. Such a determination provides two devices,
for example a test algorithm template and a fault periodic table.
The present disclosure at first describes the test algorithm
template, which is defined as a technique to generalize a March
test in order to expand applicability of the March test to a larger
set of faults. Application of the test algorithm template also
causes the faults to naturally cluster into sets, referred to as
fault families. A fault family is characterized by a length of a
sequence of test operations. The present disclosure also describes
the fault families and the fault periodic table. Having described
the devices of test algorithm template and fault periodic table.
The present disclosure further describes a built-in self-test
(BIST) processor unit, that arranges, utilizes and co-ordinates the
devices in a manner that achieves fault detection in an efficient,
productive and exhaustive manner. The present disclosure also
describes a memory wrapper unit that is required in order for fault
testing when conducted by the BIST processor unit.
[0026] The term symmetric faults, as used in the disclosure, is to
be interpreted as a pair of faults that are identical in every
respect except for logical states of memory cells at fault, which
are of opposite polarity. For example, stuck-at-0 and stuck-at-1
faults form a symmetric pair. A transition fault 1, in which a
write-1 operation fails on a memory cell that includes logical 0 is
symmetric with a transition fault 0, in which a write-0 operation
fails on a memory cell that includes logical 1.
[0027] The term symmetric March test, as used in the disclosure,
should be interpreted as the March test that executes a similar
March element with one or more of different addressing directions,
data polarities, and data background patterns. For example, the
March test (W0,R0); (W1,R1) is symmetric, since element (Wx, Rx) is
repeated with two different polarities of data x.
[0028] The term test mechanism, as used in the disclosure, should
be interpreted as a property of a test that characterizes the test.
Examples of the property include, but is not limited to, a
background pattern (one of checkerboard, solid-0, and solid-1), an
addressing mode (FC: fast columns, that is, column-by-column
addressing of memory or FR: fast rows, that is, row-by-row
addressing of memory), an addressing type (binary, in which
addresses are changed in the order 0,1, . . . , N-1, or ping-pong,
in which addresses are changed in the order 0, N-1,2, N-2, . . . ),
and operation concurrency (that is, two or more operations within a
test sequence made simultaneously in time or sequentially).
[0029] In subjecting an electronic memory to tests, the following
rules should be observed: (1) The symmetric March test is used so
as to detect a fault that can have a symmetric counterpart. As an
example, the symmetric March test (W0,R0); (W1,R1) is used to
detect a stuck-at fault (SAF), such that both symmetric varieties
of the SAF, namely the SAF0 and the SAF1 are detected. (2) The
March test for detecting a new fault can be constructed or
generalized from an existing March test. In one example, the March
test (W0,R0); (W1,R1) is generalized by adding one or more write
operations to each element, in order to obtain (W0,W0,R0);
(W1,W1,R1). (3) For thorough testing, the March test is normally
applied with different test mechanisms. For example, if the March
test (W0,R0); (W1,R1) is executed under the fast-column (FC)
mechanism, then it is also normal to execute the March test under
the fast-row (FR) mechanism.
[0030] The term coupling fault, as used in the disclosure, should
be interpreted as a fault that involves a pair of memory cells, and
in which an operation on a first memory cell of the pair of memory
cells can cause a fault in a second memory cell of the pair of
memory cells. As an example, a write operation in the first, or
coupling, memory cell can cause the second, or coupled, memory cell
to flip in value.
Test Algorithm Template
[0031] The test algorithm template is a method disclosed herein to
generalize March tests, in accordance with which various
embodiments can be implemented. The test algorithm template starts
with a sequence of test operations TO, and creates a March test,
notated as TA, that has the following advantageous properties: (1)
The faults detected by TO are also detected by TA. (2) TA is the
symmetric March test. (3) If TA is capable of detecting a fault F1
that is one of a pair of symmetric faults (F1, F2) then TA is also
capable of detecting a fault F2. (4) If TA is capable of detecting
the coupling fault between two memory cells such that address of
the coupled cell is greater than address of the coupling cell, then
TA is also capable of detecting the coupling fault between two
memory cells such that the address of the coupled cell is less than
the address of the coupled cell.
[0032] In order to create the March test TA from the sequence of
test operations TO, the test algorithm template needs a faulty
value of a faulty memory cell, notated as A1, and initial value of
the faulty memory cell, notated as A2. As such therefore the March
test TA is a function of A1, A2 and TO, and therefore the test
algorithm template is notated as TA(A1,A2,TO). It will be clear to
one of ordinary skill in the art that A1 is a logical opposite of a
final value generated by the sequence of test operations TO. It
will also be clear to one of ordinary skill in the art that a test
notated as .about.TO represents a similar sequence of test
operations as TO, except that data values being operated upon by
.about.TO are opposite in polarity to those being operated upon by
TO. For example if the TO is write-1 (W1) then the .about.TO will
be write-0 (W0). Within this disclosure, the sequence of test
operations .about.TO is referred to as the logical opposite of the
sequence of test operations TO.
[0033] Different procedures by which the test algorithm template
TA(A1,A2,TO) creates the March test TA from the sequence of test
operations TO is illustrated in FIG. 1A, FIG. 1B, and FIG. 1C
respectively.
[0034] FIG. 1A illustrates a plurality of cases when A1 equals A2
and a first operation of TO is a read-operation. Examples of the
plurality of cases include, but are not limited to, a first case, a
second case, a third case, and a fourth case. In the first case,
the test algorithm template comprises the following steps: [0035]
(1) write A1 along an arbitrary order of addresses, [0036] (2)
execute the sequence of test operations TO along the increasing
order of the addresses, [0037] (3) execute the sequence of test
operations .about.TO along the increasing order of the addresses,
[0038] (4) execute the sequence of test operations TO along a
decreasing order of the addresses, [0039] (5) execute the sequence
of test operations .about.TO along the decreasing order of the
addresses, and [0040] (6) read A1 along the arbitrary order of the
addresses.
[0041] In the second case, the test algorithm template comprises
the following steps: [0042] (1) write A1 along the arbitrary order
of addresses, [0043] (2) execute the sequence of test operations TO
along the decreasing order of the addresses, [0044] (3) execute the
sequence of test operations .about.TO along the decreasing order of
the addresses, [0045] (4) execute the sequence of test operations
TO along the increasing order of the addresses, [0046] (5) execute
the sequence of test operations .about.TO along the increasing
order of the addresses, and [0047] (6) read A1 along the arbitrary
order of the addresses.
[0048] In the third case, the test algorithm template comprises the
following steps: [0049] (1) write A1 along the arbitrary of
addresses, [0050] (2) execute the sequence of test operations TO
along the increasing order of the addresses, [0051] (3) execute the
sequence of test operations .about.TO along the decreasing order of
the addresses, [0052] (4) execute the sequence of test operations
TO along the decreasing order of the addresses, [0053] (5) execute
the sequence of test operations .about.TO along the increasing
order of the addresses, and [0054] (6) read A1 along the arbitrary
order of the addresses.
[0055] In the fourth case, the test algorithm template comprises
the following steps: [0056] (1) write A1 along the arbitrary order
of addresses, [0057] (2) execute the sequence of test operations TO
along the decreasing order of the addresses, [0058] (3) execute the
sequence of test operations .about.TO along the increasing order of
the addresses, [0059] (4) execute the sequence of test operations
TO along the increasing order of the addresses, [0060] (5) execute
the sequence of test operations .about.TO along the decreasing
order of the addresses, and [0061] (6) read A1 along the arbitrary
order of the addresses.
[0062] FIG. 1B illustrates a plurality of cases when A1 equals A2
and the first operation of TO is not a read-operation. Examples of
the plurality of cases include, but are not limited to, a first
case, a second case, a third case, and a fourth case. In the first
case, the test algorithm template comprises the following steps:
[0063] (1) write A1 along the arbitrary order of the addresses,
[0064] (2) read A1, then execute the sequence of test operations TO
along the increasing order of the addresses, [0065] (3) read
.about.A1, then execute the sequence of test operations .about.TO
along the increasing order of the addresses, [0066] (4) read A1,
then execute the sequence of test operations TO along the
decreasing order of the addresses, [0067] (5) read .about.A1, then
execute the sequence of test operations .about.TO along the
decreasing order of the addresses, and [0068] (6) read A1 along the
arbitrary order of the addresses.
[0069] In the second case, the test algorithm template comprises
the following steps: [0070] (1) write A1 along the increasing order
of the addresses, [0071] (2) read A1, then execute the sequence of
test operations TO along the decreasing order of the addresses,
[0072] (3) read .about.A1, then execute the sequence of test
operations .about.TO along the decreasing order of the addresses,
[0073] (4) read A1, then execute the sequence of test operations TO
along the increasing order of the addresses, [0074] (5) read
.about.A1, then execute the sequence of test operations .about.TO
along the increasing order of the addresses, and [0075] (6) read A1
along the arbitrary order of the addresses.
[0076] In the third case, the test algorithm template comprises the
following steps: [0077] (1) write A1 along the increasing order of
the addresses, [0078] (2) read A1, then execute the sequence of
test operations TO along the increasing order of the addresses,
[0079] (3) read .about.A1, then execute the sequence of test
operations .about.TO along the decreasing order of the addresses,
[0080] (4) read A1, then execute the sequence of test operations TO
along the decreasing order of the addresses, [0081] (5) read
.about.A1, then execute the sequence of test operations .about.TO
along the increasing order of the addresses, and [0082] (6) read A1
along the arbitrary order of the addresses.
[0083] In the fourth case, the test algorithm template comprises
the following steps: [0084] (1) write A1 along the increasing order
of the addresses, [0085] (2) read A1, then execute the sequence of
test operations TO along the decreasing order of the addresses,
[0086] (3) read .about.A1, then execute the sequence of test
operations .about.TO along the increasing order of the addresses,
[0087] (4) read A1, then execute the sequence of test operations TO
along the increasing order of the addresses, [0088] (5) read
.about.A1, then execute the sequence of test operations .about.TO
along the decreasing order of the addresses, and [0089] (6) read A1
along the arbitrary order of the addresses.
[0090] FIG. 1C illustrates a plurality of cases when A1 does not
equal A2. Examples of the plurality of cases include, but are not
limited to, a first case, a second case, a third case, and a fourth
case. In the first case, the test algorithm template comprises the
following steps: [0091] (1) write A1 along the arbitrary order of
the addresses, [0092] (2) read A1, then write A2, then execute the
sequence of test operations TO along the increasing order of the
addresses, [0093] (3) read .about.A1, then write .about.A2, then
execute the sequence of test operations .about.TO along the
increasing order of the addresses, [0094] (4) read A1, then write
A2, then execute the sequence of test operations TO along the
decreasing order of the addresses, [0095] (5) read .about.A1, then
write .about.A2, then execute the sequence of test operations
.about.TO along the decreasing order of the addresses, and [0096]
(6) read A1 along the arbitrary order of the addresses.
[0097] In the second case, the test algorithm template comprises
the following steps: [0098] (1) write A1 along the arbitrary order
of the addresses, [0099] (2) read A1, then write A2, then execute
the sequence of test operations TO along the decreasing order of
the addresses, [0100] (3) read .about.A1, then write .about.A2,
then execute the sequence of test operations .about.TO along the
decreasing order of the addresses, [0101] (4) read A1, then write
A2, then execute the sequence of test operations TO along the
increasing order of the addresses, [0102] (5) read .about.A1, then
write .about.A2, then execute the sequence of test operations
.about.TO along the increasing order of the addresses, and [0103]
(6) read A1 along the arbitrary order of the addresses.
[0104] In the third case, the test algorithm template comprises the
following steps: [0105] (1) write A1 along the arbitrary order of
the addresses, [0106] (2) read A1, then write A2, then execute the
sequence of test operations TO along the increasing order of the
addresses, [0107] (3) read .about.A1, then write .about.A2, then
execute the sequence of test operations .about.TO along the
decreasing order of the addresses, [0108] (4) read A1, then write
A2, then execute the sequence of test operations TO along the
decreasing order of the addresses, [0109] (5) read .about.A1, then
write .about.A2, then execute the sequence of test operations
.about.TO along the increasing order of the addresses, and [0110]
(6) read A1 along the arbitrary order of the addresses.
[0111] In the fourth case, the test algorithm template comprises
the following steps: [0112] (1) write A1 along the arbitrary order
of the addresses, [0113] (2) read A1, then write A2, then execute
the sequence of test operations TO along the decreasing order of
the addresses, [0114] (3) read .about.A1, then write .about.A2,
then execute the sequence of test operations .about.TO along the
increasing order of the addresses, [0115] (4) read A1, then write
A2, then execute the sequence of test operations TO along the
increasing order of the addresses, [0116] (5) read .about.A1, then
write .about.A2, then execute the sequence of test operations
.about.TO along the decreasing order of the addresses, and [0117]
(6) read A1 along the arbitrary order of the addresses.
Examples of Test Generalization and Creation Using the Test
Algorithm Template
[0118] As an illustrative example, consider a case when the
sequence of test operations TO comprises no operations, that is, TO
equals an empty set O. Since TO performs no operations, and yet a
fault is manifested, A1 does not equal A2. As described in above
test algorithm templates, an applicable case is the third case,
illustrated in FIG. 1C. Applying the steps of the third case, i.e.,
FIG. 1C, the March test TA, now designated TA.sub.0, is generated
as follows:
TA.sub.0=TA(0,1,O)=(W0); (R0,W1); (R1,W0); (R0,W1); (R1,W0);
(R0).
[0119] It will be clear to one of ordinary skill in the art that
test TA.sub.0 generated in the above example detects state faults,
examples of which are stuck-at faults and state-coupling
faults.
[0120] In another example of the test generalization and creation
using the method of the test algorithm template, consider the
sequence of test operations TO to equal an operation {0W1W1R1}. The
first operation 0W1 of the sequence of test operations TO detects a
transition fault, which is defined as a fault that causes the
memory cell to fail to respond to a write-1 when initial value of
the memory cell is 0. In such a case, the initial value of the
memory cell is A2=0. A1, which is opposite of the final value of
the memory cell at the termination of TO, is A1=0. Therefore, A1
equals A2 and the first operation of TO is not a read-operation.
Therefore, the second case as illustrated in FIG. 1B, applies and
the March test TA, now designated TA.sub.1, is generated as
follows:
TA 1 = TA ( 0 , 0 , { W 1 , W 1 , R 1 } ) = ( W 0 ) ; ( R 0 , W 1 ,
W 1 , R 1 ) ; ( R 1 , W 0 , W 0 , R 0 ) ; ( R 0 , W 1 , W 1 , R 1 )
; ( R 1 , W 0 , W 0 , R 0 ) ; ( R 0 ) ##EQU00001##
[0121] It will be clear to one of ordinary skill in the art that
test TA.sub.1 generated in the above example is a smallest length
(minimal) March test that detects the static faults.
Fault Families
[0122] The fault family is a classification of faults based upon
the length of the sequence of test operations, in accordance with
which various embodiments can be implemented. A method of
classifying the faults into the fault families is now disclosed as
follows. A fault is defined to belong to a fault family F.sub.k if
the sequence of test operations that identifies the fault has k
operations. Since state faults such as stuck-at faults and
state-coupling faults need no operations to be identified, it is
clear that the state faults belong to F.sub.0. It is also clear
from properties inherent to the test algorithm template and
described above that the March test TA.sub.0 is capable of
detecting the state faults that belong to F.sub.0. Similarly, as
TA.sub.1 is generated out of the sequence of test operations TO
that can detect one type of transition fault, the March test
TA.sub.1 is capable of detecting transition faults that belong to
F.sub.1.
[0123] Other Methods of March Test Generalization are Possible:
[0124] The disclosure can provide other methods of generalization
of March tests, for example a method 200 illustrated in FIG. 2. In
the method 200, a March test M.sub.i that makes manifest a fault
family F.sub.i, both illustrated in a block 202, is subjected to a
transformation T.sub.ik 210, in order to generate a new March test
M.sub.k that makes manifest a fault family F.sub.k, illustrated in
a block 206. Similarly, the March test in the block 202 is
transformed via transformation T.sub.ij 212 in order to get the
March test M.sub.j and associated fault family F.sub.j in block
204. Furthermore, it is possible for two March tests to be
individually or jointly transformed in order to produce a third
March test, as for example the March tests in blocks 204 and 206
that are respectively subject to transformations 214 and 216 in
order to generate the March test Mt with associated fault family
F.sub.t in block 208.
[0125] An illustrative example of the method 200 is depicted in
FIG. 3A and FIG. 3B. Three transformations are illustrated in FIG.
3A: (1) Transformation TR: add read, which adds a read operation to
every March element of an input March test save first and last
elements; (2) Transformation TW: add write, which adds a write
operation to every March element of the input March test save the
first and last elements; and (3) Transformation TWR: add write, add
read, which adds first a write operation then a read operation to
every March element of the input March test save the first and last
elements. In block 302 of FIG. 3A is a March test referred to as
March test C-, which can be recognized by one of ordinary skill in
the art as formula 301 in FIG. 3B. To the March test C- of the
block 302 is applied transformation 310, which is a transformation
of type TR: add read. Upon applying the transformation, the March
test is then represented by formula 305 in FIG. 3B, which will be
recognized by one of ordinary skill in the art as March test M1.
The March test M1 is illustrated in block 306. To the March Test M1
of the block 306 is applied transformation 316, which is a
transformation of type TW: add write, and the March test is then
represented by formula 307 of FIG. 3B, which can be recognized by
one of ordinary skill in the art as March Test MSS, also
illustrated as block 308 in FIG. 3A. As a further illustration of
the process by which a test can be generalized, the March Test C-
of the block 302 is applied transformation 312, which is of type
TW: add write. Upon applying the transformation 312, the March test
is then represented by formula 303 of FIG. 3B, which will be
recognized by one of ordinary skill in the art as March test M2,
also represented in block 304 of FIG. 3A. Applying transformation
314, of type TR: add read to the March test M2 in the block 304,
the March test MSS illustrated as the block 308 is then represented
by the formula 307 of FIG. 3B. Alternately, one can generate the
March test MSS of the block 308 directly from the March test C- by
means of the transformation 318, which is of type TWR: add write,
add read.
[0126] It will be clear to one of ordinary skill in the art that
one or more methods of test generalization can be used in order to
expand applicability of a given test such that a larger family of
faults is detected. The present disclosure can thus invoke method
of test generalization in various embodiments including, but not
limited to, the methods described above.
Fault Periodic Table
[0127] The fault periodic table is an arrangement of faults in a
tabular form indexed by associated fault families and by the test
mechanism used to detect the faults, in accordance with which
various embodiments can be implemented. Apart from systematizing
the faults in a way that allows easier recall of related
properties, the fault periodic table enables prediction of the
properties of unknown faults, and thereby enabling generation of
the March tests that make apparent the unknown faults.
[0128] Principle of the fault periodic table is that the properties
of the faults are periodic functions of the lengths of the sequence
of test operations that identifies the fault. In arranging the
faults row-wise by fault-family and column-wise by test mechanism,
the faults with similar properties cluster, and different such
clusters have dissimilar properties. Choice of nomenclature makes
it clear that inspiration for the fault periodic table is
Mendeleyev's Periodic Table of chemical elements.
[0129] A fault periodic table 400 and a method of constructing the
fault periodic table 400 are illustrated in FIG. 4. A March test
TA.sub.0 that makes manifest the faults belonging to a fault family
F.sub.0 is associated with a plurality of test mechanisms that
include, but are not limited to, TM.sub.0, TM.sub.1, and TM.sub.2.
Such associations, that is, (TA.sub.0,TM.sub.0),
(TA.sub.0,TM.sub.1), and (TA.sub.0,TM.sub.2), are arranged in a row
402 that is indexed by the fault family F.sub.0. Similarly, a March
test TA.sub.1 that makes manifest the faults belonging to a fault
family F.sub.1 is associated with a plurality of test mechanisms
that include, but are not limited to, TM.sub.0,TM.sub.1, and
TM.sub.2. Such associations, that is, (TA.sub.1,TM.sub.0),
(TA.sub.1,TM.sub.1), and (TA.sub.1,TM.sub.2) are arranged in a row
404 indexed by the fault family F.sub.1. Row 406 that is indexed by
the fault family F.sub.2 is constructed, and the fault periodic
table 400 can be extended along the row-dimension as far as
desired. It is evident that row-wise arrangement described is
consequent to column-wise arrangement of the faults, each column
headed by a test mechanism, for example TM.sub.0 (column 401),
TM.sub.1 (column 403), TM.sub.2 (column 405) and so on. The
construction of the fault periodic table 400 can be described
column-first, in contrast but equivalent to row-first description
adopted herein. At an intersection of a row and a column lie
elements of the fault periodic table 400, for example element 407
which is (TA.sub.0,TM.sub.0) and is at the intersection of the row
402 and the column 401, or element 408 which is (TA.sub.1,TM.sub.1)
and is at the intersection of the row 404 and the column 403.
[0130] Predictive power of the fault periodic table 400 arises from
an observation that the faults that are made manifest by an element
along a first row of the table exhibit properties that are similar
to the faults that are made manifest by elements below the element.
That is, the faults that are manifest by the elements along a
column of the fault periodic table 400 have similar properties. In
an exemplary application of the predictive power, if an element of
the fault periodic table 400 detects a fault, then another element
below the element can also detect a similar but different fault. In
another application of the predictive power, if first several
elements of a column pass then it can be an indication that no
further faults are found by investigating later complex elements
along the column. In this way, fault testing can proceed along
paths as identified by the fault periodic table 400 resulting in
following benefits: (1) Efficiency: Tests that are likely to pass
are less likely to be conducted (2) Productiveness: Tests that are
likely to fail are likely to be conducted (3) Exhaustiveness: A
fault detected by an element in upper sections of a column can
direct further fault testing to be conducted along paths that
uncover obscure or rarely manifested faults.
[0131] It will be clear to one of ordinary skill in the art that
fault coverage can be extended by considering new fault families or
adding new test mechanisms, that is, by moving horizontally along
the fault periodic table or by adding new columns to the fault
periodic table. The method of adding new test mechanisms in order
to extend fault coverage is not mutually exclusive with, and is in
addition to, other methods of extending fault coverage disclosed
herein, for example the test algorithm template, or the method 200
described in FIG. 2, and exemplified in FIG. 3A and FIG. 3B.
[0132] The present disclosure can apply the predictive power of the
fault periodic table in various embodiments in order to achieve
automated extension of the fault coverage in an efficient,
productive and exhaustive manner.
BIST Processor Unit Capable of Automated Test Generation and
Extension
[0133] FIG. 5 illustrates the architecture of a built-in self-test
(BIST) processor unit 500 that is capable of automated generation
and execution of March tests, thereby operating over and above a
traditional mode of executing the March tests that have been
externally created. Within the BIST processor unit 500 is a BIST
finite state machine (BIST-FSM) 502 that co-ordinates actions of
other units. The BIST-FSM 502 executes its duties by means of an
unending sequence of traversals through various states, described
in detail in conjunction with FIG. 6. A test algorithm generation
unit 508 is responsible for generation of the March tests. The test
algorithm generation unit 508 includes a fault periodic table 504
and a test algorithm template unit 506. Upon generation of a March
test, the March test is loaded into a programmable test algorithm
register 512. The programmable test algorithm register 512 is also
capable of being fed with the March tests by means of external
generation and loading of the March tests. Regardless of whether
the March test is pre-defined, loaded after the external
generation, or generated within the test algorithm generation unit
508 of the BIST processor unit 500, steps for execution of a March
test sequence remain unchanged. The programmable test algorithm
register 512, including multiple fields, is explained in detail in
conjunction with FIG. 7A and FIG. 7B. A field of the programmable
test algorithm register 512 that needs to be selected in order for
a test to run depends on the state of the BIST-FSM 502, and
depending on a selected field, a certain set of addresses,
directions and operations are directed towards the electronic
memory under test. Therefore, it is necessary to have an interface
between the programmable test algorithm register 512 and the
BIST-FSM 502. Such an interface function is performed by a test
algorithm register control unit 510, which transmits information
between the BIST-FSM 502 and the programmable test algorithm
register 512.
[0134] The BIST-FSM 502 thus co-ordinates activities of the test
algorithm generation unit 508 and the programmable test algorithm
register 512 in order to make available the March test. The
BIST-FSM 502 then executes the March test. The March test includes
a sequence of operations and test mechanisms and further includes
addressing direction (that is or ), an addressing type (that is,
the addressing sequence 0,1, . . . , N-1 or a sequence 0, N-1,1,
N-2, . . . or some other addressing sequence), an addressing mode
(for example, fast-column or fast-row), an operation code (for
example, read-from-memory, write-to-memory, enable-write, and so
on) and data pattern (for example, solid-0, checkerboard, and so
on) to be applied to the electronic memory. The BIST-FSM 502 then
sends address-related information, that is, the addressing
direction, the addressing type and the addressing mode, to the
address generator 514. The address generator 514 uses information
received from the BIST-FSM 502 in order to generate address of the
memory cell that is to be tested. The BIST-FSM 502 sends data
related information, that is, pattern type to a data generator 516.
The data generator 516 interprets the pattern type in order to
excite one of a predefined background pattern register 518, or a
programmable background pattern register 520, in order to generate
the data pattern to be applied to the address selected by the
address generator 514. The predefined background pattern register
518 includes a set of patterns that are pre-loaded. The
programmable background pattern register 520 enables new background
data patterns (arising perhaps due to new test mechanisms) to be
loaded. Examples of the background data patterns include, but are
not limited to, solid-0 which entails writing logical 0 to memory
cells under test; solid-1 which entails writing logical 1 to the
memory cells under test, and checkerboard which entails writing the
pattern 010101 . . . on even rows and the pattern 101010 . . . on
odd rows. A multiplexer 522 allows selection of test data output
from one of the programmable background pattern register 520 and
the predefined background pattern register 518. A combination of
test address as computed by the address generator 514, the data
value as generated by the data generator 516 and the operation code
as generated by the BIST-FSM 502 are transmitted via a test bus to
an electronic memory cell under test, which in turn performs in a
manner described in detail in conjunction with FIG. 8.
[0135] State Diagram of the BIST-FSM:
[0136] FIG. 6 is a state diagram 600 illustrating the states that
the BIST-FSM 502 traverses in performing associated duties. The
BIST-FSM 502 can transition from one state to another in response
to an input signal, and in thus transitioning, emits an output
signal. In FIG. 6, input signals, for example signals 601, 603,
605, 607 are in italicized font and output signals, for example
signals 609, 611, 613 are in regular font. A quiescent state of the
BIST-FSM 502 is an idle state 602, in which the BIST-FSM 502 waits
for a signal START_BIST 601, in order to start a testing process.
Typically, the signal START_BIST 601 is supplied by a module that
hosts the BIST processor unit 500. The BIST-FSM 502 then
transitions to a reset state 604, in which registers within the
BIST processor unit 500 are reset. Following completion of the
reset state 604, the BIST-FSM 502 transitions to a check state 606,
in which the BIST-FSM 502 reads (via the test algorithm register
control unit 510) contents of the programmable test algorithm
register (PTAR) 512 and thereby configures the address generator
514 and the data generator 516. If, upon reading the contents of
the programmable test algorithm register 512, a NumofOps field is
found to be equal to 6, then it is equivalent to issuing to the
BIST-FSM 502 a command GOTO_CMD 603, which causes the BIST-FSM 502
to transition to a back state 608. A task performed by the BIST-FSM
502 in the back state 608 is to effect a shift of the programmable
test algorithm register 512 to a marked test element. Purpose of
the shift is to repeat the test indicated by shifted-to test
element under a different test mechanism in order to achieve
complete test coverage. Once tasks of the back state 608 are
completed, the BIST-FSM 502 transitions back to the check state
606, and in thus transitioning issues a signal BACK_DONE 609. At
the check state 606, if the signal START_BIST 605 is found to be
active, then the BIST-FSM 502 transitions to an exec state 612,
which is an executive state of the BIST-FSM 502. A principal task
of the exec state 612 is to execute the test indicated by the test
element read in the check state 606. As such the task would entail
exercising the address generator 514 and the data generator 516 and
related parts in order to apply data patterns and operations to
addressed memory. When testing task of the exec state 612 is
completed, the BIST-FSM 502 checks if there are more tests to be
run, by checking for presence of an active end field in the test
element. If the end field is not active then there are more tests
to be run, and the BIST-FSM 502 transitions to a shift state 610,
and in thus transitioning issues signal ADDR_DONE 611. In the shift
state 610 the BIST-FSM 502 moves to a next test held in the
programmable test algorithm register 512. However, if the end field
is active then a command END_CMD 607 is issued to the BIST-FSM 502
which causes the BIST-FSM 502 to wind down testing by moving
through a final set of states. The final set of states and related
tasks are as follows: a roll state 614, in which the programmable
test algorithm register 512 is shifted to starting position and a
done state 616, which is a type of quiescent state in which the
BIST-FSM 502 waits for the signal START_BIST 601 to de-assert. In
transitioning from the roll state 614 to the done state 616, the
BIST_FSM 502 emits the output signal ROLL_DONE 613. Once the signal
START_BIST 601 is de-asserted, the BIST_FSM 502 moves from the done
state 616 to its initial quiescent state, the idle state 602.
[0137] Programmable Test Algorithm Register:
[0138] FIG. 7A and FIG. 7B illustrate the contents and organization
of the programmable test algorithm register 512, in accordance with
one embodiment. FIG. 7A illustrates that the programmable test
algorithm register 512 can hold several March elements, for example
a March element 710, and a March element 720. Each March element,
for example the March element 710 has at least two fields, a March
element descriptor field 702, and one or more instances of March
operation descriptors field 704. The March element descriptor field
702 has at least six sub-fields as described in FIG. 7B: (1) a
marker sub-field represented by bit 9, which if set to 1, saves
position of a current March element for further TAR rollbacks; (2)
the pattern type represented by bits 6-8, which indicates the type
of data background pattern to be written to the electronic memory
under test; (3) the addressing mode sub-field (AddrMode)
represented by bit 5, which indicates if a rectangular memory array
under test needs to be addressed in a fast column manner or in a
fast row manner; (4) an addressing type sub-field (AddrType)
represented by bit 4, which indicates if the addressing sequence
should be in a binary order 0,1, . . . , N-1, or in a ping-pong
sequence, that is in the order 0, N-1,1, N-2, . . . , or some other
order, where N is number of addresses; (5) the addressing direction
sub-field (AddrDir) represented by bit 3, which indicates the
direction ( or ) of the addressing sequence; and (6) number of
operations sub-field (NumOfOps) represented by bits 0-2, which
indicates number of operations within the current March element if
NumOfOps.ltoreq.5 else special commands are applied: NumOfOps=i,
0.ltoreq.i.ltoreq.5: (i+1) operations; NumOfOps=6: goto command;
and NumOfOps=7: end command. The sub-fields of the March element
descriptor 702 are read by the BIST-FSM 502 and transmitted to the
address generator 514 and the data generator 516 at time of
execution of the March element. The March operation descriptors
field 704, as described in FIG. 7C, determines type of each
individual March operation and includes an inverse pattern
sub-field (PattInv) and opcode sub-fields. PattInv, represented by
bit 4, determines polarity of the data background pattern for a
direct or inverse pattern. OpCode, represented by bits 0-3,
determines type of operation. In some embodiments, the March
operation descriptors field 704 represent the sequence of
operations, for example write-enable, read-enable, or
memory-enable, that are to be performed in each memory cell
addressed by the address generator 514.
[0139] When applying the March element descriptor 702 with a goto
command, some fields of the March element descriptor 702 change in
interpretation as given below: [0140] If AddrDir is equal to 1 then
the addressing order for a repeated set of March elements is be
inversed, that is if a March element is originally (R0, W1, R1),
when repeating, the March element becomes (R0, W1, R1). Otherwise,
if AddrDir is equal to 0 then a similar addressing order for the
repeated set of March elements is used; [0141] If AddrType is equal
to 1 then the polarity of background data for the repeated set of
March elements is inversed, that is if the March element is
originally (R0, W1, R1), when repeating, the March element becomes
(R1, W0, R0). Otherwise, if AddrType is equal to 0 similar polarity
of the background data for the repeated set of March elements is
used; [0142] If AddrMode is equal to 1 then an opposite addressing
mode for the repeated set of March elements is inversed, that is if
the March element originally used fast column addressing mode, when
repeating, the March element uses fast row addressing mode.
Otherwise, if AddrMode is equal to 0 similar addressing mode for
the repeated set of March elements is used; [0143] If pattern type
is equal to the pattern type of a repeated March element then
similar data background pattern is used for the repeated set of
March elements, otherwise if the pattern type differs from the
pattern type of the repeated March element, then pattern type from
the March element descriptor is used with the goto command.
Memory Wrapper Unit
[0144] FIG. 8 illustrates the memory wrapper unit 800, at the
electronic memory under test 802, in accordance with one
embodiment. Function of the memory wrapper unit 800 is to accept
the operation-code, the memory addresses and the data patterns as
generated by the BIST processor unit 500. The memory addresses and
the data patterns are further provided to the electronic memory
under test 802. The memory wrapper unit 800 includes an operation
decoder 810 that serves to interpret the operation code sent by the
BIST processor unit 500. The operation decoder 810 further includes
a predefined operations register 804 and a programmable operations
register 806. The predefined operations register 804 serves to
interpret operation codes that have been hard-wired. The
programmable operations register 806 allows flexibility of defining
new operations that can be needed by newly generated March tests.
Such programmable decoding of the operation codes is reflected in a
table 900 of FIG. 9, which illustrates mapping between the
operations code and actions performed on a memory cell, and which
explicitly reserves space for programmable operation codes. The
operation code originating from the BIST processor unit 500 serves
to select one of the outputs of either the predefined operations
register 804 or the programmable operations register 806 via a
multiplexer 812. The operation code at output of the multiplexer
812 is used to index into the table 900 illustrated in FIG. 9, and
thereby a plurality of memory control inputs (that is, one or more
of memory-enable, write-enable, and read-enable) are sent to the
electronic memory under test 802. The table 900 also includes
predefined operations 902 and extra space for programmable
operations 904. The memory wrapper unit 800 also comprises a data
comparator 808 which serves to compare the data output from the
electronic memory under test 802 with an incoming data pattern from
the BIST processor unit 500 so as to accept or reject the
electronic memory under test 802. In some embodiments, such a
decision is fed back to the BIST processor unit 500 to generate
other March tests.
[0145] FIG. 10 is a flow diagram illustrating a method of testing
an electronic memory, in accordance with one embodiment.
[0146] At step 1005, a fault periodic table having a plurality of
columns and a plurality of rows is constructed. Each of the columns
corresponds with a functionality of a test mechanism of a plurality
of test mechanisms, and each of the rows corresponds with a fault
family of a plurality of fault families. The test mechanism can
include one or more of a background pattern, an addressing mode, an
addressing type, and concurrency of operations.
[0147] At step 1010, a first March test sequence is selected
according to a first fault family and a first test mechanism. The
first fault family belongs to the fault families, and the first
test mechanism belongs to the test mechanisms.
[0148] In some embodiments, selection of the first March test
sequence includes selecting test data from a plurality of
predefined background patterns and a plurality of programmable
background patterns. In other embodiments, selection of the first
March test sequence includes selecting a memory control signal from
a plurality of predefined operations and a plurality of
programmable operations.
[0149] At step 1015, the first March test sequence is applied to
the electronic memory.
[0150] At step 1020, a second March test sequence is selected
according to a second fault family of the fault families and a
second test mechanism of the test mechanisms.
[0151] At step 1025, the second March test sequence is applied to
the electronic memory.
[0152] The electronic memory is hence tested for each of the fault
families as described in steps 1010, 1015, 1020, and 1025.
[0153] At step 1030, the electronic memory under test is determined
to be one of acceptable and unacceptable based on results of the
first March test sequence and the second March test sequence.
[0154] In some embodiments, the first March test sequence and the
second March test sequence each represent a March test, for example
the March test TA, created from a sequence of test operations, for
example the sequence of test operations TO, and is explained in
conjunction with FIG. 1A, FIG. 1B, and FIG. 1C respectively.
[0155] The electronic memory is unacceptable based on failure of
one or more of the first March test sequence and the second March
test sequence. The electronic memory is hence discarded.
[0156] In some embodiments, the results are used to extend the
fault periodic table by creating a new fault family or by creating
another test mechanism.
[0157] It will be clear to one of ordinary skill in the art that
the flexibility provided by the present invention in terms of
programmability of operation-codes, background patterns, test
algorithms, allows customization of the BIST processor unit and
also enables a user to find a better and optimal trade-off between
functionality and area occupied on silicon. Auto-generalization
capability of the present disclosure further can enhance testing of
the electronic memory by enabling tests to be conducted
efficiently, productively and exhaustively.
[0158] The foregoing description sets forth numerous specific
details to convey a thorough understanding of embodiments of the
disclosure. However, it will be apparent to one skilled in the art
that embodiments of the disclosure may be practiced without these
specific details. Some well-known features are not described in
detail in order to avoid obscuring the disclosure. Other variations
and embodiments are possible in light of above teachings, and it is
thus intended that the scope of disclosure not be limited by this
Detailed Description, but only by the Claims.
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