U.S. patent application number 12/961107 was filed with the patent office on 2012-08-16 for semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings.
This patent application is currently assigned to STATS CHIPPAC, LTD.. Invention is credited to Rajendra D. Pendse.
Application Number | 20120208326 12/961107 |
Document ID | / |
Family ID | 43780840 |
Filed Date | 2012-08-16 |
United States Patent
Application |
20120208326 |
Kind Code |
A9 |
Pendse; Rajendra D. |
August 16, 2012 |
Semiconductor Device and Method of Forming Narrow Interconnect
Sites on Substrate with Elongated Mask Openings
Abstract
A semiconductor device has a semiconductor die with a plurality
of bumps formed over a surface of the semiconductor die. A
plurality of conductive traces is formed over a surface of the
substrate with interconnect sites. A masking layer is formed over
the surface of the substrate. The masking layer has a plurality of
parallel elongated openings each exposing at least two of the
conductive traces and permitting a flow of bump material along a
length of the plurality of conductive traces within the plurality
of elongated openings while preventing the flow of bump material
past a boundary of the plurality of elongated openings. One of the
conductive traces passes beneath at least two of the elongated
openings. The bumps are bonded to the interconnect sites so that
the bumps cover a top surface and side surface of the interconnect
sites. An encapsulant is deposited around the bumps between the
semiconductor die and substrate.
Inventors: |
Pendse; Rajendra D.;
(Fremont, CA) |
Assignee: |
STATS CHIPPAC, LTD.
Singapore
SG
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Prior
Publication: |
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Document Identifier |
Publication Date |
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US 20110076809 A1 |
March 31, 2011 |
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Family ID: |
43780840 |
Appl. No.: |
12/961107 |
Filed: |
December 6, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12362627 |
Jan 30, 2009 |
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12961107 |
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11435555 |
May 16, 2006 |
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12362627 |
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60594885 |
May 16, 2005 |
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Current U.S.
Class: |
438/127 ;
257/737; 257/E21.502; 257/E23.068 |
Current CPC
Class: |
H01L 2224/05655
20130101; H01L 2224/13023 20130101; H01L 2224/13111 20130101; H01L
2224/29111 20130101; H01L 2924/01075 20130101; H01L 2924/0133
20130101; H05K 3/3452 20130101; H01L 2224/13109 20130101; H01L
2924/00014 20130101; H01L 2924/13091 20130101; H01L 2224/05655
20130101; H01L 2224/1308 20130101; H01L 2924/1306 20130101; H01L
2224/131 20130101; H01L 2224/05644 20130101; H01L 2924/01027
20130101; H01L 2924/0133 20130101; H01L 2224/13144 20130101; H01L
2224/13111 20130101; H01L 2224/48091 20130101; H01L 2924/01079
20130101; H01L 2924/01082 20130101; H01L 2224/13111 20130101; H01L
2224/16225 20130101; H01L 2224/83192 20130101; H01L 2224/13082
20130101; H01L 2224/1308 20130101; H01L 2224/13111 20130101; H01L
2224/13116 20130101; H01L 2224/13155 20130101; H01L 2924/00013
20130101; H01L 2224/1308 20130101; H01L 2224/05647 20130101; H01L
2224/131 20130101; H01L 2224/16225 20130101; H01L 2924/0133
20130101; H01L 24/81 20130101; H01L 2224/1308 20130101; H01L
2924/12041 20130101; H01L 2924/14 20130101; H01L 24/13 20130101;
H01L 2224/05124 20130101; H01L 2224/05624 20130101; H01L 2224/1308
20130101; H01L 24/48 20130101; H01L 2224/11822 20130101; H01L
2224/13111 20130101; H01L 2224/13144 20130101; H01L 2924/01033
20130101; H01L 2924/0132 20130101; H01L 2924/181 20130101; H01L
2924/0132 20130101; H01L 24/29 20130101; H01L 2924/014 20130101;
H01L 24/73 20130101; H01L 2224/05647 20130101; H01L 2924/00014
20130101; H05K 2201/0989 20130101; H01L 2224/05144 20130101; H01L
2224/1308 20130101; H01L 2924/0105 20130101; H01L 2224/05644
20130101; H01L 2224/05147 20130101; H01L 2224/16225 20130101; H01L
2224/29109 20130101; H01L 2224/81097 20130101; H01L 2224/73265
20130101; H01L 2924/00014 20130101; H05K 2201/10674 20130101; H01L
21/563 20130101; H01L 2224/05124 20130101; H01L 2224/05139
20130101; H01L 2224/05144 20130101; H01L 2224/13111 20130101; H01L
2224/16235 20130101; H01L 2924/01006 20130101; H01L 2924/15174
20130101; H01L 2224/13111 20130101; H01L 24/32 20130101; H01L
2924/01015 20130101; H01L 2924/01322 20130101; H01L 2224/13116
20130101; H01L 2224/73265 20130101; H01L 2224/73265 20130101; H01L
2224/05111 20130101; H01L 2224/27013 20130101; H01L 2924/0132
20130101; H01L 2224/05624 20130101; H01L 2224/05611 20130101; H01L
2224/13111 20130101; H01L 2224/16013 20130101; H01L 2224/16225
20130101; H01L 2224/81208 20130101; H01L 2224/45015 20130101; H01L
2924/00 20130101; H01L 2924/00014 20130101; H01L 2224/05147
20130101; H01L 2224/05155 20130101; H01L 2224/13116 20130101; H01L
2224/16225 20130101; H01L 2224/16225 20130101; H01L 2924/01078
20130101; H01L 24/16 20130101; H01L 2224/13111 20130101; H01L
2924/01013 20130101; H01L 2924/01049 20130101; H01L 2924/181
20130101; H01L 2224/2919 20130101; H01L 2224/16225 20130101; H01L
2224/48091 20130101; H01L 2224/13155 20130101; H01L 2224/83051
20130101; H01L 2924/01029 20130101; H01L 2224/13147 20130101; H01L
2224/16014 20130101; H01L 2224/73204 20130101; H01L 2224/05111
20130101; H01L 2224/13109 20130101; H01L 2224/16237 20130101; H01L
2224/8121 20130101; H01L 2224/81815 20130101; H01L 2924/00013
20130101; H01L 2924/19041 20130101; H01L 2924/181 20130101; H01L
2224/32145 20130101; H01L 2924/00 20130101; H01L 2924/01029
20130101; H01L 2924/01082 20130101; H01L 2924/00014 20130101; H01L
2924/01082 20130101; H01L 2924/00 20130101; H01L 2924/207 20130101;
H01L 2924/00014 20130101; H01L 2224/13111 20130101; H01L 2224/13111
20130101; H01L 2924/00 20130101; H01L 2924/00014 20130101; H01L
2924/0105 20130101; H01L 2924/0105 20130101; H01L 2224/13111
20130101; H01L 2924/00 20130101; H01L 2924/01049 20130101; H01L
2224/45099 20130101; H01L 2924/00014 20130101; H01L 2924/01047
20130101; H01L 2924/01047 20130101; H01L 2224/13111 20130101; H01L
2924/00014 20130101; H01L 2224/13099 20130101; H01L 2924/01049
20130101; H01L 2924/01029 20130101; H01L 2924/0105 20130101; H01L
2924/00 20130101; H01L 2924/014 20130101; H01L 2224/13155 20130101;
H01L 2924/0665 20130101; H01L 2924/00014 20130101; H01L 2924/00014
20130101; H01L 2924/00014 20130101; H01L 2924/014 20130101; H01L
2924/00012 20130101; H01L 2924/00014 20130101; H01L 2924/00014
20130101; H01L 2924/01047 20130101; H01L 2224/13147 20130101; H01L
2924/00012 20130101; H01L 2924/00014 20130101; H01L 2924/01029
20130101; H01L 2924/01047 20130101; H01L 2924/01047 20130101; H01L
2224/131 20130101; H01L 2224/13111 20130101; H01L 2924/00014
20130101; H01L 2924/01029 20130101; H01L 2924/01082 20130101; H01L
2924/01047 20130101; H01L 2924/01029 20130101; H01L 2924/00
20130101; H01L 2224/48227 20130101; H01L 2924/00014 20130101; H01L
2224/48227 20130101; H01L 2924/0105 20130101; H01L 2924/00014
20130101; H01L 2924/01047 20130101; H01L 2924/01047 20130101; H01L
2924/01047 20130101; H01L 2224/13116 20130101; H01L 2224/32145
20130101; H01L 2924/01047 20130101; H01L 2924/00014 20130101; H01L
2224/13111 20130101; H01L 2924/00014 20130101; H01L 2924/00014
20130101; H01L 2224/32145 20130101; H01L 2224/13144 20130101; H01L
2924/00 20130101; H01L 2924/01029 20130101; H01L 2924/0105
20130101; H01L 2924/01047 20130101; H01L 2924/0105 20130101; H01L
2924/00014 20130101; H01L 2924/01029 20130101; H01L 2924/00014
20130101; H01L 2924/01049 20130101; H01L 2924/00 20130101; H01L
2924/00014 20130101; H01L 2924/00014 20130101; H01L 2924/01047
20130101; H01L 2924/00014 20130101; H01L 2924/01082 20130101; H01L
2924/00014 20130101; H01L 2924/0105 20130101; H01L 2924/13091
20130101; H01L 2224/13147 20130101; H01L 2224/1308 20130101; H01L
2924/01046 20130101; H01L 2224/13111 20130101; H01L 2924/0132
20130101; H01L 2924/1306 20130101; H01L 2224/05639 20130101; H01L
2224/05611 20130101; H01L 2224/1308 20130101; H01L 2224/2919
20130101; H01L 2224/48227 20130101; H01L 2224/81191 20130101; H01L
2924/12041 20130101; H01L 2224/05139 20130101; H01L 2224/05155
20130101; H01L 2924/01047 20130101; H01L 2924/01074 20130101; H01L
2924/1433 20130101; H01L 2224/13111 20130101; H01L 2224/05639
20130101; H01L 2224/73203 20130101; H01L 2924/15311 20130101 |
Class at
Publication: |
438/127 ;
257/737; 257/E23.068; 257/E21.502 |
International
Class: |
H01L 21/56 20060101
H01L021/56; H01L 23/498 20060101 H01L023/498 |
Claims
1. A method of making a semiconductor device, comprising: providing
a semiconductor die having a plurality of bumps formed over a
surface of the semiconductor die; providing a substrate; forming a
plurality of conductive traces over a surface of the substrate with
interconnect sites; forming a masking layer over the surface of the
substrate, the masking layer including a plurality of parallel
elongated openings each exposing at least two of the conductive
traces and permitting a flow of bump material along a length of the
plurality of conductive traces within the plurality of elongated
openings while preventing the flow of bump material past a boundary
of the plurality of elongated openings; bonding the bumps to the
interconnect sites so that the bumps cover a top surface and side
surface of the interconnect sites; and depositing an encapsulant
around the bumps between the semiconductor die and substrate.
2. The method of claim 1, wherein one of the plurality of
conductive traces passes beneath at least two of the elongated
openings.
3. The method of claim 1, wherein a length of each of the plurality
of elongated openings is perpendicular to a length of each of the
plurality of conductive traces.
4. The method of claim 1, wherein a width of each of the plurality
of elongated openings is less than 90 micrometers.
5. The method of claim 1, wherein a surface of the substrate is
non-wettable with the bump material.
6. The method of claim 1, wherein the bumps include a fusible
portion and non-fusible portion.
7. A method of making a semiconductor device, comprising: providing
a semiconductor die; providing a substrate; forming a plurality of
conductive traces over a surface of the substrate with interconnect
sites; forming a masking layer over the surface of the substrate,
the masking layer including a plurality of elongated openings
exposing at least two of the conductive traces; forming a plurality
of interconnect structures between the semiconductor die and the
interconnect sites of the substrate; and depositing an encapsulant
between the semiconductor die and substrate.
8. The method of claim 7, wherein one of the plurality of
conductive traces passes beneath at least two of the plurality of
elongated openings.
9. The method of claim 7, wherein a length of each of the plurality
of elongated openings is perpendicular to a length of each of the
plurality of conductive traces.
10. The method of claim 7, wherein a width of each of the plurality
of elongated openings is less than 90 micrometers.
11. The method of claim 7, wherein the elongated openings permit a
flow of bump material along a length of the plurality of conductive
traces within the elongated openings while preventing the flow of
bump material past a boundary of the elongated openings.
12. The method of claim 7, wherein the interconnect structures
include a fusible portion and non-fusible portion.
13. The method of claim 7, wherein the interconnect structures
include a conductive pillar and bump formed over the conductive
pillar.
14. A method of making a semiconductor device, comprising:
providing a semiconductor die; providing a substrate; forming a
plurality of conductive traces over a surface of the substrate with
interconnect sites; forming a masking layer over the surface of the
substrate, the masking layer including a plurality of elongated
openings exposing at least two of the conductive traces; and
forming a plurality of interconnect structures between the
semiconductor die and the interconnect sites of the substrate so
that the interconnect structures cover a top surface and side
surface of the interconnect sites.
15. The method of claim 14, further including depositing an
encapsulant between the semiconductor die and substrate.
16. The method of claim 14, wherein one of the plurality of
conductive traces passes beneath at least two of the plurality of
elongated openings.
17. The method of claim 14, wherein a length of each of the
plurality of elongated openings is perpendicular to a length of
each of the plurality of conductive traces.
18. The method of claim 14, wherein a width of each of the
plurality of elongated openings is less than 90 micrometers.
19. The method of claim 14, wherein the interconnect structures
include a fusible portion and non-fusible portion.
20. The method of claim 14, wherein the interconnect structures
include a conductive pillar and bump formed over the conductive
pillar.
21. A semiconductor device, comprising: a semiconductor die; a
substrate having a plurality of conductive traces formed over a
surface of the substrate with interconnect sites; a masking layer
formed over the surface of the substrate, the masking layer
including a plurality of elongated openings exposing at least two
of the conductive traces; a plurality of interconnect structures
formed between the semiconductor die and the interconnect sites of
the substrate; and an encapsulant deposited between the
semiconductor die and substrate.
22. The semiconductor device of claim 21, wherein one of the
plurality of conductive traces passes beneath at least two of the
plurality of elongated openings.
23. The semiconductor device of claim 21, wherein a length of each
of the plurality of elongated openings is perpendicular to a length
of each of the plurality of conductive traces.
24. The semiconductor device of claim 21, wherein the interconnect
structures include a fusible portion and non-fusible portion.
25. The semiconductor device of claim 21, wherein the interconnect
structures include a conductive pillar and bump formed over the
conductive pillar.
Description
CLAIM TO DOMESTIC PRIORITY
[0001] The present application is a continuation-in-part of U.S.
patent application Ser. No. 12/362,627, filed Jan. 30, 2009, and
claims priority to the foregoing parent application pursuant to 35
U.S.C. .sctn. 120.
FIELD OF THE INVENTION
[0002] The present invention relates to semiconductor devices and,
particularly, to a semiconductor device and method of forming
narrow interconnect sites on a substrate with elongated mask
openings.
BACKGROUND OF THE INVENTION
[0003] Semiconductor devices are commonly found in modern
electronic products. Semiconductor devices vary in the number and
density of electrical components. Discrete semiconductor devices
generally contain one type of electrical component, e.g., light
emitting diode (LED), small signal transistor, resistor, capacitor,
inductor, and power metal oxide semiconductor field effect
transistor (MOSFET). Integrated semiconductor devices typically
contain hundreds to millions of electrical components. Examples of
integrated semiconductor devices include microcontrollers,
microprocessors, charged-coupled devices (CCDs), solar cells, and
digital micro-mirror devices (DMDs).
[0004] Semiconductor devices perform a wide range of functions such
as signal processing, high-speed calculations, transmitting and
receiving electromagnetic signals, controlling electronic devices,
transforming sunlight to electricity, and creating visual
projections for television displays. Semiconductor devices are
found in the fields of entertainment, communications, power
conversion, networks, computers, and consumer products.
Semiconductor devices are also found in military applications,
aviation, automotive, industrial controllers, and office
equipment.
[0005] Semiconductor devices exploit the electrical properties of
semiconductor materials. The atomic structure of semiconductor
material allows its electrical conductivity to be manipulated by
the application of an electric field or base current or through the
process of doping. Doping introduces impurities into the
semiconductor material to manipulate and control the conductivity
of the semiconductor device.
[0006] A semiconductor device contains active and passive
electrical structures. Active structures, including bipolar and
field effect transistors, control the flow of electrical current.
By varying levels of doping and application of an electric field or
base current, the transistor either promotes or restricts the flow
of electrical current. Passive structures, including resistors,
capacitors, and inductors, create a relationship between voltage
and current necessary to perform a variety of electrical functions.
The passive and active structures are electrically connected to
form circuits, which enable the semiconductor device to perform
high-speed calculations and other useful functions.
[0007] Semiconductor devices are generally manufactured using two
complex manufacturing processes, i.e., front-end manufacturing, and
back-end manufacturing, each involving potentially hundreds of
steps. Front-end manufacturing involves the formation of a
plurality of die on the surface of a semiconductor wafer. Each die
is typically identical and contains circuits formed by electrically
connecting active and passive components. Back-end manufacturing
involves singulating individual die from the finished wafer and
packaging the die to provide structural support and environmental
isolation.
[0008] One goal of semiconductor manufacturing is to produce
smaller semiconductor devices. Smaller devices typically consume
less power, have higher performance, and can be produced more
efficiently. In addition, smaller semiconductor devices have a
smaller footprint, which is desirable for smaller end products. A
smaller die size can be achieved by improvements in the front-end
process resulting in die with smaller, higher density active and
passive components. Back-end processes may result in semiconductor
device packages with a smaller footprint by improvements in
electrical interconnection and packaging materials.
[0009] In conventional flipchip type packages, a semiconductor die
is mounted to a package substrate with the active side of the die
facing the substrate. Conventionally, the interconnection of the
circuitry in the semiconductor die with circuitry in the substrate
is made by way of bumps which are attached to an array of
interconnect pads on the die and bonded to a corresponding
complementary array of interconnect pads, often referred to as
capture pads on the substrate.
[0010] The areal density of electronic features on integrated
circuits has increased enormously, and a semiconductor die having a
greater density of circuit features also may have a greater density
of sites for interconnection with the package substrate.
[0011] The package is connected to underlying circuitry, such as a
printed circuit board or motherboard, by way of second level
interconnects between the package and underlying circuit. The
second level interconnects have a greater pitch than the flipchip
interconnects, and so the routing on the substrate conventionally
fans out. Significant technological advances have enabled
construction of fine lines and spaces. In the conventional
arrangement, space between adjacent pads limits the number of
traces than can escape from the more inward capture pads in the
array. The fan-out routing between the capture pads beneath the
semiconductor die and external pins of the package is formed on
multiple metal layers within the package substrate. For a complex
interconnect array, substrates having multiple layers can be
required to achieve routing between the die pads and second level
interconnects on the package.
[0012] Multiple layer substrates are expensive and, in conventional
flipchip constructs, the substrate alone typically accounts for
more than half the package cost. The high cost of multilayer
substrates has been a factor in limiting proliferation of flipchip
technology in mainstream products. The escape routing pattern
typically introduces additional electrical parasitics because the
routing includes short runs of unshielded wiring and vias between
wiring layers in the signal transmission path. Electrical
parasitics can significantly limit package performance.
[0013] In some conventional processes, a flipchip interconnect is
made by contacting the bumps or balls on the semiconductor die with
corresponding interconnect sites on the substrate circuitry, and
then heating to reflow the fusible portion of the solder bumps or
to reflow the solder bumps in their entirety to make the electrical
connection. In such processes, the melted solder may flow from the
interconnect site along the metal of the circuitry, depleting the
solder at the connection site and, where the bumps are collapsible
under reflow conditions, the bumps may contact adjacent circuitry
or nearby bumps, resulting in electrical failure. To avoid these
problems, the solder is confined by a solder mask formed as a layer
of dielectric material overlying the patterned metal layer at the
die mount surface of the substrate with an opening exposing an
interconnect site on the underlying circuitry. Process limitations
in patterning the solder mask prevent reliably forming well-aligned
and consistently dimensioned openings and, accordingly, where a
solder mask is employed, substrates having fine circuitry feature
dimensions as would be required for finer pitch interconnection are
not attainable.
[0014] The interconnect pitch in a conventional flipchip
interconnect is limited in part by the dimensions of the capture
pads on the substrate. The capture pads are typically much wider
than the connecting circuit elements. Recently, flipchip substrate
circuitry designs have been disclosed, in which reliable
interconnection is made on narrow circuit elements on the
substrate, as bond-on-narrow pad (BONP) interconnections described
in U.S. patent publication 20060216860, and as bump-on-lead (BOL)
interconnections described in U.S. patent publication 20050110164,
both incorporated by reference. Where a conventional solder mask is
employed, limitations in the process for patterning the solder mask
can limit pitch reduction even in some BONP or BOL substrate
configurations. The exposed bondable surface of the lead may be
contaminated by or covered by solder mask residue, resulting in an
imperfect solder joint. The bondable surface of the lead may be
inconsistently or only partially exposed at the interconnect site,
resulting in an unreliable and inconsistent trace structure.
[0015] The conventional flipchip interconnection is made by using a
melting process to join the bumps onto mating surfaces of
corresponding interconnect sites on the patterned metal layer at
the die attach surface of the substrate. Where the site is a
capture pad, the interconnect is known as a bump-on-capture pad
(BOC) interconnect. Where the site is a lead or narrow pad, the
interconnect is known as a BOL or BONP interconnect. In the BOC
design, a comparatively large capture pad is required to mate with
the bump on the semiconductor die. In some flipchip
interconnections, an insulating material or solder mask is required
to confine the flow of solder during the interconnection process.
The solder mask opening defines the contour of the melted solder at
the capture pad, i.e., solder mask defined, or the solder contour
may not be defined by the mask opening, i.e., non-solder mask
defined. In the latter case, the solder mask opening is
significantly larger than the capture pad. Since the techniques for
defining solder mask openings have wide tolerance ranges for a
solder mask defined bump configuration, the capture pad must be
large, typically considerably larger than the design size for the
mask opening, to ensure that the mask opening is located on the
mating surface of the pad. For a non-solder mask defined bump
configuration, the solder mask opening must be larger than the
capture pad. The width or diameter of capture pads can be as much
as two to four times wider than the trace width. The larger width
of the capture pads results in considerable loss of routing space
on the top substrate layer. In particular, the escape routing pitch
is much larger than the finest trace pitch that the substrate
technology can offer. A significant number of pads must be routed
on lower substrate layers by means of short stubs and vias, often
beneath the footprint of the die, emanating from the pads in
question.
[0016] FIGS. 1-3 show aspects of a conventional flipchip
interconnection using a solder mask. FIG. 1 shows substrate 12 in a
diagrammatic sectional view or plan view taken in a plane parallel
to the substrate surface. Certain features are shown as if
transparent. Substrate 12 includes a dielectric layer, supporting a
metal layer at the die attach surface, patterned to form circuitry
underlying the solder mask. The circuitry includes leads or traces
15 exposed at interconnect sites 19 by openings 18 in solder mask
16, as shown in FIG. 2. The conventional solder mask can have a
nominal mask opening diameter in the range of 80 to 90 micrometers
(.mu.m). Solder mask materials can be resolved at such pitches and,
particularly, substrates can be made comparatively inexpensively
with solder masks having 90 .mu.m openings and alignment tolerances
plus or minus 25 .mu.m. In some embodiments, laminate substrates
made according to standard design rules, such as 4-metal layer
laminates, are used. Traces 15 have a 90 .mu.m pitch and the narrow
pads are located in a 270 .mu.m area array providing an effective
escape pitch about 90 .mu.m across the edge of the die footprint,
indicated by broken line 11.
[0017] In FIG. 3, the interconnection of semiconductor die 34 onto
substrate 12 is achieved by mating bumps 35 directly onto
interconnect sites 19 on narrow leads or traces 15 patterned on a
dielectric layer on the die attach surface of substrate 12. In this
example there is no pad, and solder mask 16 serves to limit flow of
solder within the bounds of mask openings 18, preventing solder
flow away from the interconnect site along the solder-wettable
lead. The solder mask also confines flow of molten solder between
leads in the course of the assembly process. However, the density
of flipchip interconnection in which a solder mask is desired is
limited by process capability of the solder mask patterning
process.
[0018] An underfill material 37 between the active side of
semiconductor die 34 and solder mask 16 over substrate 12 protects
the interconnections and mechanically stabilizes the assembly.
Underfill material 37 can be a curable resin plus a filler, which
is typically a fine particulate material such as silica or alumina
particles. The particular resin and filler, as well as the
proportion of filler in the resin, are selected to provide suitable
mechanical and adhesion properties to underfill material 37, both
during processing and in the resulting underfill. Underfill
material 37 is formed after the interconnection has been made
between interconnect sites 19 on substrate 12 and bumps 35 on
semiconductor die 34 by applying the underfill material in a liquid
form to the narrow space between the die and substrate near an edge
of the die. Underfill material 37 is permitted to flow by capillary
action into the space, referred to as capillary underfill.
Alternatively, underfill material 37 is deposited by applying a
quantity of the underfill material to the active side of
semiconductor die 34 or to solder mask 16 over substrate 12, then
moving the die toward the substrate and pressing bumps 35 against
interconnect sites 19, referred to as no-flow underfill.
[0019] FIGS. 4 and 5 show aspects of a conventional flipchip
interconnection without using a solder mask. FIG. 4 shows a package
assembly, in a diagrammatic partial sectional view taken in a plane
parallel to the substrate surface, along the lines 4-4' in FIG. 5.
Certain features are shown as if transparent. FIG. 5 shows a
partial sectional view of a package as in FIG. 4, taken in a plane
perpendicular to the plane of the package substrate surface, along
line 5-5' in FIG. 4.
[0020] FIG. 4 shows an escape routing pattern for substrate 42
arranged for the semiconductor die on which the die attach pads are
located in an array of parallel rows near the die perimeter. The
patterned traces or leads 43 are routed according to a pattern
complementary to the arrangement of bumps 45 on the semiconductor
die. The BOL interconnection is achieved by mating bumps 45
directly onto respective interconnect sites 40 of narrow leads or
traces 43 on substrate 42 in a complementary array near the edge of
the die footprint, indicated by broken line 41. The leads 43 are
formed by patterning a metal layer on a die attach surface of
substrate dielectric layer 42. The electrical interconnection of
semiconductor die 46 is made by joining bumps 45 formed on
interconnect pads on the active side of the die onto interconnect
sites 40, as shown in FIG. 5. Certain ones of escape traces 43 pass
between bumps 45 and are routed across substrate 42 in rows toward
the interior of the die footprint.
[0021] Without a solder mask, the molten bump material can be
confined by a non-collapsible bump with solder on the interconnect
site. Alternatively, an encapsulating resin adhesive is employed in
a no-flow underfill process to confine the solder flow during the
melt phase of the interconnection process. The no-flow underfill
material is applied before semiconductor die 46 and substrate 42
are brought together. The no-flow underfill material is displaced
by the approach of bumps 45 onto interconnect sites 40, and by the
opposed surfaces of the die and the substrate. The adhesive for the
no-flow underfill material can be a fast-gelling adhesive or other
material that gels sufficiently at the gel temperature in a time
period in the order of 1-2 seconds.
SUMMARY OF THE INVENTION
[0022] A need exists to minimize escape pitch of trace lines for
higher routing density. Accordingly, in one embodiment, the present
invention is a method of making a semiconductor device comprising
the steps of providing a semiconductor die having a plurality of
bumps formed over a surface of the semiconductor die, providing a
substrate, forming a plurality of conductive traces over a surface
of the substrate with interconnect sites, and forming a masking
layer over the surface of the substrate. The masking layer has a
plurality of parallel elongated openings each exposing at least two
of the conductive traces and permitting a flow of bump material
along a length of the plurality of conductive traces within the
plurality of elongated openings while preventing the flow of bump
material past a boundary of the plurality of elongated openings.
The method further includes the steps of bonding the bumps to the
interconnect sites so that the bumps cover a top surface and side
surface of the interconnect sites, and depositing an encapsulant
around the bumps between the semiconductor die and substrate.
[0023] In another embodiment, the present invention is a method of
making a semiconductor device comprising the steps of providing a
semiconductor die, providing a substrate, forming a plurality of
conductive traces over a surface of the substrate with interconnect
sites, forming a masking layer over the surface of the substrate,
forming a plurality of interconnect structures between the
semiconductor die and the interconnect sites of the substrate, and
depositing an encapsulant between the semiconductor die and
substrate. The solder mask has a plurality of elongated openings
exposing at least two of the conductive traces.
[0024] In another embodiment, the present invention is a method of
making a semiconductor device comprising the steps of providing a
semiconductor die, providing a substrate, forming a plurality of
conductive traces over a surface of the substrate with interconnect
sites, forming a masking layer over the surface of the substrate,
and forming a plurality of interconnect structures between the
semiconductor die and the interconnect sites of the substrate so
that the interconnect structures cover a top surface and side
surface of the interconnect sites. The solder mask has a plurality
of elongated openings exposing at least two of the conductive
traces.
[0025] In another embodiment, the present invention is a
semiconductor device comprising a semiconductor die and substrate
having a plurality of conductive traces formed over a surface of
the substrate with interconnect sites. A masking layer is formed
over the surface of the substrate. The masking layer has a
plurality of elongated openings exposing at least two of the
conductive traces. A plurality of interconnect structures is formed
between the semiconductor die and the interconnect sites of the
substrate. An encapsulant is deposited between the semiconductor
die and substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0026] FIG. 1 illustrates a conventional flipchip package substrate
with a solder mask parallel to a plane of the package substrate
surface;
[0027] FIG. 2 illustrates a conventional flipchip package substrate
with a solder mask perpendicular to a plane of the package
substrate surface;
[0028] FIG. 3 illustrates a conventional flipchip assembly with a
semiconductor die interconnected on a substrate;
[0029] FIG. 4 illustrates a conventional flipchip interconnection
of a semiconductor die on a substrate without a solder mask;
[0030] FIG. 5 illustrates the semiconductor die mounted to the
substrate without a solder mask as in FIG. 4;
[0031] FIG. 6 illustrates a PCB with different types of packages
mounted to its surface;
[0032] FIGS. 7a-7c illustrate further detail of the representative
semiconductor packages mounted to the PCB;
[0033] FIG. 8 illustrates a flipchip package substrate with a
solder mask having elongated openings parallel to a plane of the
package substrate surface;
[0034] FIG. 9 illustrates the flipchip interconnection of FIG. 8
employing the solder mask with elongated openings perpendicular to
the plane of the package substrate surface;
[0035] FIG. 10 illustrates a flipchip assembly with a semiconductor
die interconnected on a substrate as in FIGS. 8 and 9;
[0036] FIGS. 11a-11h illustrate various interconnect structures
formed over a semiconductor die for bonding to conductive traces on
a substrate;
[0037] FIGS. 12a-12g illustrate the semiconductor die and
interconnect structure bonded to the conductive traces;
[0038] FIGS. 13a-13d illustrate the semiconductor die with a
wedge-shaped interconnect structure bonded to the conductive
traces;
[0039] FIGS. 14a-14d illustrate another embodiment of the
semiconductor die and interconnect structure bonded to the
conductive traces;
[0040] FIGS. 15a-15c illustrate stepped bump and stud bump
interconnect structures bonded to the conductive traces;
[0041] FIGS. 16a-16b illustrate conductive traces with conductive
vias;
[0042] FIGS. 17a-17c illustrate mold underfill between the
semiconductor die and substrate;
[0043] FIG. 18 illustrates another mold underfill between the
semiconductor die and substrate;
[0044] FIG. 19 illustrates the semiconductor die and substrate
after mold underfill;
[0045] FIGS. 20a-20g illustrate various arrangements of the
conductive traces with open solder registration;
[0046] FIGS. 21a-21b illustrate the open solder registration with
patches between the conductive traces; and
[0047] FIG. 22 illustrates a POP with masking layer dam to restrain
the encapsulant during mold underfill.
DETAILED DESCRIPTION OF THE DRAWINGS
[0048] The present invention is described in one or more
embodiments in the following description with reference to the
figures, in which like numerals represent the same or similar
elements. While the invention is described in terms of the best
mode for achieving the invention's objectives, it will be
appreciated by those skilled in the art that it is intended to
cover alternatives, modifications, and equivalents as can be
included within the spirit and scope of the invention as defined by
the appended claims and their equivalents as supported by the
following disclosure and drawings.
[0049] Semiconductor devices are generally manufactured using two
complex manufacturing processes: front-end manufacturing and
back-end manufacturing. Front-end manufacturing involves the
formation of a plurality of die on the surface of a semiconductor
wafer. Each die on the wafer contains active and passive electrical
components, which are electrically connected to form functional
electrical circuits. Active electrical components, such as
transistors and diodes, have the ability to control the flow of
electrical current. Passive electrical components, such as
capacitors, inductors, resistors, and transformers, create a
relationship between voltage and current necessary to perform
electrical circuit functions.
[0050] Passive and active components are formed over the surface of
the semiconductor wafer by a series of process steps including
doping, deposition, photolithography, etching, and planarization.
Doping introduces impurities into the semiconductor material by
techniques such as ion implantation or thermal diffusion. The
doping process modifies the electrical conductivity of
semiconductor material in active devices, transforming the
semiconductor material into an insulator, conductor, or dynamically
changing the semiconductor material conductivity in response to an
electric field or base current. Transistors contain regions of
varying types and degrees of doping arranged as necessary to enable
the transistor to promote or restrict the flow of electrical
current upon the application of the electric field or base
current.
[0051] Active and passive components are formed by layers of
materials with different electrical properties. The layers can be
formed by a variety of deposition techniques determined in part by
the type of material being deposited. For example, thin film
deposition can involve chemical vapor deposition (CVD), physical
vapor deposition (PVD), electrolytic plating, and electroless
plating processes. Each layer is generally patterned to form
portions of active components, passive components, or electrical
connections between components.
[0052] The layers can be patterned using photolithography, which
involves the deposition of light sensitive material, e.g.,
photoresist, over the layer to be patterned. A pattern is
transferred from a photomask to the photoresist using light. The
portion of the photoresist pattern subjected to light is removed
using a solvent, exposing portions of the underlying layer to be
patterned. The remainder of the photoresist is removed, leaving
behind a patterned layer. Alternatively, some types of materials
are patterned by directly depositing the material into the areas or
voids formed by a previous deposition/etch process using techniques
such as electroless and electrolytic plating.
[0053] Depositing a thin film of material over an existing pattern
can exaggerate the underlying pattern and create a non-uniformly
flat surface. A uniformly flat surface is required to produce
smaller and more densely packed active and passive components.
Planarization can be used to remove material from the surface of
the wafer and produce a uniformly flat surface. Planarization
involves polishing the surface of the wafer with a polishing pad.
An abrasive material and corrosive chemical are added to the
surface of the wafer during polishing. The combined mechanical
action of the abrasive and corrosive action of the chemical removes
any irregular topography, resulting in a uniformly flat
surface.
[0054] Back-end manufacturing refers to cutting or singulating the
finished wafer into the individual die and then packaging the die
for structural support and environmental isolation. To singulate
the die, the wafer is scored and broken along non-functional
regions of the wafer called saw streets or scribes. The wafer is
singulated using a laser cutting tool or saw blade. After
singulation, the individual die are mounted to a package substrate
that includes pins or contact pads for interconnection with other
system components. Contact pads formed over the semiconductor die
are then connected to contact pads within the package. The
electrical connections can be made with solder bumps, stud bumps,
conductive paste, or wirebonds. An encapsulant or other molding
material is deposited over the package to provide physical support
and electrical isolation. The finished package is then inserted
into an electrical system and the functionality of the
semiconductor device is made available to the other system
components.
[0055] FIG. 6 illustrates electronic device 50 having a chip
carrier substrate or printed circuit board (PCB) 52 with a
plurality of semiconductor packages mounted on its surface.
Electronic device 50 can have one type of semiconductor package, or
multiple types of semiconductor packages, depending on the
application. The different types of semiconductor packages are
shown in FIG. 6 for purposes of illustration.
[0056] Electronic device 50 can be a stand-alone system that uses
the semiconductor packages to perform one or more electrical
functions. Alternatively, electronic device 50 can be a
subcomponent of a larger system. For example, electronic device 50
can be part of a cellular phone, personal digital assistant (PDA),
digital video camera (DVC), or other electronic communication
device. Alternatively, electronic device 50 can be a graphics card,
network interface card, or other signal processing card that can be
inserted into a computer. The semiconductor package can include
microprocessors, memories, application specific integrated circuits
(ASIC), logic circuits, analog circuits, RF circuits, discrete
devices, or other semiconductor die or electrical components. The
miniaturization and the weight reduction are essential for these
products to be accepted by the market. The distance between
semiconductor devices must be decreased to achieve higher
density.
[0057] In FIG. 6, PCB 52 provides a general substrate for
structural support and electrical interconnect of the semiconductor
packages mounted on the PCB. Conductive signal traces 54 are formed
over a surface or within layers of PCB 52 using evaporation,
electrolytic plating, electroless plating, screen printing, or
other suitable metal deposition process. Signal traces 54 provide
for electrical communication between each of the semiconductor
packages, mounted components, and other external system components.
Traces 54 also provide power and ground connections to each of the
semiconductor packages.
[0058] In some embodiments, a semiconductor device has two
packaging levels. First level packaging is a technique for
mechanically and electrically attaching the semiconductor die to an
intermediate carrier. Second level packaging involves mechanically
and electrically attaching the intermediate carrier to the PCB. In
other embodiments, a semiconductor device may only have the first
level packaging where the die is mechanically and electrically
mounted directly to the PCB.
[0059] For the purpose of illustration, several types of first
level packaging, including wire bond package 56 and flipchip 58,
are shown on PCB 52. Additionally, several types of second level
packaging, including ball grid array (BGA) 60, bump chip carrier
(BCC) 62, dual in-line package (DIP) 64, land grid array (LGA) 66,
multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70,
and quad flat package 72, are shown mounted on PCB 52. Depending
upon the system requirements, any combination of semiconductor
packages, configured with any combination of first and second level
packaging styles, as well as other electronic components, can be
connected to PCB 52. In some embodiments, electronic device 50
includes a single attached semiconductor package, while other
embodiments call for multiple interconnected packages. By combining
one or more semiconductor packages over a single substrate,
manufacturers can incorporate pre-made components into electronic
devices and systems. Because the semiconductor packages include
sophisticated functionality, electronic devices can be manufactured
using cheaper components and a streamlined manufacturing process.
The resulting devices are less likely to fail and less expensive to
manufacture resulting in a lower cost for consumers.
[0060] FIGS. 7a-7c show exemplary semiconductor packages. FIG. 7a
illustrates further detail of DIP 64 mounted on PCB 52.
Semiconductor die 74 includes an active region containing analog or
digital circuits implemented as active devices, passive devices,
conductive layers, and dielectric layers formed within the die and
are electrically interconnected according to the electrical design
of the die. For example, the circuit can include one or more
transistors, diodes, inductors, capacitors, resistors, and other
circuit elements formed within the active region of semiconductor
die 74. Contact pads 76 are one or more layers of conductive
material, such as aluminum (Al), copper (Cu), tin (Sn), nickel
(Ni), gold (Au), or silver (Ag), and are electrically connected to
the circuit elements formed within semiconductor die 74. During
assembly of DIP 64, semiconductor die 74 is mounted to an
intermediate carrier 78 using a gold-silicon eutectic layer or
adhesive material such as thermal epoxy or epoxy resin. The package
body includes an insulative packaging material such as polymer or
ceramic. Conductor leads 80 and wire bonds 82 provide electrical
interconnect between semiconductor die 74 and PCB 52. Encapsulant
84 is deposited over the package for environmental protection by
preventing moisture and particles from entering the package and
contaminating die 74 or wire bonds 82.
[0061] FIG. 7b illustrates further detail of BCC 62 mounted on PCB
52. Semiconductor die 88 is mounted over carrier 90 using an
underfill or epoxy-resin adhesive material 92. Wire bonds 94
provide first level packaging interconnect between contact pads 96
and 98. Molding compound or encapsulant 100 is deposited over
semiconductor die 88 and wire bonds 94 to provide physical support
and electrical isolation for the device. Contact pads 102 are
formed over a surface of PCB 52 using a suitable metal deposition
process such as electrolytic plating or electroless plating to
prevent oxidation. Contact pads 102 are electrically connected to
one or more conductive signal traces 54 in PCB 52. Bumps 104 are
formed between contact pads 98 of BCC 62 and contact pads 102 of
PCB 52.
[0062] In FIG. 7c, semiconductor die 58 is mounted face down to
intermediate carrier 106 with a flipchip style first level
packaging. Active region 108 of semiconductor die 58 contains
analog or digital circuits implemented as active devices, passive
devices, conductive layers, and dielectric layers formed according
to the electrical design of the die. For example, the circuit can
include one or more transistors, diodes, inductors, capacitors,
resistors, and other circuit elements within active region 108.
Semiconductor die 58 is electrically and mechanically connected to
carrier 106 through bumps 110.
[0063] BGA 60 is electrically and mechanically connected to PCB 52
with a BGA style second level packaging using bumps 112.
Semiconductor die 58 is electrically connected to conductive signal
traces 54 in PCB 52 through bumps 110, signal lines 114, and bumps
112. A molding compound or encapsulant 116 is deposited over
semiconductor die 58 and carrier 106 to provide physical support
and electrical isolation for the device. The flipchip semiconductor
device provides a short electrical conduction path from the active
devices on semiconductor die 58 to conduction tracks on PCB 52 in
order to reduce signal propagation distance, lower capacitance, and
improve overall circuit performance. In another embodiment, the
semiconductor die 58 can be mechanically and electrically connected
directly to PCB 52 using flipchip style first level packaging
without intermediate carrier 106.
[0064] In a flipchip type semiconductor die, the interconnect is
accomplished by connecting the interconnect bump directly onto a
narrow interconnection pad or narrow pad, rather than onto a
conventional capture pad. The flipchip package substrate has a
patterned metal layer on a die attach side of a dielectric
substrate layer, a metal layer including interconnect sites, and a
substrate including a masking layer having an opening spanning a
plurality of the interconnect sites and traces. The opening has a
generally elongated shape oriented so that its longer dimension
spans multiple interconnect sites, traces, and other circuit
elements. The shorter dimension of the elongated openings limit the
exposure of the lengths of the interconnect sites. Accordingly, the
flow of fusible material that is melted during the reflow step in
the interconnection process is limited along the length of the
interconnect sites by the width of the mask opening. The number of
interconnect sites on which the flow of melted bump material is so
limited is determined by the length of the mask opening and the
number of interconnect sites spanned by the opening. The masking
layer allows confinement of the bump material during the remelt
stage of interconnection, yet it is within common design rules for
mask patterning.
[0065] FIG. 8 shows substrate 120, in a diagrammatic sectional view
or plan view taken in a plane parallel to the substrate surface.
Certain features are shown as if transparent. Substrate 120 has a
dielectric layer supporting a metal layer at the die attach
surface, patterned to form circuitry underlying the masking layer.
The circuitry includes traces or leads 124 exposed at interconnect
sites 126a, 126b, and 126c by elongated openings 128a, 128b, and
128c in masking layer 130, as shown in FIG. 9. The interconnect
sites 126a-126c are arranged in an orthogonal array of three rows
each generally parallel to the die edge, as indicated by broken
line 132.
[0066] The elongated openings 128a-128c in masking layer 130 expose
multiple interconnect sites 126a-126c associated with two or more
adjacent circuit features. As shown in FIG. 8, each of the
elongated openings 128a-128c exposes one of the rows of
interconnect sites 126a-126c, which can be a row on an array of
interconnect sites. The row of interconnect sites 126a-126c exposed
need not be in a straight line, that is openings 128a-128c need not
be rectangular. The openings 128a-128c can have a regular or
irregular shape. Where the elongated openings 128a-128c have a
shape of a regular polygon, such as a rectangle, the elongated
opening need not necessarily be oriented parallel to a row of
interconnect sites or to the die margin. In addition, some of leads
124 pass beneath multiple elongated openings 128a-128c.
[0067] In FIG. 10, a flipchip interconnect structure is formed by
providing semiconductor die 140 with bumps 142 attached to die
pads, and bonding bumps 142 onto interconnect sites 126 on
substrate 120 in a high trace density arrangement. Other leads 124
are interconnected at other localities, which would be visible in
other sectional views. The narrow dimension width of the elongated
masking openings 128a-128c serves to limit flow of bump material
away from interconnect sites 126a-126c along the wettable lead 124.
The width of the elongated mask openings 128a-128c can be
determined by the design rules for patterning the masking layer. In
one embodiment, the nominal mask opening width can be in the range
about 80 to 90 .mu.m or less. Alternatively, the nominal mask
opening width can be 100 .mu.m or more. Mask materials can be
resolved at such pitches and, particularly, substrates can be made
comparatively inexpensively with masking layers having 90 .mu.m
openings and having alignment tolerances plus or minus 25 .mu.m. In
some embodiments, laminate substrates made according to standard
design rules, such as 4-metal layer laminates, are used.
[0068] The feature sizes required for masking layer 130 can be made
coarser because the elongated mask openings 128a-128c span a number
of interconnect sites 126a-126c. The alignment of mask openings
128a-128c with interconnect sites 126a-126c can be significantly
relaxed. The risk of partial exposure of bondable areas of leads
124 at interconnect sites 126a-126c is practically avoided. Bump
material run-off along the length of the circuit features at
interconnect sites 126a-126c is confined by the width of mask
openings 128a-128c. Any runoff toward adjacent circuit features is
reduced because the dielectric material of substrate 120 is not
wettable by the bump material.
[0069] The electrical interconnect can be formed by
thermo-mechanically joining bump 142 to interconnect sites
126a-126c without melting the bump material. A no-flow underfill
material is cured to a gel stage. Bumps 142 are then melted in a
reflow operation to form a reliable interconnection which confines
the joint to a relatively small volume and minimizes the risk of
bridging to an adjacent circuit element. In some embodiments,
fillets are formed along the surrounding surface and exposed
sidewalls of interconnect sites 126a-126c.
[0070] Solder paste can be provided at interconnect sites 126a-126c
on leads 124, to provide a fusible medium for the interconnect. The
paste is dispensed by a printing process, reflowed, and coined if
necessary to provide uniform surfaces to meet bumps 142. The solder
paste can be applied in the course of assembly, or a substrate can
be provided with paste suitably patterned prior to assembly. Other
approaches to applying solder selectively to interconnect sites
126a-126c include solder-on-lead embodiments, such as electroless
plating and electroplating techniques. The solder-on-lead
configuration provides additional solder volume for the
interconnect, and can provide higher product yield and higher die
standoff.
[0071] For interconnection of a semiconductor die having
high-melting temperature bumps onto an organic substrate, such as a
high-lead solder used with ceramic substrates, the masking layer
limits the flow of fusible solder paste along the circuit element
near the interconnect site. The solder paste can be selected to
have a melting temperature low enough that the organic substrate is
not damaged during reflow. To form the interconnect in such
embodiments, the high-melting interconnect bumps are contacted with
the solder-on-lead sites, and the remelt fuses the solder-on-lead
to the bumps. Where a non-collapsible bump is used, together with a
solder-on-lead process, no preapplied adhesive is required, as the
displacement or flow of the solder is limited by the fact that only
a small quantity of solder is present at each interconnect. The
non-collapsible bump prevents collapse of the assembly. In other
embodiments, the solder-on-lead configuration can use eutectic
solder bumps.
[0072] For packages employing no-flow underfill techniques, a
substrate is provided with at least one dielectric layer and having
a metal layer on a die attach surface. The metal layer is patterned
to provide circuitry, particularly traces or leads with
interconnect sites on the die attach surface. The substrate is
supported, for example on a carrier or stage, with a substrate
surface opposite the die attach surface facing the support. A
semiconductor die is provided with bumps attached to die pads on
the active side. The bumps include a fusible material which
contacts the mating surfaces of the leads. A quantity of an
underfill material, such as an encapsulating resin adhesive, is
dispensed over the die attach surface of the substrate, covering
the interconnect sites on the leads over the active side of the
semiconductor die. A pick-and-place tool with a chuck picks up the
semiconductor die by contacting of the chuck with the backside of
the die. Using the pick-and-place tool, the semiconductor die is
positioned facing the substrate with the active side of the die
toward the die attach surface of the substrate. The semiconductor
die and substrate are aligned and moved one toward the other so
that the bumps contact the corresponding interconnect sites on the
traces or leads on the substrate. A force is applied to press the
bumps onto the mating surfaces at the interconnect sites on the
leads. The force is sufficient to displace the adhesive from
between the bumps and the mating surfaces at the interconnect sites
on the leads. The bumps are deformed by the force, breaking the
oxide film on the contacting surface of the bumps and/or on the
interconnect sites of leads. The deformation of the bumps may
result in the fusible material of the bumps being pressed onto the
top and over the edges of the interconnect sites. The adhesive is
caused to cure at least partially by heating to a selected
temperature. At this stage, the adhesive need only be partially
cured to an extent sufficient subsequently to prevent flow of
molten bump material along an interface between the adhesive and
the conductive traces. The fusible material of the bumps is melted
and then is re-solidified, forming a metallurgical interconnection
between the bump and interconnect site. The adhesive is completely
cured to finish the die mount and secure the electrical
interconnection at the mating surface.
[0073] Where interconnect is formed by a no-flow underfill process,
the no-flow underfill adhesive can be pre-applied to the die
surface, or at least to the bumps on the die surface, rather than
to the substrate. The adhesive can be pooled in a reservoir, and
the active side of the semiconductor die can be dipped in the pool
and removed so that a quantity of the adhesive is carried on the
bumps. Using a pick-and-place tool, the semiconductor die is
positioned facing a supported substrate with the active side of the
die toward the die attach surface of the substrate. The
semiconductor die and substrate are aligned and moved one toward
the other so that the bumps contact the corresponding interconnect
sites on the substrate. Such a method is described in U.S. Pat. No.
6,780,682, which is incorporated by reference. Then forcing,
curing, and melting are carried out as described above.
[0074] In some approaches to flipchip interconnection, the
metallurgical interconnection is formed first, and then an
underfill material is flowed into the space between the
semiconductor die and substrate. The no-flow underfill material is
applied before the semiconductor die and substrate are brought
together. The no-flow underfill material is displaced by the
approach of the bumps onto the interconnect sites, and by the
opposed surfaces of the die and the substrate. The no-flow
underfill material can be non-conductive pastes or fast-gelling
adhesive that gels sufficiently at the gel temperature in a time
period in the order of 1-2 seconds.
[0075] The curing of the adhesive can be completed prior to, or
concurrently with, or following melting the bump material.
Typically, the adhesive is a thermally curable adhesive, and the
extent of curing at any phase in the process is controlled by
regulating the temperature. The components can be heated and cured
by raising the temperature of the chuck on the pick and place tool,
or by raising the temperature of the substrate support.
[0076] Alternative bump structures, such as composite bumps, can be
employed in the BOL interconnects. Composite bumps have at least
two bump portions, made of different bump materials, including one
which is collapsible under reflow conditions, and one which is
substantially non-collapsible under reflow conditions. The
non-collapsible portion is attached to the interconnect site on the
die. Typical materials for the non-collapsible portion include
various solders having a high Pd content. Typical materials for the
collapsible portion of the composite bump include eutectic solders.
The collapsible portion is joined to the non-collapsible portion,
and it is the collapsible portion that makes the connection with
the interconnect site.
[0077] FIGS. 11-14 describe other embodiments with various
interconnect structures applicable to the interconnect structure,
as described in FIGS. 8-10. FIG. 11a shows a semiconductor wafer
220 with a base substrate material 222, such as silicon, germanium,
gallium arsenide, indium phosphide, or silicon carbide, for
structural support. A plurality of semiconductor die or components
224 is formed on wafer 220 separated by saw streets 226 as
described above.
[0078] FIG. 11b shows a cross-sectional view of a portion of
semiconductor wafer 220. Each semiconductor die 224 has a back
surface 228 and active surface 230 containing analog or digital
circuits implemented as active devices, passive devices, conductive
layers, and dielectric layers formed within the die and
electrically interconnected according to the electrical design and
function of the die. For example, the circuit can include one or
more transistors, diodes, and other circuit elements formed within
active surface 230 to implement analog circuits or digital
circuits, such as digital signal processor (DSP), ASIC, memory, or
other signal processing circuit. Semiconductor die 224 can also
contain integrated passive devices (IPDs), such as inductors,
capacitors, and resistors, for RF signal processing. In one
embodiment, semiconductor die 224 is a flipchip type semiconductor
die.
[0079] An electrically conductive layer 232 is formed over active
surface 230 using PVD, CVD, electrolytic plating, electroless
plating process, or other suitable metal deposition process.
Conductive layer 232 can be one or more layers of Al, Cu, Sn, Ni,
Au, Ag, or other suitable electrically conductive material.
Conductive layer 232 operates as contact pads electrically
connected to the circuits on active surface 230.
[0080] FIG. 11c shows a portion of semiconductor wafer 220 with an
interconnect structure formed over contact pads 232. An
electrically conductive bump material 234 is deposited over contact
pads 232 using an evaporation, electrolytic plating, electroless
plating, ball drop, or screen printing process. Bump material 234
can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations
thereof, with an optional flux solution. For example, bump material
234 can be eutectic Sn/Pb, high-lead solder, or lead-free solder.
Bump material 234 is generally compliant and undergoes plastic
deformation greater than about 25 .mu.m under a force equivalent to
a vertical load of about 200 grams. Bump material 234 is bonded to
contact pad 232 using a suitable attachment or bonding process. For
example, bump material 234 can be compression bonded to contact pad
232. Bump material 234 can also be reflowed by heating the material
above its melting point to form spherical balls or bumps 236, as
shown in FIG. 11d. In some applications, bumps 236 are reflowed a
second time to improve electrical connection to contact pad 232.
Bumps 236 represent one type of interconnect structure that can be
formed over contact pad 232. The interconnect structure can also
use stud bump, micro bump, or other electrical interconnect.
[0081] FIG. 11e shows another embodiment of the interconnect
structure formed over contact pads 232 as composite bumps 238
including a non-fusible or non-collapsible portion 240 and fusible
or collapsible portion 242. The fusible or collapsible and
non-fusible or non-collapsible attributes are defined for bumps 238
with respect to reflow conditions. The non-fusible portion 240 can
be Au, Cu, Ni, high-lead solder, or lead-tin alloy. The fusible
portion 242 can be Sn, lead-free alloy, Sn-Ag alloy, Sn-Ag-Cu
alloy, Sn-Ag-indium (In) alloy, eutectic solder, tin alloys with
Ag, Cu, or Pb, or other relatively low temperature melt solder. In
one embodiment, given a contact pad 232 width or diameter of 100
.mu.m, the non-fusible portion 240 is about 45 .mu.m in height and
fusible portion 242 is about 35 .mu.m in height.
[0082] FIG. 11f shows another embodiment of the interconnect
structure formed over contact pads 232 as bump 244 over conductive
pillar 246. Bump 244 is fusible or collapsible and conductive
pillar 246 is non-fusible or non-collapsible. The fusible or
collapsible and non-fusible or non-collapsible attributes are
defined with respect to reflow conditions. Bump 244 can be Sn,
lead-free alloy, Sn-Ag alloy, Sn-Ag-Cu alloy, Sn-Ag-In alloy,
eutectic solder, tin alloys with Ag, Cu, or Pb, or other relatively
low temperature melt solder. Conductive pillar 246 can be Au, Cu,
Ni, high-lead solder, or lead-tin alloy. In one embodiment,
conductive pillar 246 is a Cu pillar and bump 244 is a solder cap.
Given a contact pad 232 width or diameter of 100 .mu.m, conductive
pillar 246 is about 45 .mu.m in height and bump 244 is about 35
.mu.m in height.
[0083] FIG. 11g shows another embodiment of the interconnect
structure formed over contact pads 232 as bump material 248 with
asperities 250. Bump material 248 is soft and deformable under
reflow conditions with a low yield strength and high elongation to
failure, similar to bump material 234. Asperities 250 are formed
with a plated surface finish and are shown exaggerated in the
figures for purposes of illustration. The scale of asperities 250
is generally in the order about 1-25 .mu.m. The asperities can also
be formed on bump 236, composite bump 238, and bump 244.
[0084] In FIG. 11h, semiconductor wafer 220 is singulated through
saw street 226 using a saw blade or laser cutting tool 252 into
individual semiconductor die 224.
[0085] FIG. 12a shows a substrate or PCB 254 with conductive trace
256. Substrate 254 can be a single-sided FR5 laminate or 2-sided
BT-resin laminate. Semiconductor die 224 is positioned so that bump
material 234 is aligned with an interconnect site on conductive
trace 256, see FIGS. 20a-20g. Alternatively, bump material 234 can
be aligned with a conductive pad or other interconnect site formed
on substrate 254. Bump material 234 is wider than conductive trace
256. In one embodiment, bump material 234 has a width of less than
100 .mu.m and conductive trace or pad 256 has a width of 35 .mu.m
for a bump pitch of 150 .mu.m. Conductive traces 256 are applicable
to the interconnect structure, as described in FIGS. 8-10.
[0086] A pressure or force F is applied to back surface 228 of
semiconductor die 224 to press bump material 234 onto conductive
trace 256. The force F can be applied with an elevated temperature.
Due to the compliant nature of bump material 234, the bump material
deforms or extrudes around the top surface and side surface of
conductive trace 256, referred to as BOL. In particular, the
application of pressure causes bump material 234 to undergo a
plastic deformation greater than about 25 .mu.m under force F
equivalent to a vertical load of about 200 grams and cover the top
surface and side surface of the conductive trace, as shown in FIG.
12b. Bump material 234 can also be metallurgically connected to
conductive trace 256 by bringing the bump material in physical
contact with the conductive trace and then reflowing the bump
material under a reflow temperature.
[0087] By making conductive trace 256 narrower than bump material
234, the conductive trace pitch can be reduced to increase routing
density and I/O count. The narrower conductive trace 256 reduces
the force F needed to deform bump material 234 around the
conductive trace. For example, the requisite force F may be 30-50%
of the force needed to deform bump material against a conductive
trace or pad that is wider than the bump material. The lower
compressive force F is useful for fine pitch interconnect and small
die to maintain coplanarity with a specified tolerance and achieve
uniform z-direction deformation and high reliability interconnect
union. In addition, deforming bump material 234 around conductive
trace 256 mechanically locks the bump to the trace to prevent die
shifting or die floating during reflow.
[0088] FIG. 12c shows bump 236 formed over contact pad 232 of
semiconductor die 224. Semiconductor die 224 is positioned so that
bump 236 is aligned with an interconnect site on conductive trace
256. Alternatively, bump 236 can be aligned with a conductive pad
or other interconnect site formed on substrate 254. Bump 236 is
wider than conductive trace 256. Conductive traces 256 are
applicable to the interconnect structure, as described in FIGS.
8-10.
[0089] A pressure or force F is applied to back surface 228 of
semiconductor die 224 to press bump 236 onto conductive trace 256.
The force F can be applied with an elevated temperature. Due to the
compliant nature of bump 236, the bump deforms or extrudes around
the top surface and side surface of conductive trace 256. In
particular, the application of pressure causes bump material 236 to
undergo a plastic deformation and cover the top surface and side
surface of conductive trace 256. Bump 236 can also be
metallurgically connected to conductive trace 256 by bringing the
bump in physical contact with the conductive trace under reflow
temperature.
[0090] By making conductive trace 256 narrower than bump 236, the
conductive trace pitch can be reduced to increase routing density
and I/O count. The narrower conductive trace 256 reduces the force
F needed to deform bump 236 around the conductive trace. For
example, the requisite force F may be 30-50% of the force needed to
deform a bump against a conductive trace or pad that is wider than
the bump. The lower compressive force F is useful for fine pitch
interconnect and small die to maintain coplanarity within a
specified tolerance and achieve uniform z-direction deformation and
high reliability interconnect union. In addition, deforming bump
236 around conductive trace 256 mechanically locks the bump to the
trace to prevent die shifting or die floating during reflow.
[0091] FIG. 12d shows composite bump 238 formed over contact pad
232 of semiconductor die 224. Semiconductor die 224 is positioned
so that composite bump 238 is aligned with an interconnect site on
conductive trace 256. Alternatively, composite bump 238 can be
aligned with a conductive pad or other interconnect site formed on
substrate 254. Composite bump 238 is wider than conductive trace
256. Conductive traces 256 are applicable to the interconnect
structure, as described in FIGS. 8-10.
[0092] A pressure or force F is applied to back surface 228 of
semiconductor die 224 to press fusible portion 242 onto conductive
trace 256. The force F can be applied with an elevated temperature.
Due to the compliant nature of fusible portion 242, the fusible
portion deforms or extrudes around the top surface and side surface
of conductive trace 256. In particular, the application of pressure
causes fusible portion 242 to undergo a plastic deformation and
cover the top surface and side surface of conductive trace 256.
Composite bump 238 can also be metallurgically connected to
conductive trace 256 by bringing fusible portion 242 in physical
contact with the conductive trace under reflow temperature. The
non-fusible portion 240 does not melt or deform during the
application of pressure or temperature and retains its height and
shape as a vertical standoff between semiconductor die 224 and
substrate 254. The additional displacement between semiconductor
die 224 and substrate 254 provides greater coplanarity tolerance
between the mating surfaces.
[0093] During a reflow process, a large number (e.g., thousands) of
composite bumps 238 on semiconductor die 224 are attached to
interconnect sites on conductive trace 256 of substrate 254. Some
of the bumps 238 may fail to properly connect to conductive trace
256, particularly if die 224 is warped. Recall that composite bump
238 is wider than conductive trace 256. With a proper force
applied, the fusible portion 242 deforms or extrudes around the top
surface and side surface of conductive trace 256 and mechanically
locks composite bump 238 to the conductive trace. The mechanical
interlock is formed by nature of the fusible portion 242 being
softer and more compliant than conductive trace 256 and therefore
deforming over the top surface and around the side surface of the
conductive trace for greater contact surface area. The mechanical
interlock between composite bump 238 and conductive trace 256 holds
the bump to the conductive trace during reflow, i.e., the bump and
conductive trace do not lose contact. Accordingly, composite bump
238 mating to conductive trace 256 reduces bump interconnect
failures.
[0094] FIG. 12e shows conductive pillar 246 and bump 244 formed
over contact pad 232 of semiconductor die 224. Semiconductor die
224 is positioned so that bump 244 is aligned with an interconnect
site on conductive trace 256. Alternatively, bump 244 can be
aligned with a conductive pad or other interconnect site formed on
substrate 254. Bump 244 is wider than conductive trace 256.
Conductive traces 256 are applicable to the interconnect structure,
as described in FIGS. 8-10.
[0095] A pressure or force F is applied to back surface 228 of
semiconductor die 224 to press bump 244 onto conductive trace 256.
The force F can be applied with an elevated temperature. Due to the
compliant nature of bump 244, the bump deforms or extrudes around
the top surface and side surface of conductive trace 256. In
particular, the application of pressure causes bump 244 to undergo
a plastic deformation and cover the top surface and side surface of
conductive trace 256. Conductive pillar 246 and bump 244 can also
be metallurgically connected to conductive trace 256 by bringing
the bump in physical contact with the conductive trace under reflow
temperature. Conductive pillar 246 does not melt or deform during
the application of pressure or temperature and retains its height
and shape as a vertical standoff between semiconductor die 224 and
substrate 254. The additional displacement between semiconductor
die 224 and substrate 254 provides greater coplanarity tolerance
between the mating surfaces. The wider bump 244 and narrower
conductive trace 256 have similar low requisite compressive force
and mechanical locking features and advantages described above for
bump material 234 and bump 236.
[0096] FIG. 12f shows bump material 248 with asperities 250 formed
over contact pad 232 of semiconductor die 224. Semiconductor die
224 is positioned so that bump material 248 is aligned with an
interconnect site on conductive trace 256. Alternatively, bump
material 248 can be aligned with a conductive pad or other
interconnect site formed on substrate 254. Bump material 248 is
wider than conductive trace 256. A pressure or force F is applied
to back surface 228 of semiconductor die 224 to press bump material
248 onto conductive trace 256. The force F can be applied with an
elevated temperature. Due to the compliant nature of bump material
248, the bump deforms or extrudes around the top surface and side
surface of conductive trace 256. In particular, the application of
pressure causes bump material 248 to undergo a plastic deformation
and cover the top surface and side surface of conductive trace 256.
In addition, asperities 250 are metallurgically connected to
conductive trace 256. Asperities 250 are sized on the order about
1-25 .mu.m.
[0097] FIG. 12g shows a substrate or PCB 258 with trapezoidal
conductive trace 260 having angled or sloped sides. Bump material
261 is formed over contact pad 232 of semiconductor die 224.
Semiconductor die 224 is positioned so that bump material 261 is
aligned with an interconnect site on conductive trace 260.
Alternatively, bump material 261 can be aligned with a conductive
pad or other interconnect site formed on substrate 258. Bump
material 261 is wider than conductive trace 260. Conductive traces
260 are applicable to the interconnect structure, as described in
FIGS. 8-10.
[0098] A pressure or force F is applied to back surface 228 of
semiconductor die 224 to press bump material 261 onto conductive
trace 260. The force F can be applied with an elevated temperature.
Due to the compliant nature of bump material 261, the bump material
deforms or extrudes around the top surface and side surface of
conductive trace 260. In particular, the application of pressure
causes bump material 261 to undergo a plastic deformation under
force F to cover the top surface and the angled side surface of
conductive trace 260. Bump material 261 can also be metallurgically
connected to conductive trace 260 by bringing the bump material in
physical contact with the conductive trace and then reflowing the
bump material under a reflow temperature.
[0099] FIGS. 13a-13d show a BOL embodiment of semiconductor die 224
and elongated composite bump 262 having a non-fusible or
non-collapsible portion 264 and fusible or collapsible portion 266.
The non-fusible portion 264 can be Au, Cu, Ni, high-lead solder, or
lead-tin alloy. The fusible portion 266 can be Sn, lead-free alloy,
Sn-Ag alloy, Sn-Ag-Cu alloy, Sn-Ag-In alloy, eutectic solder, tin
alloys with Ag, Cu, or Pb, or other relatively low temperature melt
solder. The non-fusible portion 264 makes up a larger part of
composite bump 262 than the fusible portion 266. The non-fusible
portion 264 is fixed to contact pad 232 of semiconductor die
224.
[0100] Semiconductor die 224 is positioned so that composite bump
262 is aligned with an interconnect site on conductive trace 268
formed on substrate 270, as shown in FIG. 13a. Composite bump 262
is tapered along conductive trace 268, i.e., the composite bump has
a wedge shape, longer along a length of conductive trace 268 and
narrower across the conductive trace. The tapered aspect of
composite bump 262 occurs along the length of conductive trace 268.
The view in FIG. 13a shows the shorter aspect or narrowing taper
co-linear with conductive trace 268. The view in FIG. 13b, normal
to FIG. 13a, shows the longer aspect of the wedge-shaped composite
bump 262. The shorter aspect of composite bump 262 is wider than
conductive trace 268. The fusible portion 266 collapses around
conductive trace 268 upon application of pressure and/or reflow
with heat, as shown in FIGS. 13c and 13d. The non-fusible portion
264 does not melt or deform during reflow and retains its form and
shape. The non-fusible portion 264 can be dimensioned to provide a
standoff distance between semiconductor die 224 and substrate 270.
A finish such as Cu OSP can be applied to substrate 270. Conductive
traces 268 are applicable to the interconnect structure, as
described in FIGS. 8-10.
[0101] During a reflow process, a large number (e.g., thousands) of
composite bumps 262 on semiconductor die 224 are attached to
interconnect sites on conductive trace 268 of substrate 270. Some
of the bumps 262 may fail to properly connect to conductive trace
268, particularly if semiconductor die 224 is warped. Recall that
composite bump 262 is wider than conductive trace 268. With a
proper force applied, the fusible portion 266 deforms or extrudes
around the top surface and side surface of conductive trace 268 and
mechanically locks composite bump 262 to the conductive trace. The
mechanical interlock is formed by nature of the fusible portion 266
being softer and more compliant than conductive trace 268 and
therefore deforming around the top surface and side surface of the
conductive trace for greater contact area. The wedge-shape of
composite bump 262 increases contact area between the bump and
conductive trace, e.g., along the longer aspect of FIGS. 13b and
13d, without sacrificing pitch along the shorter aspect of FIGS.
13a and 13c. The mechanical interlock between composite bump 262
and conductive trace 268 holds the bump to the conductive trace
during reflow, i.e., the bump and conductive trace do not lose
contact. Accordingly, composite bump 262 mating to conductive trace
268 reduces bump interconnect failures.
[0102] FIGS. 14a-14d show a BOL embodiment of semiconductor die 224
with bump material 274 formed over contact pads 232, similar to
FIG. 11c. In FIG. 14a, bump material 274 is generally compliant and
undergoes plastic deformation greater than about 25 .mu.m under a
force equivalent to a vertical load of about 200 grams. Bump
material 274 is wider than conductive trace 276 on substrate 278. A
plurality of asperities 280 is formed on conductive trace 276 with
a height on the order about 1-25 .mu.m.
[0103] Semiconductor die 224 is positioned so that bump material
274 is aligned with an interconnect site on conductive trace 276.
Alternatively, bump material 274 can be aligned with a conductive
pad or other interconnect site formed on substrate 278. A pressure
or force F is applied to back surface 228 of semiconductor die 224
to press bump material 274 onto conductive trace 276 and asperities
280, as shown in FIG. 14b. The force F can be applied with an
elevated temperature. Due to the compliant nature of bump material
274, the bump material deforms or extrudes around the top surface
and side surface of conductive trace 276 and asperities 280. In
particular, the application of pressure causes bump material 274 to
undergo a plastic deformation and cover the top surface and side
surface of conductive trace 276 and asperities 280. The plastic
flow of bump material 274 creates macroscopic mechanical
interlocking points between the bump material and the top surface
and side surface of conductive trace 276 and asperities 280. The
plastic flow of bump material 274 occurs around the top surface and
side surface of conductive trace 276 and asperities 280, but does
not extend excessively onto substrate 278, which could cause
electrical shorting and other defects. The mechanical interlock
between the bump material and the top surface and side surface of
conductive trace 276 and asperities 280 provides a robust
connection with greater contact area between the respective
surfaces, without significantly increasing the bonding force. The
mechanical interlock between the bump material and the top surface
and side surface of conductive trace 276 and asperities 280 also
reduces lateral die shifting during subsequent manufacturing
processes, such as encapsulation.
[0104] FIG. 14c shows another BOL embodiment with bump material 274
narrower than conductive trace 276. A pressure or force F is
applied to back surface 228 of semiconductor die 224 to press bump
material 274 onto conductive trace 276 and asperities 280. The
force F can be applied with an elevated temperature. Due to the
compliant nature of bump material 274, the bump material deforms or
extrudes over the top surface of conductive trace 276 and
asperities 280. In particular, the application of pressure causes
bump material 274 to undergo a plastic deformation and cover the
top surface of conductive trace 276 and asperities 280. The plastic
flow of bump material 274 creates macroscopic mechanical
interlocking points between the bump material and the top surface
of conductive trace 276 and asperities 280. The mechanical
interlock between the bump material and the top surface of
conductive trace 276 and asperities 280 provides a robust
connection with greater contact area between the respective
surfaces, without significantly increasing the bonding force. The
mechanical interlock between the bump material and the top surface
of conductive trace 276 and asperities 280 also reduces lateral die
shifting during subsequent manufacturing processes, such as
encapsulation.
[0105] FIG. 14d shows another BOL embodiment with bump material 274
formed over an edge of conductive trace 276, i.e., part of the bump
material is over the conductive trace and part of the bump material
is not over the conductive trace. A pressure or force F is applied
to back surface 228 of semiconductor die 224 to press bump material
274 onto conductive trace 276 and asperities 280. The force F can
be applied with an elevated temperature. Due to the compliant
nature of bump material 274, the bump material deforms or extrudes
over the top surface and side surface of conductive trace 276 and
asperities 280. In particular, the application of pressure causes
bump material 274 to undergo a plastic deformation and cover the
top surface and side surface of conductive trace 276 and asperities
280. The plastic flow of bump material 274 creates macroscopic
mechanical interlocking between the bump material and the top
surface and side surface of conductive trace 276 and asperities
280. The mechanical interlock between the bump material and the top
surface and side surface of conductive trace 276 and asperities 280
provides a robust connection with greater contact area between the
respective surfaces, without significantly increasing the bonding
force. The mechanical interlock between the bump material and the
top surface and side surface of conductive trace 276 and asperities
280 also reduces lateral die shifting during subsequent
manufacturing processes, such as encapsulation.
[0106] FIGS. 15a-15c show a BOL embodiment of semiconductor die 224
with bump material 284 formed over contact pads 232, similar to
FIG. 11c. A tip 286 extends from the body of bump material 284 as a
stepped bump with tip 286 narrower than the body of bump material
284, as shown in FIG. 15a. Semiconductor die 224 is positioned so
that bump material 284 is aligned with an interconnect site on
conductive trace 288 on substrate 290. More specifically, tip 286
is centered over an interconnect site on conductive trace 288.
Alternatively, bump material 284 and tip 286 can be aligned with a
conductive pad or other interconnect site formed on substrate 290.
Bump material 284 is wider than conductive trace 288 on substrate
290.
[0107] Conductive trace 288 is generally compliant and undergoes
plastic deformation greater than about 25 .mu.m under a force
equivalent to a vertical load of about 200 grams. A pressure or
force F is applied to back surface 228 of semiconductor die 224 to
press tip 284 onto conductive trace 288. The force F can be applied
with an elevated temperature. Due to the compliant nature of
conductive trace 288, the conductive trace deforms around tip 286,
as shown in FIG. 15b. In particular, the application of pressure
causes conductive trace 288 to undergo a plastic deformation and
cover the top surface and side surface of tip 286.
[0108] FIG. 15c shows another BOL embodiment with rounded bump
material 294 formed over contact pads 232. A tip 296 extends from
the body of bump material 294 to form a stud bump with the tip
narrower than the body of bump material 294. Semiconductor die 224
is positioned so that bump material 294 is aligned with an
interconnect site on conductive trace 298 on substrate 300. More
specifically, tip 296 is centered over an interconnect site on
conductive trace 298. Alternatively, bump material 294 and tip 296
can be aligned with a conductive pad or other interconnect site
formed on substrate 300. Bump material 294 is wider than conductive
trace 298 on substrate 300.
[0109] Conductive trace 298 is generally compliant and undergoes
plastic deformation greater than about 25 .mu.m under a force
equivalent to a vertical load of about 200 grams. A pressure or
force F is applied to back surface 228 of semiconductor die 224 to
press tip 296 onto conductive trace 298. The force F can be applied
with an elevated temperature. Due to the compliant nature of
conductive trace 298, the conductive trace deforms around tip 296.
In particular, the application of pressure causes conductive trace
298 to undergo a plastic deformation and cover the top surface and
side surface of tip 296.
[0110] The conductive traces described in FIGS. 12a-12g, 13a-13d,
and 14a-14d can also be compliant material as described in FIGS.
15a-15c.
[0111] FIGS. 16a-16b show a BOL embodiment of semiconductor die 224
with bump material 304 formed over contact pads 232, similar to
FIG. 11c. Bump material 304 is generally compliant and undergoes
plastic deformation greater than about 25 .mu.m under a force
equivalent to a vertical load of about 200 grams. Bump material 304
is wider than conductive trace 306 on substrate 308. A conductive
via 310 is formed through conductive trace 306 with an opening 312
and conductive sidewalls 314, as shown in FIG. 16a. Conductive
traces 306 are applicable to the interconnect structure, as
described in FIGS. 8-10.
[0112] Semiconductor die 224 is positioned so that bump material
304 is aligned with an interconnect site on conductive trace 306,
see FIGS. 20a-20g. Alternatively, bump material 304 can be aligned
with a conductive pad or other interconnect site formed on
substrate 308. A pressure or force F is applied to back surface 228
of semiconductor die 224 to press bump material 304 onto conductive
trace 306 and into opening 312 of conductive via 310. The force F
can be applied with an elevated temperature. Due to the compliant
nature of bump material 304, the bump material deforms or extrudes
around the top surface and side surface of conductive trace 306 and
into opening 312 of conductive vias 310, as shown in FIG. 16b. In
particular, the application of pressure causes bump material 304 to
undergo a plastic deformation and cover the top surface and side
surface of conductive trace 306 and into opening 312 of conductive
via 310. Bump material 304 is thus electrically connected to
conductive trace 306 and conductive sidewalls 314 for z-direction
vertical interconnect through substrate 308. The plastic flow of
bump material 304 creates a mechanical interlock between the bump
material and the top surface and side surface of conductive trace
306 and opening 312 of conductive via 310.
[0113] The mechanical interlock between the bump material and the
top surface and side surface of conductive trace 306 and opening
312 of conductive via 310 provides a robust connection with greater
contact area between the respective surfaces, without significantly
increasing the bonding force. The mechanical interlock between the
bump material and the top surface and side surface of conductive
trace 306 and opening 312 of conductive via 310 also reduces
lateral die shifting during subsequent manufacturing processes,
such as encapsulation. Since conductive via 310 is formed within
the interconnect site with bump material 304, the total substrate
interconnect area is reduced.
[0114] In the BOL embodiments of FIGS. 12a-12g, 13a-13d, 14a-14d,
15a-15c, and 16a-16b, by making the conductive trace narrower than
the interconnect structure, the conductive trace pitch can be
reduced to increase routing density and I/O count. The narrower
conductive trace reduces the force F needed to deform the
interconnect structure around the conductive trace. For example,
the requisite force F may be 30-50% of the force needed to deform a
bump against a conductive trace or pad that is wider than the bump.
The lower compressive force F is useful for fine pitch interconnect
and small die to maintain coplanarity within a specified tolerance
and achieve uniform z-direction deformation and high reliability
interconnect union. In addition, deforming the interconnect
structure around the conductive trace mechanically locks the bump
to the trace to prevent die shifting or die floating during
reflow.
[0115] FIGS. 17a-17c show a mold underfill (MUF) process to deposit
encapsulant around the bumps between the semiconductor die and
substrate. FIG. 17a shows semiconductor die 224 mounted to
substrate 254 using bump material 234 from FIG. 12b and placed
between upper mold support 316 and lower mold support 318 of chase
mold 320. The other semiconductor die and substrate combinations
from FIGS. 12a-12g, 13a-13d, 14a-14d, 15a-15c, and 16a-16b can be
placed between upper mold support 316 and lower mold support 318 of
chase mold 320. The upper mold support 316 includes compressible
releasing film 322.
[0116] In FIG. 17b, upper mold support 316 and lower mold support
318 are brought together to enclose semiconductor die 224 and
substrate 254 with an open space over the substrate and between the
semiconductor die and substrate. Compressible releasing film 322
conforms to back surface 228 and side surface of semiconductor die
224 to block formation of encapsulant on these surfaces. An
encapsulant 324 in a liquid state is injected into one side of
chase mold 320 with nozzle 326 while an optional vacuum assist 328
draws pressure from the opposite side to uniformly fill the open
space over substrate 254 and the open space between semiconductor
die 224 and substrate 254 with the encapsulant. Encapsulant 324 can
be polymer composite material, such as epoxy resin with filler,
epoxy acrylate with filler, or polymer with proper filler.
Encapsulant 324 is non-conductive and environmentally protects the
semiconductor device from external elements and contaminants.
Compressible material 322 prevents encapsulant 324 from flowing
over back surface 228 and around the side surface of semiconductor
die 224. Encapsulant 324 is cured. The back surface 228 and side
surface of semiconductor die 224 remain exposed from encapsulant
324.
[0117] FIG. 17c shows an embodiment of MUF and mold overfill (MOF),
i.e., without compressible material 322. Semiconductor die 224 and
substrate 254 are placed between upper mold support 316 and lower
mold support 318 of chase mold 320. The upper mold support 316 and
lower mold support 318 are brought together to enclose
semiconductor die 224 and substrate 254 with an open space over the
substrate, around the semiconductor die, and between the
semiconductor die and substrate. Encapsulant 324 in a liquid state
is injected into one side of chase mold 320 with nozzle 326 while
an optional vacuum assist 328 draws pressure from the opposite side
to uniformly fill the open space around semiconductor die 224 and
over substrate 254 and the open space between semiconductor die 224
and substrate 254 with the encapsulant. Encapsulant 324 is
cured.
[0118] FIG. 18 shows another embodiment of depositing encapsulant
around semiconductor die 224 and in the gap between semiconductor
die 224 and substrate 254. Semiconductor die 224 and substrate 254
are enclosed by dam 330. Encapsulant 332 is dispensed from nozzles
334 in a liquid state into dam 330 to fill the open space over
substrate 254 and the open space between semiconductor die 224 and
substrate 254. The volume of encapsulant 332 dispensed from nozzles
334 is controlled to fill dam 330 without covering back surface 228
or the side surface of semiconductor die 224. Encapsulant 332 is
cured.
[0119] FIG. 19 shows semiconductor die 224 and substrate 254 after
the MUF process from FIGS. 17a, 17c, and 18. Encapsulant 324 is
uniformly distributed over substrate 254 and around bump material
234 between semiconductor die 224 and substrate 254.
[0120] FIGS. 20a-20g show top views of various conductive trace
layouts on substrate or PCB 340. In FIG. 20a, conductive trace 342
is a straight conductor with integrated bump pad or interconnect
site 344 formed on substrate 340. The sides of substrate bump pad
344 can be co-linear with conductive trace 342. In the prior art, a
solder registration opening (SRO) is typically formed over the
interconnect site to contain the bump material during reflow. The
SRO increases interconnect pitch and reduces I/O count. In
contrast, masking layer 346 can be formed over a portion of
substrate 340; however, the masking layer is not formed around
substrate bump pad 344 of conductive trace 342. That is, the
portion of conductive trace 342 designed to mate with the bump
material is devoid of any SRO of masking layer 346 that would have
been used for bump containment during reflow.
[0121] Semiconductor die 224 is placed over substrate 340 and the
bump material is aligned with substrate bump pads 344. The bump
material is electrically and metallurgically connected to substrate
bump pads 344 by bringing the bump material in physical contact
with the bump pad and then reflowing the bump material under a
reflow temperature.
[0122] In another embodiment, an electrically conductive bump
material is deposited over substrate bump pad 344 using an
evaporation, electrolytic plating, electroless plating, ball drop,
or screen printing process. The bump material can be Al, Sn, Ni,
Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an
optional flux solution. For example, the bump material can be
eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump
material is bonded to substrate bump pad 344 using a suitable
attachment or bonding process. In one embodiment, the bump material
is reflowed by heating the material above its melting point to form
bump or interconnect 348, as shown in FIG. 20b. In some
applications, bump 348 is reflowed a second time to improve
electrical contact to substrate bump pad 344. The bump material
around the narrow substrate bump pad 344 maintains die placement
during reflow.
[0123] In high routing density applications, it is desirable to
minimize escape pitch of conductive traces 342. The escape pitch
between conductive traces 342 can be reduced by eliminating the
masking layer for the purpose of reflow containment, i.e., by
reflowing the bump material without a masking layer. Since no SRO
is formed around die bump pad 232 or substrate bump pad 344,
conductive traces 342 can be formed with a finer pitch, i.e.,
conductive trace 342 can be disposed closer together or to nearby
structures. With no SRO around substrate bump pad 344, the pitch
between conductive traces 342 is given as P=D+PLT+W/2, wherein D is
the base diameter of bump 348, PLT is die placement tolerance, and
W is the width of conductive trace 342. In one embodiment, given a
bump base diameter of 100 .mu.m, PLT of 10 .mu.m, and trace line
width of 30 .mu.m, the minimum escape pitch of conductive trace 342
is 125 .mu.m. The mask-less bump formation eliminates the need to
account for the ligament spacing of masking material between
adjacent openings, solder mask registration tolerance (SRT), and
minimum resolvable SRO, as found in the prior art.
[0124] When the bump material is reflowed without a masking layer
to metallurgically and electrically connect die bump pad 232 to
substrate bump pad 344, the wetting and surface tension causes the
bump material to maintain self-confinement and be retained within
the space between die bump pad 232 and substrate bump pad 344 and
portion of substrate 340 immediately adjacent to conductive trace
342 substantially within the footprint of the bump pads.
[0125] To achieve the desired self-confinement property, the bump
material can be immersed in a flux solution prior to placement on
die bump pad 232 or substrate bump pad 344 to selectively render
the region contacted by the bump material more wettable than the
surrounding area of conductive traces 342. The molten bump material
remains confined substantially within the area defined by the bump
pads due to the wettable properties of the flux solution. The bump
material does not run-out to the less wettable areas. A thin oxide
layer or other insulating layer can be formed over areas where bump
material is not intended to make the area less wettable. Hence,
masking layer 340 is not needed around die bump pad 232 or
substrate bump pad 344.
[0126] FIG. 20c shows another embodiment of parallel conductive
traces 352 as a straight conductor with integrated rectangular bump
pad or interconnect site 354 formed on substrate 350. In this case,
substrate bump pad 354 is wider than conductive trace 352, but less
than the width of the mating bump. The sides of substrate bump pad
354 can be parallel to conductive trace 352. Masking layer 356 can
be formed over a portion of substrate 350; however, the masking
layer is not formed around substrate bump pad 354 of conductive
trace 352. That is, the portion of conductive trace 352 designed to
mate with the bump material is devoid of any SRO of masking layer
356 that would have been used for bump containment during
reflow.
[0127] FIG. 20d shows another embodiment of conductive traces 360
and 362 arranged in an array of multiple rows with offset
integrated bump pad or interconnect site 364 formed on substrate
366 for maximum interconnect escape routing density and capacity.
Alternate conductive traces 360 and 362 include an elbow for
routing to bump pads 364. The sides of each substrate bump pad 364
is co-linear with conductive traces 360 and 362. Masking layer 368
can be formed over a portion of substrate 366; however, masking
layer 368 is not formed around substrate bump pad 364 of conductive
traces 360 and 362. That is, the portion of conductive trace 360
and 362 designed to mate with the bump material is devoid of any
SRO of masking layer 368 that would have been used for bump
containment during reflow.
[0128] FIG. 20e shows another embodiment of conductive traces 370
and 372 arranged in an array of multiple rows with offset
integrated bump pad or interconnect site 374 formed on substrate
376 for maximum interconnect escape routing density and capacity.
Alternate conductive traces 370 and 372 include an elbow for
routing to bump pads 374. In this case, substrate bump pad 374 is
rounded and wider than conductive traces 370 and 372, but less than
the width of the mating interconnect bump material. Masking layer
378 can be formed over a portion of substrate 376; however, masking
layer 378 is not formed around substrate bump pad 374 of conductive
traces 370 and 372. That is, the portion of conductive trace 370
and 372 designed to mate with the bump material is devoid of any
SRO of masking layer 378 that would have been used for bump
containment during reflow.
[0129] FIG. 20f shows another embodiment of conductive traces 380
and 382 arranged in an array of multiple rows with offset
integrated bump pad or interconnect site 384 formed on substrate
386 for maximum interconnect escape routing density and capacity.
Alternate conductive traces 380 and 382 include an elbow for
routing to bump pads 384. In this case, substrate bump pad 384 is
rectangular and wider than conductive traces 380 and 382, but less
than the width of the mating interconnect bump material. Masking
layer 388 can be formed over a portion of substrate 386; however,
masking layer 388 is not formed around substrate bump pad 384 of
conductive traces 380 and 382. That is, the portion of conductive
trace 380 and 382 designed to mate with the bump material is devoid
of any SRO of masking layer 388 that would have been used for bump
containment during reflow.
[0130] As one example of the interconnect process, semiconductor
die 224 is placed over substrate 366 and bump material 234 is
aligned with substrate bump pads 364 from FIG. 20d. Bump material
234 is electrically and metallurgically connected to substrate bump
pad 364 by pressing the bump material or by bringing the bump
material in physical contact with the bump pad and then reflowing
the bump material under a reflow temperature, as described for
FIGS. 12a-12g, 13a-13d, 14a-14d, 15a-15c, and 16a-16b.
[0131] In another embodiment, an electrically conductive bump
material is deposited over substrate bump pad 364 using an
evaporation, electrolytic plating, electroless plating, ball drop,
or screen printing process. The bump material can be Al, Sn, Ni,
Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an
optional flux solution. For example, the bump material can be
eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump
material is bonded to substrate bump pad 364 using a suitable
attachment or bonding process. In one embodiment, the bump material
is reflowed by heating the material above its melting point to form
bump or interconnect 390, as shown in FIG. 20g. In some
applications, bump 390 is reflowed a second time to improve
electrical contact to substrate bump pad 364. The bump material
around the narrow substrate bump pad 364 maintains die placement
during reflow. Bump material 234 or bumps 390 can also be formed on
substrate bump pad configurations of FIGS. 20a-20g.
[0132] In high routing density applications, it is desirable to
minimize escape pitch of conductive traces 360 and 362 or other
conductive trace configurations of FIGS. 20a-20g. The escape pitch
between conductive traces 360 and 362 can be reduced by eliminating
the masking layer for the purpose of reflow containment, i.e., by
reflowing the bump material without a masking layer. Since no SRO
is formed around die bump pad 232 or substrate bump pad 364,
conductive traces 360 and 362 can be formed with a finer pitch,
i.e., conductive traces 360 and 362 can be disposed closer together
or to nearby structures. With no SRO around substrate bump pad 364,
the pitch between conductive traces 360 and 362 is given as
P=D/2+PLT+W/2, wherein D is the base diameter of bump 390, PLT is
die placement tolerance, and W is the width of conductive traces
360 and 362. In one embodiment, given a bump base diameter of 100
.mu.m, PLT of 10 .mu.m, and trace line width of 30 .mu.m, the
minimum escape pitch of conductive traces 360 and 362 is 125 .mu.m.
The mask-less bump formation eliminates the need to account for the
ligament spacing of masking material between adjacent openings,
SRT, and minimum resolvable SRO, as found in the prior art.
[0133] When the bump material is reflowed without a masking layer
to metallurgically and electrically connect die bump pad 232 to
substrate bump pad 364, the wetting and surface tension causes the
bump material to maintain self-confinement and be retained within
the space between die bump pad 232 and substrate bump pad 364 and
portion of substrate 366 immediately adjacent to conductive traces
360 and 362 substantially within the footprint of the bump
pads.
[0134] To achieve the desired self-confinement property, the bump
material can be immersed in a flux solution prior to placement on
die bump pad 232 or substrate bump pad 364 to selectively render
the region contacted by the bump material more wettable than the
surrounding area of conductive traces 360 and 362. The molten bump
material remains confined substantially within the area defined by
the bump pads due to the wettable properties of the flux solution.
The bump material does not run-out to the less wettable areas. A
thin oxide layer or other insulating layer can be formed over areas
where bump material is not intended to make the area less wettable.
Hence, masking layer 368 is not needed around die bump pad 232 or
substrate bump pad 364.
[0135] In FIG. 21a, masking layer 392 is deposited over a portion
of conductive traces 394 and 396. However, masking layer 392 is not
formed over integrated bump pads 398. Consequently, there is no SRO
for each bump pad 398 on substrate 400. A non-wettable masking
patch 402 is formed on substrate 400 interstitially within the
array of integrated bump pads 398, i.e., between adjacent bump
pads. The masking patch 402 can also be formed on semiconductor die
224 interstitially within the array of die bump pads 398. More
generally, the masking patch is formed in close proximity to the
integrated bump pads in any arrangement to prevent run-out to less
wettable areas.
[0136] Semiconductor die 224 is placed over substrate 400 and the
bump material is aligned with substrate bump pads 398. The bump
material is electrically and metallurgically connected to substrate
bump pad 398 by pressing the bump material or by bringing the bump
material in physical contact with the bump pad and then reflowing
the bump material under a reflow temperature, as described for
FIGS. 12a-12g, 13a-13d, 14a-14d, 15a-15c, and 16a-16b.
[0137] In another embodiment, an electrically conductive bump
material is deposited over die integrated bump pads 398 using an
evaporation, electrolytic plating, electroless plating, ball drop,
or screen printing process. The bump material can be Al, Sn, Ni,
Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an
optional flux solution. For example, the bump material can be
eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump
material is bonded to integrated bump pads 398 using a suitable
attachment or bonding process. In one embodiment, the bump material
is reflowed by heating the material above its melting point to form
spherical balls or bumps 404, as shown in FIG. 21b. In some
applications, bumps 404 are reflowed a second time to improve
electrical contact to integrated bump pads 398. The bumps can also
be compression bonded to integrated bump pads 398. Bumps 404
represent one type of interconnect structure that can be formed
over integrated bump pads 398. The interconnect structure can also
use stud bump, micro bump, or other electrical interconnect.
[0138] In high routing density applications, it is desirable to
minimize escape pitch. In order to reduce the pitch between
conductive traces 394 and 396, the bump material is reflowed
without a masking layer around integrated bump pads 398. The escape
pitch between conductive traces 394 and 396 can be reduced by
eliminating the masking layer and associated SROs around the
integrated bump pads for the purpose of reflow containment, i.e.,
by reflowing the bump material without a masking layer. Masking
layer 392 can be formed over a portion of conductive traces 394 and
396 and substrate 400 away from integrated bump pads 398; however,
masking layer 392 is not formed around integrated bump pads 398.
That is, the portion of conductive trace 394 and 396 designed to
mate with the bump material is devoid of any SRO of masking layer
392 that would have been used for bump containment during
reflow.
[0139] In addition, masking patch 402 is formed on substrate 400
interstitially within the array of integrated bump pads 398.
Masking patch 402 is non-wettable material. Masking patch 402 can
be the same material as masking layer 392 and applied during the
same processing step, or a different material during a different
processing step. Masking patch 402 can be formed by selective
oxidation, plating, or other treatment of the portion of the trace
or pad within the array of integrated bump pads 398. Masking patch
402 confines bump material flow to integrated bump pads 398 and
prevents leaching of conductive bump material to adjacent
structures.
[0140] When the bump material is reflowed with masking patch 402
interstitially disposed within the array of integrated bump pads
398, the wetting and surface tension causes the bump material to be
confined and retained within the space between die bump pads 232
and integrated bump pads 398 and portion of substrate 400
immediately adjacent to conductive traces 394 and 396 and
substantially within the footprint of the integrated bump pads
398.
[0141] To achieve the desired confinement property, the bump
material can be immersed in a flux solution prior to placement on
die bump pads 232 or integrated bump pads 398 to selectively render
the region contacted by the bump material more wettable than the
surrounding area of conductive traces 394 and 396. The molten bump
material remains confined substantially within the area defined by
the bump pads due to the wettable properties of the flux solution.
The bump material does not run-out to the less wettable areas. A
thin oxide layer or other insulating layer can be formed over areas
where bump material is not intended to make the area less wettable.
Hence, masking layer 392 is not needed around die bump pads 232 or
integrated bump pads 398.
[0142] Since no SRO is formed around die bump pads 232 or
integrated bump pads 398, conductive traces 394 and 396 can be
formed with a finer pitch, i.e., the conductive traces can be
disposed closer to adjacent structures without making contact and
forming electrical shorts. Assuming the same solder registration
design rule, the pitch between conductive traces 394 and 396 is
given as P=(1.1D+W)/2, where D is the base diameter of bump 404 and
W is the width of conductive traces 394 and 396. In one embodiment,
given a bump diameter of 100 .mu.m and trace line width of 20
.mu.m, the minimum escape pitch of conductive traces 394 and 396 is
65 .mu.m. The bump formation eliminates the need to account for the
ligament spacing of masking material between adjacent openings and
minimum resolvable SRO, as found in the prior art.
[0143] FIG. 22 shows package-on-package (PoP) 405 with
semiconductor die 406 stacked over semiconductor die 408 using die
attach adhesive 410. Semiconductor die 406 and 408 each have an
active surface containing analog or digital circuits implemented as
active devices, passive devices, conductive layers, and dielectric
layers formed within the die and electrically interconnected
according to the electrical design and function of the die. For
example, the circuit can include one or more transistors, diodes,
and other circuit elements formed within the active surface to
implement analog circuits or digital circuits, such as DSP, ASIC,
memory, or other signal processing circuit. Semiconductor die 406
and 408 can also contain IPDs, such as inductors, capacitors, and
resistors, for RF signal processing.
[0144] Semiconductor die 406 is mounted to conductive traces 412
formed on substrate 414 using bump material 416 formed on contact
pads 418, using any of the embodiments from FIGS. 12a-12g, 13a-13d,
14a-14d, 15a-15c, and 16a-16b. Conductive traces 412 are applicable
to the interconnect structure, as described in FIGS. 8-10.
Semiconductor die 408 is electrically connected to contact pads 420
formed on substrate 414 using bond wires 422. The opposite end of
bond wire 422 is bonded to contact pads 424 on semiconductor die
406.
[0145] Masking layer 426 is formed over substrate 414 and opened
beyond the footprint of semiconductor die 406. While masking layer
426 does not confine bump material 416 to conductive traces 412
during reflow, the open mask can operate as a dam to prevent
encapsulant 428 from migrating to contact pads 420 or bond wires
422 during MUF. Encapsulant 428 is deposited between semiconductor
die 408 and substrate 414, similar to FIGS. 17a-17c. Masking layer
426 blocks MUF encapsulant 428 from reaching contact pads 420 and
bond wires 422, which could cause a defect. Masking layer 426
allows a larger semiconductor die to be placed on a given substrate
without risk of encapsulant 428 bleeding onto contact pads 420.
[0146] While one or more embodiments of the present invention have
been illustrated in detail, the skilled artisan will appreciate
that modifications and adaptations to those embodiments may be made
without departing from the scope of the present invention as set
forth in the following claims.
* * * * *