U.S. patent application number 13/409693 was filed with the patent office on 2012-07-05 for structure and method to improve threshold voltage of mosfets including a high k dielectric.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Sunfei Fang, Brian J. Greene, Effendi Leobandung, Qingqing Liang, Edward P. Maciejewski, Yanfeng Wang.
Application Number | 20120168874 13/409693 |
Document ID | / |
Family ID | 43534168 |
Filed Date | 2012-07-05 |
United States Patent
Application |
20120168874 |
Kind Code |
A1 |
Fang; Sunfei ; et
al. |
July 5, 2012 |
STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS
INCLUDING A HIGH K DIELECTRIC
Abstract
Threshold voltage controlled semiconductor structures are
provided in which a conformal nitride-containing liner is located
on at least exposed sidewalls of a patterned gate dielectric
material having a dielectric constant of greater than silicon
oxide. The conformal nitride-containing liner is a thin layer that
is formed using a low temperature (less than 500.degree. C.)
nitridation process.
Inventors: |
Fang; Sunfei;
(LaGrangeville, NY) ; Greene; Brian J.;
(Wappingers Falls, NY) ; Leobandung; Effendi;
(Wappingers Falls, NY) ; Liang; Qingqing;
(Fishkill, NY) ; Maciejewski; Edward P.;
(Wappingers Falls, NY) ; Wang; Yanfeng; (Fishkill,
NY) |
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
43534168 |
Appl. No.: |
13/409693 |
Filed: |
March 1, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12535183 |
Aug 4, 2009 |
8173531 |
|
|
13409693 |
|
|
|
|
Current U.S.
Class: |
257/369 ;
257/402; 257/E27.062; 257/E29.255 |
Current CPC
Class: |
H01L 21/823842 20130101;
H01L 21/823864 20130101; H01L 29/517 20130101; H01L 21/28247
20130101; H01L 29/66636 20130101; H01L 21/823857 20130101; H01L
29/6659 20130101 |
Class at
Publication: |
257/369 ;
257/402; 257/E27.062; 257/E29.255 |
International
Class: |
H01L 27/092 20060101
H01L027/092; H01L 29/78 20060101 H01L029/78 |
Claims
1. A semiconductor structure comprising: at least one patterned
gate stack in at least one device region of a semiconductor
substrate, said at least one patterned gate stack including from
bottom to top, a patterned gate dielectric material having a
dielectric constant of greater than silicon oxide and a patterned
gate conductor; and a conformal nitride-containing liner located on
at least exposed sidewalls of the patterned gate dielectric
material, said conformal nitride-containing liner having a
thickness of from 0.5 nm to 50 nm.
2. The semiconductor structure of claim 1 further including a
patterned threshold voltage adjusting layer between the patterned
gate dielectric and the patterned gate conductor, wherein said
patterned threshold voltage adjusting layer includes a pFET
threshold voltage adjusting material selected from Al,
Al.sub.2O.sub.3, Ge, GeO.sub.2, Ta, Ta.sub.2O.sub.5, Ti, and
TiO.sub.2.
3. The semiconductor structure of claim 1 further including a
patterned threshold voltage adjusting layer between the patterned
gate dielectric and the patterned gate conductor, wherein said
patterned threshold voltage adjusting layer is an nFET threshold
voltage adjusting material, said nFET threshold adjusting material
includes a rare earth metal-containing material or an alkaline
earth metal-containing material.
4. The semiconductor structure of claim 1 further comprising an
embedded semiconductor material having a different lattice constant
than the semiconductor substrate within the semiconductor substrate
at a footprint of the at least one patterned gate stacks.
5. The semiconductor structure of claim 1 wherein said conformal
nitride-containing liner has an upper surface that extends above an
upper surface of the patterned gate conductor of said at least one
patterned gate stack.
6. The semiconductor structure of claim 1 wherein said patterned
gate dielectric and said patterned gate conductor have sidewalls
that are vertically coincident.
7. The semiconductor structure of claim 1 wherein said conformal
nitride-containing liner has an upper surface that does not extend
above an upper surface of said patterned gate dielectric
material.
8. The semiconductor structure of claim 7 further comprising an
inner liner located on the upper surface of said conformal
nitride-containing liner, said inner liner having one vertical edge
in contact with a remaining vertical sidewall portion of said at
least one patterned gate stack.
9. The semiconductor structure of claim 8 further comprising an
oxide liner located on another vertical edge of said inner liner
and on an uppermost surface of said inner liner, but not in contact
with an outer vertical edge of said conformal nitride-containing
liner.
10. The semiconductor structure of claim 9 further comprising an
embedded semiconductor material having a different lattice constant
than the semiconductor substrate within the semiconductor substrate
at a footprint of the at least one patterned gate stacks.
11. A semiconductor structure comprising: a first patterned gate
stack in a first device region of a semiconductor substrate, and a
second patterned gate stack in a second device region of the
semiconductor substrate, wherein said first patterned gate stack
includes from bottom to top, a patterned gate dielectric material
having a dielectric constant of greater than silicon oxide and a
patterned gate conductor and said second patterned gate stack
includes from bottom to top, a patterned gate dielectric material
having a dielectric constant of greater than silicon oxide and a
patterned gate conductor; and a conformal nitride-containing liner
located on at least exposed sidewalls of the patterned gate
dielectric material in both device regions, the conformal
nitride-containing liner having a thickness of from 0.5 nm to 50
nm.
12. The semiconductor structure of claim 11 further comprising a
first patterned threshold voltage adjusting layer between the
patterned gate dielectric and the patterned gate conductor in the
first patterned gate stack and a second patterned threshold voltage
adjusting layer between the patterned gate dielectric and the
patterned gate conductor in the second patterned gate stack wherein
one of the first or second patterned threshold voltage adjusting
layers is a pFET threshold voltage adjusting material selected from
Al, Al.sub.2O.sub.3, Ge, GeO.sub.2, Ta, Ta.sub.2O.sub.5, Ti, and
TiO.sub.2.
13. The semiconductor structure of claim 12 wherein the other of
said first or second patterned threshold voltage adjusting layers
not including a pFET threshold voltage adjusting material is an
nFET threshold voltage adjusting material, said nFET threshold
adjusting material includes a rare earth metal-containing material
or an alkaline earth metal-containing material.
14. The semiconductor structure of claim 11 further comprising an
embedded semiconductor material having a different lattice constant
than the semiconductor substrate within the semiconductor substrate
at a footprint of one of the patterned gate stacks.
15. The semiconductor structure of claim 11 wherein said conformal
nitride-containing liner in both device regions has an upper
surface that extends above an upper surface of each patterned gate
conductor of said first and second patterned gate stacks.
16. The semiconductor structure of claim 11 wherein said patterned
gate dielectric and said patterned gate dielectric in each device
region have sidewalls that are vertically coincident.
17. The semiconductor structure of claim 11 wherein said conformal
nitride-containing liner in each device region has an upper surface
that does not extend above an upper surface of each patterned gate
dielectric material.
18. The semiconductor structure of claim 17 further comprising an
inner liner located on the upper surface of said conformal
nitride-containing liner in each device region, said inner liner
having one vertical edge in contact with a remaining vertical
sidewall portion of said first and second patterned gate
stacks.
19. The semiconductor structure of claim 18 further comprising an
oxide liner located on another vertical edge of said inner liner
and on an uppermost surface of said inner liner, but not in contact
with an outer vertical edge of said conformal nitride-containing
liner.
20. The semiconductor structure of claim 19 further comprising an
embedded semiconductor material having a different lattice constant
than the semiconductor substrate within the semiconductor substrate
at a footprint of the said first and second patterned gate stacks.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. patent application
Ser. No. 12/535,183, filed Aug. 4, 2009, the entire content and
disclosure of which is incorporated herein by reference.
BACKGROUND
[0002] The present invention relates to a semiconductor device and
to a method of forming a semiconductor device. More particularly,
the present invention relates to a metal oxide semiconductor field
effect transistor (MOSFET) including a high k gate dielectric in
which the threshold voltage of the device is improved and to a
method of fabricating the same.
[0003] In semiconductor devices including field effect transistors
(FETs), threshold voltage of the transistors has been
conventionally controlled by doping an impurity into the channel
region and by appropriately adjusting the dose amount. Threshold
voltage control using only this technique, e.g., only through
adjustment of the amount of the channel impurity, however, raises
nonconformities such that an increase in the dose of the impurity
to be doped into the channel region may lower ON-state current due
to scattering by the impurity, may increase the Gate-Induced Drain
Leakage (GIDL) current, and may increase substrate current upon
application of substrate voltage. For this reason,
low-power-consumption devices having a large amount of impurity
doped into the channel region have occasionally resulted in a
decrease in an ON-state current, and an increase in the GIDL
current.
[0004] Another prior art technique that has been conventionally
used to control the threshold voltage of FET devices is to
fabricate a device in which different conductivity type
transistors, e.g., nFETs and pFETs, are formed on gate oxides that
have a different thickness. That is, it is known to form a device
in which the thickness of a gate oxide film of an nFET is different
from that of a gate oxide film of a pFET.
[0005] In recent years, there has been another trend of using a
high dielectric constant film, i.e., a high k dielectric, as the
gate insulating film of FET devices. High k dielectrics are those
dielectrics that have a dielectric constant that is greater than
silicon oxide. Representative high k dielectrics that are useful as
a gate insulating material include metal oxides such as, for
example, zirconium oxide and hafnium oxide. The use of high k
dielectrics as the gate insulating film of a metal oxide
semiconductor field effect transistor (MOSFET) can successfully
reduce the equivalent silicon oxide thickness in an electrical
sense, even if the physical thickness thereof is increased relative
to a silicon oxide gate dielectric. Hence, high k dielectric films
when used as a gate insulating film are stable both in a physical
sense and in a structural sense. This makes it possible to increase
the MOS capacitance for improved MOSFET characteristics, and to
reduce gate leakage current as compared with the conventional
devices in which silicon oxide was used as the gate insulating
film.
[0006] Although high k dielectrics provide improvements over
conventionally used silicon oxide as the gate insulating film in a
FET device, the use of the same is not without problems. For
example, FET devices including high k gate dielectrics exhibit a
non-ideal threshold voltage when the device is used.
[0007] In the prior art, various techniques including, for example,
forming a threshold voltage adjusting layer interposed between the
high k gate dielectric and the gate electrode have been proposed.
Although such threshold voltage adjusting techniques have been
proposed for a device with fixed critical dimensions (i.e., channel
length of L and channel width W), large variations of threshold
voltage along critical dimensions, including Vt-L and Vt-W are
still observed. The term "Vt-L" denotes the threshold voltage along
the channel length, while the term "Vt-W" denotes the threshold
voltage along the channel width. It's critical to reduce Vt
variations of MOSFETs in a circuit, since there is always actual
variations of a device designed at the same design dimensions.
[0008] In view of the above, there is still a need for providing a
method that forms FET devices, including MOSFET and CMOS
(complementary metal oxide semiconductor) devices, in which the
variation of threshold voltage within the devices is minimized.
BRIEF SUMMARY
[0009] In one embodiment, a method of fabricating a semiconductor
structure having a controlled threshold voltage is provided that
includes providing at least one patterned gate stack in at least
one device region of a semiconductor substrate. In this embodiment,
the at least one patterned gate stack includes from bottom to top,
a patterned gate dielectric material having a dielectric constant
of greater than silicon oxide and a patterned gate conductor. An
optional patterned threshold voltage adjusting layer may also be
present between the patterned gate dielectric and the patterned
gate conductor. Next, a conformal nitride-containing liner is
formed on at least exposed sidewalls of the patterned gate
dielectric material by utilizing a low temperature nitridation
process that is performed at a temperature of less than 500.degree.
C. in a nitrogen-containing ambient.
[0010] In another embodiment, a method of fabricating a CMOS
structure having a controlled threshold voltage is provided. This
embodiment of the invention includes providing a first patterned
gate stack in a first device region of a semiconductor substrate,
and a second patterned gate stack in a second device region of the
semiconductor substrate. The first patterned gate stack includes
from bottom to top, a patterned gate dielectric material having a
dielectric constant of greater than silicon oxide, optionally a
patterned first threshold voltage adjusting layer, and a patterned
gate conductor and the second patterned gate stack includes from
bottom to top, a patterned gate dielectric material having a
dielectric constant of greater than silicon oxide, optionally a
patterned second threshold voltage adjusting layer, and a patterned
gate conductor. In this embodiment, and when present, the optional
first patterned threshold voltage adjusting layer is a different
threshold voltage adjusting type of material as compared to the
optional second patterned threshold voltage adjusting layer. Next,
a conformal nitride-containing liner is formed on at least exposed
sidewalls of the patterned gate dielectric material in both device
regions by a low temperature nitridation process that is performed
at a temperature of less than 500.degree. C. in a
nitrogen-containing ambient.
[0011] In yet another embodiment of the invention, a method of
forming a CMOS structure is provided that includes providing a
first patterned gate stack in a first device region of a
semiconductor substrate, and a second patterned gate stack in a
second device region of the semiconductor substrate. The first
patterned gate stack includes from bottom to top, a patterned gate
dielectric material having a dielectric constant of greater than
silicon oxide, optionally a patterned first threshold voltage
adjusting layer, and a patterned gate conductor and the second
patterned gate stack includes from bottom to top, a patterned gate
dielectric material having a dielectric constant of greater than
silicon oxide, optionally a patterned second threshold voltage
adjusting layer, and a patterned gate conductor. In this
embodiment, the optional first patterned threshold voltage
adjusting layer is a different threshold voltage adjusting type of
material as compared to the optional second patterned threshold
voltage adjusting layer. Next, an embedded semiconductor material
having a different lattice constant than the semiconductor
substrate is formed within the semiconductor substrate at a
footprint of one of the patterned gate stacks and thereafter
sidewalls of the patterned gate dielectric material in each of the
patterned gate stacks is selectively exposed. A conformal
nitride-containing liner is then formed on at least the exposed
sidewalls of the patterned gate dielectric material in both device
regions by a low temperature nitridation process that is performed
at a temperature of less than 500.degree. C. in a
nitrogen-containing ambient.
[0012] In a further embodiment of the invention, a semiconductor
structure is provided that has a controlled threshold voltage. The
semiconductor structure of this embodiment includes at least one
patterned gate stack in at least one device region of a
semiconductor substrate. The at least one patterned gate stack
includes from bottom to top, a patterned gate dielectric material
having a dielectric constant of greater than silicon oxide,
optionally a patterned threshold voltage adjusting layer, and a
patterned gate conductor. The structure of this embodiment further
includes a conformal nitride-containing liner located on at least
exposed sidewalls of the patterned gate dielectric material, the
conformal nitride-containing liner having a thickness of from 0.5
nm to 50 nm.
[0013] In an even further embodiment of the invention, a CMOS
structure is provided that includes a first patterned gate stack in
a first device region of a semiconductor substrate, and a second
patterned gate stack in a second device region of the semiconductor
substrate. The first patterned gate stack includes from bottom to
top, a patterned gate dielectric material having a dielectric
constant of greater than silicon oxide, optionally a patterned
first threshold voltage adjusting layer, and a patterned gate
conductor and the second patterned gate stack includes from bottom
to top, a patterned gate dielectric material having a dielectric
constant of greater than silicon oxide, optionally a patterned
second threshold voltage adjusting layer, and a patterned gate
conductor. In this embodiment, and when present, the optional first
patterned threshold voltage adjusting layer is a different
threshold voltage adjusting type of material as compared to the
optional second patterned threshold voltage adjusting layer. In
this embodiment, the structure also includes a conformal
nitride-containing liner located on at least exposed sidewalls of
the patterned gate dielectric material in both device regions, the
conformal nitride-containing liner having a thickness of from 0.5
nm to 50 nm.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0014] FIG. 1 is a pictorial representation (through a cross
sectional view) depicting an initial structure including a high k
gate dielectric located atop a substrate that can be employed in a
first embodiment of the invention.
[0015] FIG. 2 is a pictorial representation (through a cross
sectional view) depicting the structure of FIG. 1 after forming an
optional first threshold voltage adjusting layer atop the high k
gate dielectric.
[0016] FIG. 3 is a pictorial representation (through a cross
sectional view) depicting the structure of FIG. 2 after formation
of a patterned mask atop a portion of the optional first threshold
voltage adjusting layer within one device region of the
substrate.
[0017] FIG. 4 is a pictorial representation (through a cross
sectional view) depicting the structure of FIG. 3 after removing
unexposed portions of the optional first threshold voltage
adjusting layer from the device region not including the patterned
mask.
[0018] FIG. 5 is a pictorial representation (through a cross
sectional view) depicting the structure of FIG. 4 after removing
the patterned mask therefrom.
[0019] FIG. 6 is a pictorial representation (through a cross
sectional view) depicting the structure of FIG. 5 after forming an
optional second threshold adjusting layer within the device region
not including the first threshold voltage adjusting layer.
[0020] FIG. 7 is a pictorial representation (through a cross
sectional view) depicting the structure of FIG. 6 after formation
of patterned gate stacks including an optional hard mask located
atop a gate conductor material.
[0021] FIG. 8 is a pictorial representation (through a cross
sectional view) depicting the structure of FIG. 7 after performing
a low temperature nitridation process to each of the patterned gate
stacks.
[0022] FIG. 9 is a pictorial representation (through a cross
sectional view) depicting the structure of FIG. 7 after formation
of an embedded semiconductor material within the substrate at the
footprint of at least one of the patterned gate stacks in
accordance with a second embodiment of the invention.
[0023] FIG. 10 is a pictorial representation (through a cross
sectional view) depicting the structure of FIG. 9 after exposing
sidewalls of the high k gate dielectric present in each of the
patterned gate stacks.
[0024] FIG. 11 is a pictorial representation (through a cross
sectional view) depicting the structure of FIG. 10 after performing
a low temperature nitridation process to the exposed sidewalls of
the high k gate dielectric that is present in each of the patterned
gate stacks.
DETAILED DESCRIPTION
[0025] The present invention, which provides semiconductor
structures having improved threshold voltage control, will now be
described in greater detail by referring to the following
discussion and drawings that accompany the present application. It
is noted that the drawings mentioned above are provided for
illustrative purposes only and, as such, the drawings are not drawn
to scale.
[0026] In the following description, numerous specific details are
set forth, such as particular structures, components, materials,
dimensions, processing steps and techniques, in order to provide a
thorough understanding of the present invention. However, it will
be appreciated by one of ordinary skill in the art that the
invention may be practiced without these specific details. In other
instances, well-known structures or processing steps have not been
described in detail in order to avoid obscuring the invention.
[0027] It will be understood that when an element as a layer,
region or substrate is referred to as being "on" or "over" another
element, it can be directly on the other element or intervening
elements may also be present. In contrast, when an element is
referred to as being "directly on" or "directly over" another
element, there are no intervening elements present. It will also be
understood that when an element is referred to as being "connected"
or "coupled" to another element, it can be directly connected or
coupled to the other element or intervening elements may be
present. In contrast, when an element is referred to as being
"directly connected" or "directly coupled" to another element,
there are no intervening elements present.
[0028] Reference is first made to FIG. 1 which shows an initial
structure 10 that can be employed in one embodiment of the present
invention. Specifically, the initial structure 10 includes a
semiconductor substrate 12 including a first device region 14 and a
second device region 16. Although two devices regions are described
and illustrated, the present invention can be employed in
embodiments wherein a single device region is present, or in
embodiments in which a plurality of device regions are present.
[0029] The initial structure 10 illustrated in FIG. 1 also includes
a high k gate dielectric 18 located atop the semiconductor
substrate 12 in both the first device region 14 and the second
device region 16. The first device region 14 is either an nFET
device region or a pFET device region, while the second device
region 16 is the other of an nFET device region or a pFET device
region.
[0030] The semiconductor substrate 12 illustrated in FIG. 1 is
comprised of any semiconductor material including, but not limited
to Si, Ge, SiGe, SiC, SiGeC, GaAs, GaN, InAs, InP and all other
III/V or II/VI compound semiconductors. Semiconductor substrate 12
may also comprise an organic semiconductor or a layered
semiconductor such as Si/SiGe, a silicon-on-insulator (SOI), a
SiGe-on-insulator (SGOI) or a germanium-on-insulator (GOI). In some
embodiments of the present invention, it is preferred that the
semiconductor substrate 12 be composed of a Si-containing
semiconductor material, i.e., a semiconductor material that
includes silicon. The semiconductor substrate 12 may be doped,
undoped or contain doped and undoped regions therein. The
semiconductor substrate 12 may include a single crystal orientation
or it may include at least two coplanar surface regions that have
different crystal orientations (the latter substrate is referred to
in the art as a hybrid substrate). When a hybrid substrate is
employed, an nFET is typically formed on a (100) crystal surface,
while a pFET is typically formed on a (110) crystal plane. The
hybrid substrate can be formed by techniques that are well known in
the art. See, for example, co-owned U.S. Pat. No. 7,329,923, U.S.
Publication No. 20050116290, dated Jun. 2, 2005 and U.S. Pat. No.
7,023,055, the entire contents of each are incorporated herein by
reference.
[0031] The semiconductor substrate 12 may also include a first
doped (n- or p-) region, and a second doped (n- or p-) region. For
clarity, the doped regions are not specifically shown in any of the
drawings of the present application. The first doped region and the
second doped region may be the same, or they may have different
conductivities and/or doping concentrations. These doped regions
are known as "wells" and they are formed utilizing conventional ion
implantation processes.
[0032] At least one isolation region (not shown) is then typically
formed into the semiconductor substrate 12. The at least one
isolation region may be a trench isolation region or a field oxide
isolation region. The trench isolation region is formed utilizing a
conventional trench isolation process well known to those skilled
in the art. For example, lithography, etching and filling of the
trench with a trench dielectric may be used in forming the trench
isolation region. Optionally, a liner may be formed in the trench
prior to trench fill, a densification step may be performed after
the trench fill and a planarization process may follow the trench
fill as well. The field oxide may be formed utilizing a so-called
local oxidation of silicon process. Note that the at least one
isolation region provides isolation between neighboring gate
regions, typically required when the neighboring gates have
opposite conductivities, i.e., nFETs and pFETs. The isolation
region is typically present between the various device regions of
the substrate, i.e., between first device region 14 and second
device region 16.
[0033] After processing the semiconductor substrate 12, a chemox
layer (not shown) is optionally formed on the surface of the
semiconductor substrate 12. The optional chemox layer is formed
utilizing a conventional growing technique that is well known to
those skilled in the art including, for example, oxidation or
oxynitridation. In some embodiments, the chemox layer is formed by
a wet chemical oxidation process. When the substrate 12 is a
Si-containing semiconductor, the chemox layer is comprised of
silicon oxide, silicon oxynitride or a nitrided silicon oxide. When
the semiconductor substrate 12 is other than a Si-containing
semiconductor, the chemox layer may comprise a semiconducting
oxide, a semiconducting oxynitride or a nitrided semiconducting
oxide. The thickness of the chemox layer is typically from 0.5 nm
to 1.5 nm, with a thickness from 0.8 nm to 1 nm being more typical.
The thickness, however, may be different after processing at higher
temperatures, which are usually required during FET or CMOS
fabrication.
[0034] High k gate dielectric 18 is then formed atop the
semiconductor substrate 12. In some embodiments, and as
illustrated, the high k gate dielectric 18 is formed directly on a
surface of the semiconductor substrate 12. In other embodiments,
the high gate dielectric 18 is formed on a surface of the chemox
layer described above.
[0035] The high k gate dielectric 18 employed includes any
dielectric metal oxide having a dielectric constant that is greater
than the dielectric constant of silicon oxide, e.g., 3.9.
Typically, the high k gate dielectric 18 that is employed in has a
dielectric constant greater than 4.0, with a dielectric constant of
greater than 8.0 being even more typical. Exemplary high k
dielectric materials include, but are not limited to HfO.sub.2,
ZrO.sub.2, La.sub.2O.sub.3, Al.sub.2O.sub.3, TiO.sub.2,
SrTiO.sub.3, LaAlO.sub.3, Y.sub.2O.sub.3, HfO.sub.xN.sub.y,
Zro.sub.xN.sub.y, La.sub.2O.sub.xN.sub.y, Al.sub.2O.sub.xN.sub.y,
TiO.sub.xN.sub.y, SrTiO.sub.xN.sub.y, LaAlO.sub.xN.sub.y,
Y.sub.2O.sub.xN.sub.y, a silicate thereof, and an alloy thereof.
Multilayered stacks of these high k materials can also be employed
as the high k gate dielectric 18. Each value of x is independently
from 0.5 to 3 and each value of y is independently from 0 to 2.
[0036] The thickness of the high k gate dielectric 18 may vary
depending on the technique used to form the same. Typically,
however, the high k gate dielectric 18 has a thickness from 0.5 nm
to 10 nm, with a thickness from 1.0 nm to 5 nm being even more
typical. The high k gate dielectric 18 employed may have an
effective oxide thickness on the order of, or less than, 1 nm.
[0037] The high k gate dielectric 18 is formed by methods well
known in the art including, for example, chemical vapor deposition
(CVD), physical vapor deposition (PVD), molecular beam deposition
(MBD), pulsed laser deposition (PLD), liquid source misted chemical
deposition (LSMCD), atomic layer deposition (ALD), and other like
deposition processes.
[0038] Reference is now made to FIG. 2, which illustrates the
initial structure of FIG. 1 after forming an optional first
threshold voltage adjusting layer 20 atop the high k gate
dielectric 18. The term "threshold voltage adjusting layer" as used
throughout the instant application denotes a material that moves
the threshold voltage of a gate stack towards either an nFET or
pFET band edge. The optional first threshold voltage adjusting
layer 20 employed may include an nFET threshold voltage adjusting
material or a pFET threshold voltage adjusting material. The type
of threshold voltage adjusting material employed in this step is
dependent on which conductivity type device, e.g., nFET or pFET, is
being fabricated.
[0039] One example of an nFET threshold voltage adjusting material
that can be used as the optional first threshold voltage adjusting
layer 20 is a rare earth metal-containing material that comprises
an oxide or nitride of at least one element from Group IIIB of the
Periodic Table of Elements (CAS version) including, for example,
La, Ce, Pr, Nd, Pm, Sm, Eu, Ga, Tb, Dy, Ho, Er, Tm, Yb, Lu or
mixtures thereof. Preferably, the rare earth metal-containing
material comprises an oxide of La, Ce, Y, Sm, Er and/or Tb, with
La.sub.2O.sub.3 being more preferred.
[0040] The rare earth metal-containing material is formed utilizing
a conventional deposition process including, for example,
evaporation, molecular beam deposition, metalorgano chemical vapor
deposition (MOCVD), atomic layer deposition (ALD), physical vapor
deposition (PVD) and other like deposition processes. In one
embodiment of the present invention, the rare earth
metal-containing material is formed by placing the structure
including the high k gate dielectric into the load-lock of a
molecular beam deposition chamber, followed by pumping this chamber
down to the range of 10.sup.-5 Torr to 10.sup.-8 Torr. After these
steps, the structure is inserted, without breaking vacuum into the
growth chamber where the rare earth metal-containing material such
as La oxide is deposited by directing atomic/molecular beams of the
rare earth metal and oxygen or nitrogen onto the structure's
surface. Specifically, because of the low pressure of the chamber,
the released atomic/molecular species are beamlike and are not
scattered prior to arriving at the structure. A substrate
temperature of about 300.degree. C. is used. In the case of
La.sub.2O.sub.3 deposition, the La evaporation cell is held in the
temperature range of 1400.degree. C. to 1700.degree. C., and a flow
rate of 1 sccm to 3 sccm of molecular oxygen is used.
Alternatively, atomic or excited oxygen may be used as well, and
this can be created by passing the oxygen through a radio frequency
source excited in the range of 50 Watts to 600 Watts. During the
deposition, the pressure within the chamber can be in the range
from 1.times.10.sup.-5 Torr to 8.times.10.sup.-5 Torr, and the La
oxide growth rate can be in the range from 0.1 nm per minute to 2
nm per minute, with a range from 0.5 nm per minute to 1.5 nm per
minute being more typical.
[0041] Another example of an nFET threshold voltage adjusting
material that can be employed as the optional first threshold
voltage adjusting layer 20 is an alkaline earth metal-containing
material that comprises a compound having the formula MA.sub.x
wherein M is an alkaline earth metal (Be, Mg, Ca, Sr, and/or Ba), A
is one of O, S and a halide, and x is 1 or 2. Alkaline earth
metal-containing compounds that include a mixture of alkaline earth
metals and/or a mixture of anions, such as an oxychloride can also
be used as an nFET threshold voltage adjusting material. Examples
of alkaline earth metal-containing compounds that can be used
include, but are not limited to MgO, MgS, MgF.sub.2, MgCl.sub.2,
MgBr.sub.2, MgI.sub.2, CaO, CaS, CaF.sub.2, CaCl.sub.2, CaBr.sub.2,
CaI.sub.2, SrO, SrS, SrF.sub.2, SrCl.sub.2, SrBr.sub.2, SrI.sub.2,
BaO, BaS, BaF.sub.2, BaCl.sub.2, BaBr.sub.2, and BaI.sub.2. In one
preferred embodiment of the present invention, the alkaline earth
metal-containing compound includes Mg. MgO is a highly preferred
alkaline earth metal-containing material employed in one embodiment
of the present invention.
[0042] The alkaline earth metal-containing material is formed
utilizing a conventional deposition process including, for example,
sputtering from a target, reactive sputtering of an alkaline earth
metal under oxygen plasma conditions, electroplating, evaporation,
molecular beam deposition, MOCVD, ALD, PVD and other like
deposition processes.
[0043] In addition to nFET threshold voltage adjusting materials,
the optional first threshold voltage adjusting layer 20 can
alternatively be a pFET threshold voltage adjusting material.
Examples of pFET threshold voltage adjusting materials include Al
(and its compounds that are non-conductive such as, for example
Al.sub.2O.sub.3), Ge (and its compounds that are non-conductive
such as, for example GeO.sub.2), and non-conductive compounds of Ti
and Ta such as, TiO.sub.2 and Ta.sub.2O.sub.5 respectively.
[0044] The nFET threshold voltage adjusting materials are formed
utilizing conventional deposition processes well known to those
skilled in the art including, but not limited to chemical vapor
deposition (CVD), plasma enhanced chemical vapor deposition
(PECVD), chemical solution deposition, atomic layer deposition
(ALD), physical vapor deposition (PVD), sputtering and plating.
[0045] Notwithstanding the type of material used as the optional
first threshold voltage adjusting layer 20, the optional first
threshold voltage adjusting layer 20, when present, has a thickness
from 0.1 nm to 5.0 nm, with a thickness from 1.0 nm to 3.0 nm being
even more typical.
[0046] Next, and as is illustrated in FIG. 3, a first patterned
mask 22 is formed on the surface of the optional first threshold
voltage adjusting layer 20 protecting one of the device regions,
while leaving the other device region unprotected. In the
embodiment illustrated, the first patterned mask 22 is protecting a
portion of the optional first threshold voltage adjusting layer 20
that is located in the first device region 14, while another
portion of the optional threshold voltage adjusting layer 20 in the
second device region 16 is left unprotected.
[0047] The first patterned mask 22 employed may include a hard
mask, a photoresist or a multi-layered stack thereof. In one
embodiment, the first patterned mask 22 is a photoresist. In
another embodiment, the first patterned mask 22 is a hard mask
selected from a semiconductor oxide, semiconductor nitride, or
semiconductor oxynitride.
[0048] The first patterned mask 22 is formed utilizing conventional
techniques including deposition, photolithography and optionally
etching, that are well known to those skilled in the art. In
particular, and when the patterned mask is comprised solely of a
photoresist, a blanket layer of photoresist material is first
applied to the upper surface of the first threshold voltage
adjusting layer 20 utilizing a conventional deposition process such
as, for example, spin-on coating, evaporation, chemical vapor
deposition (CVD), and plasma enhanced chemical vapor deposition
(PECVD). After deposition of the blanket layer of photoresist, the
blanket layer is patterned by lithography including exposing the
photoresist to a desired pattern of radiation and then developing
the exposed resist utilizing a conventional resist developer.
[0049] When a hard mask is used as the first patterned mask 22, a
blanket layer of hard mask material is first deposited on the
surface of the optional first threshold voltage adjusting layer 20
utilizing a conventional deposition process including, for example,
CVD, PECVD, chemical solution deposition, evaporation, atomic layer
deposition (ALD), and physical vapor deposition (PVD). Next, a
blanket layer of photoresist is applied atop the blanket layer of
hard mask material, and thereafter lithography is used to pattern
the photoresist. The pattern within the patterned resist is then
transferred to the underlying hard mask material utilizing one of
dry etching (reactive ion etching, ion beam etching, plasma
etching, or laser ablation) and chemical wet etching. The patterned
resist is optionally removed from the structure following the
pattern transfer step utilizing a conventional resist stripping
process well known to those skilled in the art. Alternatively, the
patterned resist can remain atop the pattern hard mask and form a
multilayered patterned mask of the invention.
[0050] Next, the structure shown in FIG. 3 is subjected to an
etching step that selectively removes the exposed portions of the
optional first threshold voltage adjusting layer 20 from one of the
device regions that is not protected by the first patterned mask
22. In the embodiment illustrated, the optional first threshold
voltage adjusting layer 20 is removed from the second device region
16. Note that after removing the optional threshold voltage
adjusting layer 20 from the non-protected device region, an upper
surface of the underlying high k gate dielectric 18 is exposed. The
resultant structure is shown in FIG. 5. Typically, the exposed
portion of the optional first threshold adjusting layer 20 is
removed utilizing a dry etching step such as, for example, reactive
ion etching, ion beam etching, plasma etching and laser ablation.
In one embodiment of the invention, a plasma etching process is
used to strip the exposed optional first threshold voltage
adjusting layer 20 from the structure. When the first patterned
mask 22 includes a resist, this etching step can also
simultaneously remove the patterned resist. When the patterned mask
is a hard mask, a separate etching step is performed that removes
the first patterned mask from the structure. The resultant
structure after first hard mask removal is shown, for example, in
FIG. 5.
[0051] Next, an optional second threshold voltage adjusting layer
is applied to the structure shown in FIG. 5. The optional second
threshold voltage adjusting layer is the other of the nFET or pFET
threshold voltage adjusting material not employed as the optional
first threshold voltage adjusting layer 20. The optional second
threshold voltage adjusting layer is applied utilizing one of the
techniques described above in respect to the optional first
threshold voltage adjusting layer 20. Next, a second patterned mask
(not shown) is formed over the device region not including the
remaining optional first threshold voltage adjusting layer 20. In
the illustrated example, the second patterned resist is formed atop
the second device region 16.
[0052] The second patterned mask can include one of the mask
materials mentioned above for the first patterned mask and the
second patterned mask can be formed utilizing the processing
described above in forming the first patterned mask. After
application of the second patterned mask, the exposed portion of
the optional second threshold voltage adjusting layer is then
removed utilizing another etching process. After removing the
exposed optional second threshold voltage adjusting layer from the
device region including the remaining portion of the optional first
threshold voltage adjusting layer 20, the second patterned mask is
removed as described above providing the structure shown in FIG. 6.
In FIG. 6, the remaining optional second threshold voltage
adjusting layer is denoted by reference numeral 28. As shown, the
remaining optional first threshold voltage adjusting layer 20
laterally abuts the remaining optional second threshold voltage
adjusting layer 28. When the optional first and second threshold
voltage adjusting layers are not present, the processing shown in
FIGS. 2-6 can be omitted. In some embodiments, the optional first
and second threshold voltage layers are present. In other
embodiments, the optional first and second threshold voltage
adjusting layers are not present.
[0053] It is noted that in embodiments in which a single device
region is present, the application of the optional second threshold
voltage adjusting layer and second patterned mask can be
omitted.
[0054] A conductive material is then formed atop the remaining
optional first threshold voltage adjusting layer 20 and the
remaining optional second threshold voltage adjusting layer 28. If
the optional first and second threshold voltage layers are not
present, a conductive material is formed atop gate dielectric 18.
Optionally, a hard mask material can be formed atop the conductive
material. The conductive material that is employed may comprise any
conductive material including but not limited to polycrystalline
silicon, polycrystalline silicon germanium, an elemental metal,
(e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium,
palladium and platinum), an alloy of at least one elemental metal,
an elemental metal nitride (e.g., tungsten nitride, aluminum
nitride, and titanium nitride), an elemental metal silicide (e.g.,
tungsten silicide, nickel silicide, and titanium silicide) and
multilayers thereof. Preferably, the conductive material that is
formed atop the remaining threshold voltage adjusting layers
includes at least an elemental metal. In one embodiment of the
present invention, a single conductive material layer is formed. In
another embodiment of the present invention, a first conductive
material layer and a second conductive material layer are
formed.
[0055] The conductive material is formed utilizing a conventional
deposition process including, for example, chemical vapor
deposition (CVD), plasma enhanced chemical vapor deposition
(PECVD), evaporation, physical vapor deposition (PVD), sputtering,
chemical solution deposition, atomic layer deposition (ALD) and
other liked deposition processes. When Si-containing materials are
used as the conductive material, the Si-containing materials can be
doped within an appropriate impurity by utilizing either an in-situ
doping deposition process or by utilizing deposition, followed by a
step such as ion implantation in which the appropriate impurity is
introduced into the Si-containing material. When a metal silicide
is formed, a conventional silicidation process is employed.
[0056] The as deposited conductive material typically has a
thickness from 10 nm to 1000 nm, with a thickness from 50 nm to 500
nm being even more typical.
[0057] After forming the conductive material atop the remaining
optional first and second threshold voltage adjusting layers, an
optional hard mask material can be formed atop the conductive
material. The optional hard mask material includes an oxide, a
nitride, an oxynitride or any combination thereof including
multilayered stacks. When present the optional hard mask material
is formed utilizing a conventional deposition process well known to
those skilled in the art including, for example, CVD and PECVD.
Alternatively, the optional hard mask material is formed by a
thermal process such as, for example, oxidation and/or
nitridation.
[0058] The thickness of the optional hard mask material may vary
depending on the exact hard mask material employed as well as the
process that is used in forming the same. Typically, the hard mask
material has a thickness from 5 nm to 200 nm, with a thickness from
10 nm to 50 nm being even more typical. The hard mask material is
typically employed when the conductive material is a Si-containing
material such as polysilicon or SiGe.
[0059] After forming the conductive material and optionally the
hard mask material, the material stack including the same is then
patterned by conventional lithography and etching to form a first
patterned gate stack 30 in the first device region 14 and a second
patterned gate stack 32 in the second device region 16. The first
patterned gate stack 30 includes, from bottom to top, patterned
high k gate dielectric 18', optional patterned first threshold
voltage adjusting layer 20', patterned conductive conductor 27 and
optionally patterned hard mask 29. The second patterned gate stack
32 includes, from bottom to top, patterned high k gate dielectric
18', optional patterned second threshold voltage adjusting layer
28', patterned gate conductor 27 and optional patterned hard mask
29. Note that the patterned gate conductor in both device regions
is one of the conductive materials described above. The structure
including the patterned gate stacks is shown in FIG. 7.
[0060] It should be noted that variations of the method described
above can also be used to form the structure shown in FIG. 7. These
variations of forming the structure shown in FIG. 7 are also
contemplated and can be used herein as well.
[0061] In one embodiment, the patterned gate stacks, e.g., first
patterned gate stack 30 and second patterned gate stack 32, are now
subjected to a low temperature nitridation process to form a
conformal nitride-containing liner 34 on at least the sidewalls of
the patterned high k gate dielectric (hereinafter patterned gate
dielectric material) 18'; in some embodiments the conformal
nitride-containing liner 34 can also extend onto other exposed
sidewalls of the patterned gate stacks including atop the exposed
upper horizontal surface of the patterned gate stacks. The
structure including the conformal nitride-containing liner 34 is
shown, for example, in FIG. 8. The conformal nitride-containing
liner 34 is a thin layer typically having a thickness from 0.5 nm
to 50 nm, with a thickness from 1 nm to 10 nm being even more
typical.
[0062] The low temperature nitridation process that is employed in
forming conformal nitride-containing liner 34 is carried out in the
presence of a nitrogen-containing ambient. Nitrogen-containing
ambients that can be used in forming the conformal
nitride-containing liner 34 include, but are not limited to
N.sub.2, NH.sub.3, NH.sub.4, NO, NO.sub.2, SiH.sub.4 and a mixture
thereof. In some embodiments of the present invention, the
nitrogen-containing ambient can be used neat. In other embodiments
of the present invention, the nitrogen-containing ambient is
admixed with an inert gas including, for example, one of He, Ar and
Ne. When an inert gas is admixed with the nitrogen-containing
ambient, the nitrogen-containing ambient is present in the
admixture in a concentration from 0.1-100%. In one embodiment,
N.sub.2 is used as the nitrogen-containing gas.
[0063] The low temperature nitridation process is typically
performed utilizing a plasma that contains the above mentioned
nitrogen-containing ambients. The low temperature nitridation
process is also performed at a temperature that has little or no
impact on the patterned gate stack. Specifically, the low
temperature nitridation process is performed at a temperature of
less than 500.degree. C., with a temperature from 100.degree. C. to
300.degree. C. being even more preferred. Low temperature
nitridation within the aforementioned temperature range has little
or no impact on the patterned gate stacks, while temperatures above
the aforementioned range would negatively impact the patterned gate
stack by variation of threshold voltage Vt.
[0064] It is observe that the presence of the thin conformal
nitride-containing liner 34 on the sidewalls of the patterned gate
stacks, e.g., 30 and 32, helps to minimize the threshold variation
within the FET device. Moreover, the thin conformal
nitride-containing liner 34 passivates the exposed gate stack from
any potential reaction with an ambient during following processes.
Any potential reactions between the gate stack with the ambient
could cause variation of the threshold voltage Vt.
[0065] In some embodiments of the invention, a single low
temperature nitridation exposure is performed, while in other
embodiments multiple low temperature nitridation exposures are
performed.
[0066] Further CMOS processing steps can now be employed in
fabricating at least one FET device. The further CMOS processing
steps include, but are not limited to, optional gate sidewall
passivation, optional spacer formation, source and drain extension
formation, and source and drain region formation.
[0067] FIGS. 1-8 described above illustrate one embodiment of the
present invention in which low temperature nitridation is performed
after formation of the patterned gate stacks. It is noted that
improvements in threshold voltage control were not exhibited if low
temperature nitridation was performed prior to patterned gate stack
formation.
[0068] The following description, which refers to FIGS. 9-11,
illustrates another embodiment of the invention in which a low
temperature nitridation process is performed after gate patterning
and formation of an embedded semiconductor material within the
substrate at the footprint of at least one of the patterned gate
stacks. The embedded semiconductor material employed in this
embodiment of the present invention has a different lattice
constant that substrate 10.
[0069] This embodiment begins by first providing the structure
shown in either FIG. 7 or FIG. 8. For clarity, the following
description and drawings assume that the structure shown in FIG. 7
is employed. After providing that structure, an inner liner 36 is
then formed on the exposed sidewalls of the first patterned gate
stack 30 and the second patterned gate stack 32 by deposition and
etching. The inner liner 36, which is L-shaped, is comprised of a
conformal nitride-containing material such as a nitride,
oxynitride, or a multilayered stack thereof. The thickness of the
inner liner 36 is typically from 1 nm to 100 nm, with a thickness
from 10 nm to 50 nm being more typical.
[0070] After forming the inner liner 36, a low temperature oxide
liner (LTO) 38 is formed utilizing a conventional low temperature
(less than 500.degree. C.) deposition process and etching. The LTO
liner 38, which lies on an exposed horizontal surface of inner
liner 36, may comprise an oxide, oxynitride or a multilayered stack
thereof. The thickness of the LTO liner 38 is typically from 0 nm
to 100 nm, with a thickness from 5 nm to 20 nm being more
typical.
[0071] A semiconductor material block mask 40 is then formed by
conventional deposition and thereafter patterned by lithography and
etching. As is shown in FIG. 9, for example, one of the device
regions, e.g., the first device region 14, is protected by the
semiconductor material block mask 40, while the semiconductor
substrate within the other device region, e.g., the second device
region 16, is exposed. The semiconductor material block mask 40 is
comprised of an oxide, nitride, oxynitride or any multilayered
stack thereof. As shown, portions of the semiconductor substrate 12
at the footprint of the second patterned gate stack 32 within the
second device region 16 is exposed.
[0072] An etching process that selectively removes a portion of the
semiconductor substrate 12 is then performed to form a recess
region within the exposed surface of the substrate 12. In some
embodiments of the present invention, a reactive ion etching
process can be utilized to form the recess region within the
exposed portions of the substrate 12. In other embodiments of the
present invention, a crystallographic etching process can be used
to form the recess region within the exposed portion of the
semiconductor substrate 12 in the device region not protected by
the block mask 40.
[0073] A semiconductor material 42 having a different lattice
constant than the semiconductor material of the semiconductor
substrate 12 is then formed by an epitaxial growth process. The
resultant structure after performing the above mentioned steps is
shown, for example, in FIG. 9.
[0074] The semiconductor material block mask 40 is then removed
from the structure utilizing an etching process that selectively
removes the semiconductor material block mask 40 relative to the
other materials present in the structure. An isotropic etch process
is normally used. This could lead to expose sidewalls of the
patterned gate dielectric material 18' in both of the device
regions. The isotropic etching process removes the horizontal
portions of the inner spacer 36 that are located atop the substrate
12 and that are laterally adjacent to the patterned gate dielectric
material 18' in both the device regions. The resultant structure
that is formed after the isotropic etch has been performed is shown
in FIG. 10. In FIG. 10, reference numeral 44 denotes the opening
that is formed that exposes the sidewalls of the patterned gate
dielectric in both device regions.
[0075] Next, a low temperature nitridation process is performed
that forms a conformal nitride-containing liner 34' on the exposed
sidewalls of the patterned gate dielectric material 18' in both of
the device regions. The structure including the conformal
nitride-containing liner 34' is shown, for example, in FIG. 11. The
conformal nitride-containing liner 34' is a thin layer typically
having a thickness from 0.5 nm to 50 nm, with a thickness from 1 nm
to 10 nm being even more typical.
[0076] The low temperature nitridation process that is employed in
forming conformal nitride-containing liner 34' is carried out in
the presence of a nitrogen-containing ambient. Nitrogen-containing
ambients that can be used in forming conformal nitride-containing
liner 34' include, but are not limited to N.sub.2, NH.sub.3,
NH.sub.4, NO, NO.sub.2, SiH.sub.4 and a mixture thereof. In some
embodiments of the present invention, the nitrogen-containing
ambient can be used neat. In other embodiments of the present
invention, the nitrogen-containing ambient is admixed with an inert
gas including, for example, one of He, Ar and Ne. When an inert gas
is admixed with the nitrogen-containing ambient, the
nitrogen-containing ambient is present in the admixture in a
concentration from 0.1-100%. In one embodiment, N.sub.2 is used as
the nitrogen-containing gas.
[0077] The low temperature nitridation process is typically
performed utilizing a plasma that contains the above mentioned
nitrogen-containing ambients. The low temperature nitridation
process is also performed at a temperature that has little or no
impact on the patterned gate stack. Specifically, the low
temperature nitridation process is performed at a temperature of
less than 500.degree. C., with a temperature from 100.degree. C. to
300.degree. C. being even more preferred. Low temperature
nitridation within the aforementioned temperature range has little
or no impact on the patterned gate stacks, while temperatures above
the aforementioned range would negatively impact the patterned gate
stack by variation of threshold voltage Vt.
[0078] It is observed that the presence of the thin conformal
nitride-containing liner 34' on the exposed sidewalls of the
patterned gate dielectric material 18' in both device regions,
helps to eliminate the threshold variation within the FET
device.
[0079] While the present invention has been particularly shown and
described with respect to preferred embodiments thereof, it will be
understood by those skilled in the art that the foregoing and other
changes in forms and details may be made without departing from the
spirit and scope of the present invention. It is therefore intended
that the present invention not be limited to the exact forms and
details described and illustrated, but fall within the scope of the
appended claims.
* * * * *