Greene; Brian J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Greene; Brian J..The latest application filed is for "stacked-gate transistors".

Company Profile

5.89.89

Greene; Brian J. - Portland OR
Greene; Brian J. - Wappingers Falls NY
Greene; Brian J. - Fishkill NY
Greene; Brian J. - Yorktown Heights NY US
Greene; Brian J. - Hopewell Junction NY
Greene; Brian J. - Danbury CT
Greene; Brian J - Danbury CT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Stacked-gate transistors Grant 11,404,415 - Li , et al. August 2, 2	2022-08-02
Source/drain contact depth control Grant 10,991,796 - Hu , et al. April 27, 2	2021-04-27
Stacked-gate Transistors App 20210005605 - LI; Wenjun ; et al.	2021-01-07
Source/drain Contact Depth Control App 20200203480 - HU; Lin ; et al.	2020-06-25
Channel region dopant control in fin field effect transistor Grant 10,672,907 - Chowdhury , et al.	2020-06-02
Implant after through-silicon via (TSV) etch to getter mobile ions Grant 10,170,337 - Collins , et al. J	2019-01-01
Fin fabrication process with dual shallow trench isolation and tunable inner and outer fin profile Grant 10,083,878 - Greene , et al. September 25, 2	2018-09-25
Device With Decreased Pitch Contact To Active Regions App 20180261512 - GREENE; Brian J. ; et al.	2018-09-13
Device with decreased pitch contact to active regions Grant 10,074,571 - Greene , et al. September 11, 2	2018-09-11
Method and IC structure for increasing pitch between gates Grant 9,991,167 - Kumar , et al. June 5, 2	2018-06-05
Capacitor strap connection structure and fabrication method Grant 9,960,168 - Basker , et al. May 1, 2	2018-05-01
Method And Ic Structure For Increasing Pitch Between Gates App 20170287829 - Kumar; Arvind ; et al.	2017-10-05
Implant After Through-silicon Via (tsv) Etch To Getter Mobile Ions App 20170200620 - Collins; Christopher ; et al.	2017-07-13
FinFET with constrained source-drain epitaxial region Grant 9,673,197 - Greene , et al. June 6, 2	2017-06-06
FinFET with constrained source-drain epitaxial region Grant 9,536,879 - Greene , et al. January 3, 2	2017-01-03
Epitaxial growth of material on source/drain regions of FinFET structure Grant 9,536,985 - Chudzik , et al. January 3, 2	2017-01-03
Finfet With Constrained Source-drain Epitaxial Region App 20160329428 - Greene; Brian J. ; et al.	2016-11-10
FinFET with constrained source-drain epitaxial region Grant 9,443,854 - Greene , et al. September 13, 2	2016-09-13
Merged source drain epitaxy Grant 9,437,496 - Chudzik , et al. September 6, 2	2016-09-06
Capacitor Strap Connection Structure And Fabrication Method App 20160190140 - Basker; Veeraraghavan S. ; et al.	2016-06-30
Method of forming channel region dopant control in fin field effect transistor Grant 9,379,185 - Chowdhury , et al. June 28, 2	2016-06-28
Semiconductor process temperature optimization Grant 9,349,609 - Greene , et al. May 24, 2	2016-05-24
Tucked active region without dummy poly for performance boost and variation reduction Grant 9,337,338 - Greene , et al. May 10, 2	2016-05-10
Merged Fin Structures For Finfet Devices App 20160111447 - BRYANT; Andres ; et al.	2016-04-21
Merged fin structures for finFET devices Grant 9,312,274 - Bryant , et al. April 12, 2	2016-04-12
Stress-generating structure for semiconductor-on-insulator devices Grant 9,305,999 - Zhu , et al. April 5, 2	2016-04-05
Epitaxial Growth Of Material On Source/drain Regions Of Finfet Structure App 20160093720 - Chudzik; Michael P. ; et al.	2016-03-31
Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device Grant 9,299,780 - Greene , et al. March 29, 2	2016-03-29
Finfet With Constrained Source-drain Epitaxial Region App 20160043082 - Greene; Brian J. ; et al.	2016-02-11
Channel Region Dopant Control In Fin Field Effect Transistor App 20160035831 - Chowdhury; Murshed M. ; et al.	2016-02-04
Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device Grant 9,252,215 - Greene , et al. February 2, 2	2016-02-02
Finfet With Constrained Source-drain Epitaxial Region App 20160013185 - Greene; Brian J. ; et al.	2016-01-14
Constrained Epitaxial Source/drain Regions On Semiconductor-on-insulator Finfet Device App 20150357412 - Greene; Brian J. ; et al.	2015-12-10
Tucked Active Region Without Dummy Poly For Performance Boost And Variation Reduction App 20150349089 - Greene; Brian J. ; et al.	2015-12-03
High Density Finfet Devices With Unmerged Fins App 20150333145 - Chudzik; Michael P. ; et al.	2015-11-19
Multi-height Multi-composition Semiconductor Fins App 20150333087 - Greene; Brian J. ; et al.	2015-11-19
Channel Region Dopant Control In Fin Field Effect Transistor App 20150311343 - Chowdhury; Murshed M. ; et al.	2015-10-29
FinFET structure and method to adjust threshold voltage in a FinFET structure Grant 9,171,954 - Cartier , et al. October 27, 2	2015-10-27
Semiconductor Process Temperature Optimization App 20150279692 - Greene; Brian J. ; et al.	2015-10-01
Constrained Epitaxial Source/drain Regions On Semiconductor-on-insulator Finfet Device App 20150279958 - Greene; Brian J. ; et al.	2015-10-01
Tucked active region without dummy poly for performance boost and variation reduction Grant 9,105,722 - Greene , et al. August 11, 2	2015-08-11
Multi-height multi-composition semiconductor fins Grant 9,093,275 - Greene , et al. July 28, 2	2015-07-28
Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor Grant 9,082,877 - Liang , et al. July 14, 2	2015-07-14
Multi-height Multi-composition Semiconductor Fins App 20150108616 - Greene; Brian J. ; et al.	2015-04-23
Dummy gate interconnect for semiconductor device Grant 8,993,389 - Greene , et al. March 31, 2	2015-03-31
Finfet Structure And Method To Adjust Threshold Voltage In A Finfet Structure App 20150054093 - CARTIER; Eduard A. ; et al.	2015-02-26
Fin-shaped field effect transistor (finFET) structures having multiple threshold voltages (Vt) and method of forming Grant 8,941,189 - Chowdhury , et al. January 27, 2	2015-01-27
FinFET structure and method to adjust threshold voltage in a FinFET structure Grant 8,932,949 - Cartier , et al. January 13, 2	2015-01-13
Anticipatory implant for TSV Grant 8,927,427 - Graves-Abe , et al. January 6, 2	2015-01-06
Tucked Active Region Without Dummy Poly For Performance Boost And Variation Reduction App 20150001585 - Greene; Brian J. ; et al.	2015-01-01
Complementary Metal Oxide Semiconductor (cmos) Device Having Gate Structures Connected By A Metal Gate Conductor App 20140349451 - Liang; Yue ; et al.	2014-11-27
Anticipatory Implant For Tsv App 20140319694 - Graves-Abe; Troy L. ; et al.	2014-10-30
Tucked active region without dummy poly for performance boost and variation reduction Grant 8,853,035 - Yu , et al. October 7, 2	2014-10-07
MOS having a sic/sige alloy stack Grant 8,835,234 - Chidambarrao , et al. September 16, 2	2014-09-16
Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor Grant 8,803,243 - Liang , et al. August 12, 2	2014-08-12
Finfet Structure And Method To Adjust Threshold Voltage In A Finfet Structure App 20140217504 - CARTIER; Eduard A. ; et al.	2014-08-07
Creating anisotropically diffused junctions in field effect transistor devices Grant 8,796,771 - Greene , et al. August 5, 2	2014-08-05
Post-gate shallow trench isolation structure formation Grant 8,785,291 - Yu , et al. July 22, 2	2014-07-22
Post-gate shallow trench isolation structure formation Grant 8,779,469 - Greene , et al. July 15, 2	2014-07-15
Fin-Shaped Field Effect Transistor (FINFET) Structures Having Multiple Threshold Voltages (Vt) and Method of Forming App 20140191325 - Chowdhury; Murshed M. ; et al.	2014-07-10
Dummy Gate Interconnect For Semiconductor Device App 20140191295 - Greene; Brian J. ; et al.	2014-07-10
FinFET structure and method to adjust threshold voltage in a FinFET structure Grant 8,772,149 - Cartier , et al. July 8, 2	2014-07-08
Post-gate Shallow Trench Isolation Structure Formation App 20140070274 - Greene; Brian J. ; et al.	2014-03-13
Creating Anisotropically Diffused Junctions In Field Effect Transistor Devices App 20140042541 - Greene; Brian J. ; et al.	2014-02-13
Creating anisotropically diffused junctions in field effect transistor devices Grant 8,633,096 - Greene , et al. January 21, 2	2014-01-21
Stress-generating structure for semiconductor-on-insulator devices Grant 8,629,501 - Zhu , et al. January 14, 2	2014-01-14
Self-aligned embedded SiGe structure and method of manufacturing the same Grant 8,598,009 - Greene , et al. December 3, 2	2013-12-03
Mos Having A Sic/sige Alloy Stack App 20130273699 - Chidambarrao; Dureseti ; et al.	2013-10-17
Structure and method to improve threshold voltage of MOSFETs including a high k dielectric Grant 8,513,085 - Fang , et al. August 20, 2	2013-08-20
Cmos Having A Sic/sige Alloy Stack App 20130168695 - Chidambarrao; Dureseti ; et al.	2013-07-04
Stress-generating Structure For Semiconductor-on-insulator Devices App 20130168804 - Zhu; Huilong ; et al.	2013-07-04
Complementary Metal Oxide Semiconductor (CMOS) Device Having Gate Structures Connected By A Metal Gate Conductor App 20130168776 - Liang; Yue ; et al.	2013-07-04
CMOS having a SiC/SiGe alloy stack Grant 8,476,706 - Chidambarrao , et al. July 2, 2	2013-07-02
Selective partial gate stack for improved device isolation Grant 8,466,496 - Yu , et al. June 18, 2	2013-06-18
Selective Partial Gate Stack For Improved Device Isolation App 20130126976 - Yu; Xiaojun ; et al.	2013-05-23
Post-gate Shallow Trench Isolation Structure Formation App 20130099281 - Yu; Xiaojun ; et al.	2013-04-25
Finfet Structure And Method To Adjust Threshold Voltage In A Finfet Structure App 20130099313 - CARTIER; Eduard A. ; et al.	2013-04-25
Strain-compensated field effect transistor and associated method of forming the transistor Grant 8,420,468 - Escobar , et al. April 16, 2	2013-04-16
Tucked Active Region Without Dummy Poly For Performance Boost and Variation Reduction App 20130087832 - Yu; Xiaojun ; et al.	2013-04-11
Method of providing threshold voltage adjustment through gate dielectric stack modification Grant 8,354,309 - Greene , et al. January 15, 2	2013-01-15
SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME App 20120208337 - Greene; Brian J. ; et al.	2012-08-16
Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage Grant 8,236,661 - Dennard , et al. August 7, 2	2012-08-07
Self-aligned embedded SiGe structure and method of manufacturing the same Grant 8,222,673 - Greene , et al. July 17, 2	2012-07-17
Field effect device including recessed and aligned germanium containing channel Grant 8,217,470 - Chen , et al. July 10, 2	2012-07-10
Self-aligned Well Implant For Improving Short Channel Effects Control, Parasitic Capacitance, And Junction Leakage App 20120168864 - Dennard; Robert H. ; et al.	2012-07-05
Structure And Method To Improve Threshold Voltage Of Mosfets Including A High K Dielectric App 20120168874 - Fang; Sunfei ; et al.	2012-07-05
Stress-generating Structure For Semiconductor-on-insulator Devices App 20120139081 - Zhu; Huilong ; et al.	2012-06-07
Creating Anisotropically Diffused Junctions In Field Effect Transistor Devices App 20120119294 - GREENE; BRIAN J. ; et al.	2012-05-17
Structure and method to improve threshold voltage of MOSFETS including a high K dielectric Grant 8,173,531 - Fang , et al. May 8, 2	2012-05-08
Threshold Voltage Adjustment Through Gate Dielectric Stack Modification App 20120108017 - Greene; Brian J. ; et al.	2012-05-03
Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same Grant 8,115,254 - Zhu , et al. February 14, 2	2012-02-14
Threshold voltage adjustment through gate dielectric stack modification Grant 8,106,455 - Greene , et al. January 31, 2	2012-01-31
Strain-compensated Field Effect Transistor And Associated Method Of Forming The Transistor App 20110312143 - Escobar; Alberto ; et al.	2011-12-22
SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME App 20110298008 - Greene; Brian J. ; et al.	2011-12-08
Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors Grant 8,039,331 - Allen , et al. October 18, 2	2011-10-18
Field effect transistor incorporating at least one structure for imparting temperature-dependent strain on the channel region and associated method of forming the transistor Grant 8,030,687 - Escobar , et al. October 4, 2	2011-10-04
Transistor having V-shaped embedded stressor Grant 7,989,298 - Chan , et al. August 2, 2	2011-08-02
Transistor Having V-shaped Embedded Stressor App 20110183486 - Chan; Kevin K. ; et al.	2011-07-28
Method and apparatus for post silicide spacer removal Grant 7,977,185 - Greene , et al. July 12, 2	2011-07-12
Structure and method to fabricate MOSFET with short gate Grant 7,943,467 - Zhu , et al. May 17, 2	2011-05-17
Self-aligned Well Implant For Improving Short Channel Effects Control, Parasitic Capacitance, And Junction Leakage App 20110073961 - Dennard; Robert H. ; et al.	2011-03-31
Structure And Method To Improve Threshold Voltage Of Mosfets Including A High K Dielectric App 20110031554 - Fang; Sunfei ; et al.	2011-02-10
Method and structure for reducing induced mechanical stresses Grant 7,883,948 - Greene , et al. February 8, 2	2011-02-08
Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost Grant 7,842,940 - de Souza , et al. November 30, 2	2010-11-30
Method and structure for improving device performance variation in dual stress liner technology Grant 7,843,024 - Chidambarrao , et al. November 30, 2	2010-11-30
Method and structure to reduce contact resistance on thin silicon-on-insulator device Grant 7,833,873 - Greene , et al. November 16, 2	2010-11-16
Threshold Voltage Adjustment Through Gate Dielectric Stack Modification App 20100276753 - Greene; Brian J. ; et al.	2010-11-04
Methods for forming high performance gates and structures thereof Grant 7,790,553 - Zhu , et al. September 7, 2	2010-09-07
Field Effect Device Includng Recessed And Aligned Germanium Containing Channel App 20100200934 - Chen; Xiangdong ; et al.	2010-08-12
Transistor with dielectric stressor elements Grant 7,759,739 - Chidambarrao , et al. July 20, 2	2010-07-20
Method and structure to reduce contact resistance on thin silicon-on-insulator device Grant 7,687,865 - Greene , et al. March 30, 2	2010-03-30
Dual metal gate finFETs with single or dual high-K gate dielectric Grant 7,659,157 - Greene , et al. February 9, 2	2010-02-09
Transistor with dielectric stressor element fully underlying the active semiconductor region Grant 7,659,581 - Chidambarrao , et al. February 9, 2	2010-02-09
Methods For Forming High Performance Gates And Structures Thereof App 20100006926 - ZHU; HUILONG ; et al.	2010-01-14
Structure And Method To Make High Performance Mosfet With Fully Silicided Gate App 20090236676 - Zhu; Huilong ; et al.	2009-09-24
Method And Structure For Reducing Induced Mechanical Stresses App 20090236640 - Greene; Brian J. ; et al.	2009-09-24
Method and structure for reducing induced mechanical stresses Grant 7,572,689 - Greene , et al. August 11, 2	2009-08-11
Structure And Method To Fabricate Mosfet With Short Gate App 20090184378 - Zhu; Huilong ; et al.	2009-07-23
Integration Of Ion Gettering Material In Dielectric App 20090176350 - BELYANSKY; MICHAEL P. ; et al.	2009-07-09
Scalable strained FET device and method of fabricating the same Grant 7,538,339 - Greene , et al. May 26, 2	2009-05-26
Structure and method for fabrication of deep junction silicon-on-insulator transistors Grant 7,534,667 - Chidambarrao , et al. May 19, 2	2009-05-19
Method And Structure For Reducing Induced Mechanical Stresses App 20090121295 - Greene; Brian J. ; et al.	2009-05-14
Method And Structure For Improving Device Performance Variation In Dual Stress Liner Technology App 20090079011 - Chidambarrao; Dureseti ; et al.	2009-03-26
Stress-generating Structure For Semiconductor-on-insulator Devices App 20090079026 - Zhu; Huilong ; et al.	2009-03-26
Dual Metal Gate Finfets With Single Or Dual High-k Gate Dielectric App 20090078997 - Greene; Brian J. ; et al.	2009-03-26
Test structure of semiconductor device Grant 7,501,651 - Sun , et al. March 10, 2	2009-03-10
Method to reduce contact resistance on thin silicon-on-insulator device Grant 7,479,437 - Greene , et al. January 20, 2	2009-01-20
Transistor having dielectric stressor elements at different depths from a semiconductor surface for applying shear stress Grant 7,476,938 - Chidambarrao , et al. January 13, 2	2009-01-13
Strain-compensated Field Effect Transistor And Associated Method Of Forming The Transistor App 20080315264 - Escobar; Alberto ; et al.	2008-12-25
Method and structure for improving device performance variation in dual stress liner technology Grant 7,462,522 - Chidambarrao , et al. December 9, 2	2008-12-09
Structure and method for improved stress and yield in pFETS with embedded SiGe source/drain regions Grant 7,449,378 - Chidambarrao , et al. November 11, 2	2008-11-11
Methods of manufacturing semiconductor devices with rotated substrates Grant 7,449,374 - Hierlemann , et al. November 11, 2	2008-11-11
Method And Structure To Reduce Contact Resistance On Thin Silicon-on-insulator Device App 20080272412 - Greene; Brian J. ; et al.	2008-11-06
Method And Structure To Reduce Contact Resistance On Thin Silicon-on-insulator Device App 20080274597 - Greene; Brian J. ; et al.	2008-11-06
Field Effect Transistor With Inverted T Shaped Gate Electrode And Methods For Fabrication Thereof App 20080265343 - Greene; Brian J. ; et al.	2008-10-30
Opto-thermal Annealing Methods For Forming Metal Gate And Fully Silicided Gate-field Effect Transistors App 20080220581 - Allen; Scott D. ; et al.	2008-09-11
Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors Grant 7,410,852 - Allen , et al. August 12, 2	2008-08-12
Structure And Method To Form Semiconductor-on-pores (sop) For High Device Performance And Low Manufacturing Cost App 20080179712 - de Souza; Joel P. ; et al.	2008-07-31
Scalable Strained Fet Device And Method Of Fabricating The Same App 20080150033 - Greene; Brian J. ; et al.	2008-06-26
STRUCTURE AND METHOD FOR IMPROVED STRESS AND YIELD IN pFETS WITH EMBEDDED SiGe SOURCE/DRAIN REGIONS App 20080145986 - Chidambarrao; Dureseti ; et al.	2008-06-19
Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost Grant 7,365,399 - de Souza , et al. April 29, 2	2008-04-29
Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions Grant 7,358,551 - Chidambarrao , et al. April 15, 2	2008-04-15
Method And Structure For Improving Device Performance Variation In Dual Stress Liner Technology App 20080057653 - Chidambarrao; Dureseti ; et al.	2008-03-06
Test structure of semiconductor device Grant 7,317,204 - Sun , et al. January 8, 2	2008-01-08
Method and structure to reduce contact resistance on thin silicon-on-insulator device App 20070254464 - Greene; Brian J. ; et al.	2007-11-01
Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors App 20070249131 - Allen; Scott D. ; et al.	2007-10-25
A Structure And Method For Fabrication Of Deep Junction Silicon-on-insulator Transistors App 20070249126 - Chidambarrao; Dureseti ; et al.	2007-10-25
Methods of manufacturing semiconductor devices with rotated substrates App 20070173003 - Hierlemann; Matthias ; et al.	2007-07-26
Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost App 20070164358 - de Souza; Joel P. ; et al.	2007-07-19
Method And Apparatus For Post Silicide Spacer Removal App 20070161244 - Greene; Brian J. ; et al.	2007-07-12
Methods To Form Heterogeneous Silicides/germanides In Cmos Technology App 20070123042 - Rim; Kern ; et al.	2007-05-31
Transistor With Dielectric Stressor Element Fully Underlying The Active Semiconductor Region App 20070122956 - Chidambarrao; Dureseti ; et al.	2007-05-31
Transistor Having Dielectric Stressor Elements At Different Depths From A Semiconductor Surface For Applying Shear Stress App 20070114632 - Chidambarrao; Dureseti ; et al.	2007-05-24
Transistor With Dielectric Stressor Elements App 20070096215 - Chidambarrao; Dureseti ; et al.	2007-05-03
Transistor Having Dielectric Stressor Elements For Applying In-plane Shear Stress App 20070096223 - Chidambarrao; Dureseti ; et al.	2007-05-03
Semiconductor devices with rotated substrates and methods of manufacture thereof Grant 7,205,639 - Hierlemann , et al. April 17, 2	2007-04-17
STRUCTURE AND METHOD FOR IMPROVED STRESS AND YIELD IN pFETS WITH EMBEDDED SiGe SOURCE/DRAIN REGIONS App 20070018205 - Chidambarrao; Dureseti ; et al.	2007-01-25
Semiconductor devices with rotated substrates and methods of manufacture thereof App 20060202277 - Hierlemann; Matthias ; et al.	2006-09-14
Test structure of semiconductor device App 20060163569 - Sun; Min-chul ; et al.	2006-07-27
Test structure of semiconductor device App 20060113534 - Sun; Min-chul ; et al.	2006-06-01