U.S. patent application number 12/962658 was filed with the patent office on 2011-12-22 for measuring apparatus.
This patent application is currently assigned to INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE. Invention is credited to Ming-Ji Dai, Ming-Che Hsieh, John H. Lau, Wei Li, Ra-Min Tain.
Application Number | 20110309357 12/962658 |
Document ID | / |
Family ID | 45327860 |
Filed Date | 2011-12-22 |
United States Patent
Application |
20110309357 |
Kind Code |
A1 |
Tain; Ra-Min ; et
al. |
December 22, 2011 |
MEASURING APPARATUS
Abstract
A measuring apparatus including a first chip, a first circuit
layer, a first heater, a first stress sensor and a second circuit
layer is provided. The first chip has a first through silicon via,
a first surface and a second surface opposite to the first surface.
The first circuit layer is disposed on the first surface. The first
heater and the first stress sensor are disposed on the first
surface and connected to the first circuit layer. The second
circuit layer is disposed on the second surface.
Inventors: |
Tain; Ra-Min; (Taipei
County, TW) ; Lau; John H.; (Taipei City, TW)
; Hsieh; Ming-Che; (Kaohsiung City, TW) ; Li;
Wei; (Hsinchu City, TW) ; Dai; Ming-Ji;
(Hsinchu City, TW) |
Assignee: |
INDUSTRIAL TECHNOLOGY RESEARCH
INSTITUTE
Hsinchu
TW
|
Family ID: |
45327860 |
Appl. No.: |
12/962658 |
Filed: |
December 8, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61356047 |
Jun 18, 2010 |
|
|
|
Current U.S.
Class: |
257/48 ;
257/E25.018 |
Current CPC
Class: |
G01L 1/2206 20130101;
H01L 2224/16145 20130101; G01B 7/18 20130101; G01L 1/18
20130101 |
Class at
Publication: |
257/48 ;
257/E25.018 |
International
Class: |
H01L 25/07 20060101
H01L025/07 |
Claims
1. A measuring apparatus, comprising: a first chip, having a first
through silicon via, a first surface and a second surface opposite
to the first surface; a first circuit layer, disposed on the first
surface; a first heater, disposed on the first surface, and
electrically connected to the first circuit layer; a first stress
sensor, disposed on the first surface, and electrically connected
to the first circuit layer; and a second circuit layer, disposed on
the second surface.
2. The measuring apparatus as claimed in claim 1, further
comprising a conductor device disposed in the first through silicon
via.
3. The measuring apparatus as claimed in claim 2, wherein the
conductor device is electrically connected to the first circuit
layer.
4. The measuring apparatus as claimed in claim 2, wherein the
conductor device is electrically connected to the second circuit
layer.
5. The measuring apparatus as claimed in claim 2, wherein the
conductor device is electrically connected to the first circuit
layer and the second circuit layer.
6. The measuring apparatus as claimed in claim 2, wherein a
material of the conductor device is a piezoelectric material.
7. The measuring apparatus as claimed in claim 2, wherein a
material of the conductor device is a polysilicon material or
silicon doped with phosphor.
8. The measuring apparatus as claimed in claim 1, further
comprising a second heater disposed on the second surface and
electrically connected to the second circuit layer.
9. The measuring apparatus as claimed in claim 1, further
comprising a second stress sensor disposed on the second surface
and electrically connected to the second circuit layer.
10. The measuring apparatus as claimed in claim 1, further
comprising a substrate, a plurality of pads and a third circuit
layer, wherein the first chip is disposed on the substrate through
a plurality of bumps, the pads and the third circuit layer are
disposed on the substrate, and the second circuit layer is
electrically connected to the pads through the bumps and the third
circuit layer.
11. The measuring apparatus as claimed in claim 1, further
comprising: a second chip, having a second through silicon via, a
third surface and a fourth surface opposite to the third surface; a
third circuit layer, disposed on the third surface; a second
heater, disposed on the third surface, and electrically connected
to the third circuit layer; a plurality of bumps, wherein the
second chip is disposed on the first chip through the bumps, and
the third circuit layer is electrically connected to the first
circuit layer through the bumps; a second stress sensor, disposed
on the third surface, and electrically connected to the third
circuit layer; and a fourth circuit layer, disposed on the fourth
surface.
12. The measuring apparatus as claimed in claim 11, further
comprising a conductor device disposed in the second through
silicon via.
13. The measuring apparatus as claimed in claim 12, wherein the
conductor device is electrically connected to the third circuit
layer.
14. The measuring apparatus as claimed in claim 12, wherein the
conductor device is electrically connected to the fourth circuit
layer.
15. The measuring apparatus as claimed in claim 12, wherein the
conductor device is electrically connected to the third circuit
layer and the fourth circuit layer.
16. The measuring apparatus as claimed in claim 12, wherein a
material of the conductor device is a piezoelectric material.
17. The measuring apparatus as claimed in claim 12, wherein a
material of the conductor device is a polysilicon material or
silicon doped with phosphor.
18. The measuring apparatus as claimed in claim 11, further
comprising a third heater disposed on the fourth surface and
electrically connected to the fourth circuit layer.
19. The measuring apparatus as claimed in claim 11, further
comprising a third stress sensor disposed on the fourth surface and
electrically connected to the fourth circuit layer.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefit of U.S.
provisional application Ser. No. 61/356,047, filed on Jun. 18,
2010. The entirety of the above-mentioned patent application is
hereby incorporated by reference herein and made a part of this
specification.
BACKGROUND
[0002] 1. Technical Field
[0003] The disclosure relates to an apparatus. Particularly, the
disclosure relates to a measuring apparatus.
[0004] 2. Description of Related Art
[0005] As electronic system products are gradually miniaturized,
various devices originally crowded on a circuit board are gradually
packaged in a single package structure, and are further integrated
to a single chip of heterogeneous integration. Though, during the
integration process, a multi-function and heterogeneous single chip
structure requires different manufacturing processes in accordance
with different materials. However, considerable time and investment
have to be spent with respect to such situation. Facing to a
current market pattern of short product cycles and low-cost
requirements, development of the system integration heterogeneous
chip is rather uneconomic. Therefore, to integrate chips of
different functions in a same package structure becomes a worthy
development direction.
[0006] Current techniques for integrating different chips into the
same package structure include a system on chip (SoC) technique and
a system in package (SiP) technique, etc. In these techniques, a
plurality of chips is generally packaged as a package device, in
which the chips can be evenly distributed on a substrate, or the
chips can be directly stacked. Moreover, another solution is to
stack different chips into a whole group of chips according to a
bump stacking method (which is usually performed in collaboration
with wafer thinning).
[0007] In the bump stacking structure, since multiple layers of the
chips are stacked through bump bonding, the complexity of the
structure is increased. After the chips are stacked through the
bump bonding, to observe a thermal stress/strain state of each chip
and each bump caused by thermal expansion coefficient differences
of different chips, or mechanical stress/strain caused by external
force or gravity, new measurement methods have to be developed to
effectively and promptly obtain the stress/strain states of the
chips, so as to use such real-time information to accelerate design
and process improvement to enhance competitiveness.
SUMMARY
[0008] The disclosure is directed to a measuring apparatus, which
can measure stresses of chips under various temperatures.
[0009] The disclosure provides a measuring apparatus including a
first chip, a first circuit layer, a first heater, a first stress
sensor and a second circuit layer. The first chip has a first
through silicon via, a first surface and a second surface opposite
to the first surface. The first circuit layer is disposed on the
first surface. The first heater is disposed on the first surface
and is electrically connected to the first circuit layer. The first
stress sensor is disposed on the first surface and is electrically
connected to the first circuit layer. The second circuit layer is
disposed on the second surface.
[0010] According to the above descriptions, the measuring apparatus
can use the heater to simulate various operating temperatures, so
as to measure thermal resistances of the chip under various
operating temperatures.
[0011] In order to make the aforementioned and other features and
advantages of the disclosure comprehensible, several exemplary
embodiments accompanied with figures are described in detail
below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The accompanying drawings are included to provide a further
understanding of the disclosure, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the disclosure and, together with the description,
serve to explain the principles of the disclosure.
[0013] FIG. 1A is a system block diagram of a measurement system
according to an exemplary embodiment of the disclosure.
[0014] FIG. 1B shows a conductive material stretched under an
external force.
[0015] FIG. 1C shows an angle between the piezoresistive measuring
device and the coordinate axis.
[0016] FIG. 2A is a diagram illustrating a partial package
structure of a measuring apparatus according to another exemplary
embodiment of the disclosure.
[0017] FIG. 2B is a three-dimensional view of the testing apparatus
of FIG. 2A.
[0018] FIG. 3A is a schematic diagram illustrating stresses/strains
of a chip in three-dimensional directions.
[0019] FIG. 3B is diagram illustrating an equivalent geometric
figure.
[0020] FIG. 4 is a diagram illustrating a partial package structure
of a measuring apparatus according to another exemplary embodiment
of the disclosure.
[0021] FIG. 5 is a diagram illustrating a partial package structure
of a measuring apparatus according to another exemplary embodiment
of the disclosure.
[0022] FIG. 6 is a diagram illustrating a partial package structure
of a measuring apparatus according to another exemplary embodiment
of the disclosure.
DETAILED DESCRIPTION
[0023] FIG. 1A is a system block diagram of a measurement system
according to an exemplary embodiment of the disclosure. Referring
to FIG. 1A, the measurement system 100 of the present exemplary
embodiment may measure an integrated circuit (IC) device 102 having
a stacking structure. Wherein, at least one sensor (which is
described in detail later) is disposed in internal of the IC device
102 for measuring a resistance of an internal chip of the IC device
102 and producing a set of sensing signals S1+ and S1-. The sensing
signals S1+ and S1- can be transmitted to an analysis module 104
through an output terminal of the IC device 102. In this way, the
analysis module 104 can detect internal stress/strain variations of
the IC device 102 according to the sensing signals S1+ and S1-.
[0024] The analysis module 104 can be a hardware measurement device
or an analysis software, or can even be a single chip, which is not
limited by the disclosure. The analysis module 104 may analyse the
internal stress/strain variation of the IC device 102 according to
a following principal.
[0025] The disclosure provides a testing apparatus for measuring a
thermal resistance and a stress/strain value of a three-dimensional
stacked chip structure containing through silicon vias, by which
not only a strain value of a chip of each layer can be directly
measured, a stress distribution of the chip of each layer can also
be indirectly obtained. Generally, a basic principle of strain
gauge measurement is to use a length variation of a conductor or a
semiconductor material to produce a tiny variation of a resistance
thereof. As shown in FIG. 1B, a conductive material 50 originally
has a length of L, and is increased by a tiny length .DELTA.L under
an external force, and a resistance R thereof is also increased by
.DELTA.R. If a relationship of the length variation .DELTA.L and
the resistance variation .DELTA.R is found, the strain value
thereof is obtained since the strain value is equal to the length
variation .DELTA.L divided by the original length L (.DELTA.L/L).
Generally, a resistance of a conductor is proportional to a length
of the conductor and inversely proportional to a cross-sectional
area of the conductor besides relating to its own characteristics,
so that the length variation and a variation of the cross-sectional
area of the conductor cause the resistance variation. When the
semiconductor material is stressed to produce the strain, the
resistance thereof is accordingly varied. Therefore, by accurately
measure the resistance of the semiconductor material, the
relationship of the variation amount of the resistance and the
strain can be obtained, so as to achieve a purpose of measuring the
strain value. A related theoretical equation of using a
piezoresistive measuring device to measure a piezoresistive
variation amount is as follows:
.DELTA. R R = i = 1 3 j = 1 3 A ij ' .sigma. ij ' + [ .alpha. 1 T +
.alpha. 2 T 2 + ] ( 1 ) ##EQU00001##
[0026] Where, R is a resistance of the internal chip of the IC
device 102, and .DELTA.R is a variation amount of the resistance.
Moreover, A'.sub.ij is a transition matrix,
A'.sub.ij=A'.sub.ij(.pi..sub.kl,.phi.,[a.sub.kl]),
.alpha..sub.1,.alpha..sub.2 are thermal expansion coefficients of
the material, .pi..sub.kl is a piezoresistive constant of the
material, [a.sub.kl] is a coordinate axis transition matrix, and
.phi. is an angle between the piezoresistive measuring device and
the coordinate axis, as that shown in FIG. 1C. .sigma.'.sub.ij is a
stress value, which can also be represented in form of a matrix. T
is a temperature.
[0027] According to the above equation (1), it is known that as
long as the resistance and the variation amount of the resistance
of the internal chip of the IC device 102 of FIG. 1A are obtained,
the analysis module 104 can calculate the stress/strain of the IC
device 102.
[0028] Regarding the piezoresistive measuring device made of an
isotropic homogeneous piezoresistive material (for example, metal),
if the piezoresistive measuring device is parallel to the
coordinate axis (.phi.=0.degree.), the equation (1) can be
simplified as:
.DELTA. R R = .pi. .sigma. + .alpha. .DELTA. T ( 2 )
##EQU00002##
[0029] According to the equation (2), it is known that if the
piezoresistive constant of the material is 1000.times.10.sup.-12
(1/Pa), the thermal expansion coefficient of the material is
1000.times.10.sup.-6 (1/.degree. C.), and in case of a constant
temperature (.DELTA.T=0), if the piezoresistive variation amount is
0.1%, the stress value is about 10.sup.6 Pa (i.e. 1 MPa) according
to a reverse calculation.
[0030] Moreover, the testing apparatus of the disclosure may use a
heater to simulate the temperature of the chip, so that the
principle that the temperature variation of the material causes a
tiny variation of the resistance of the material can be used to
first obtain a temperature coefficient of resistance (TCR) of the
testing apparatus itself before the stress/strain is actually
measured, so as to obtain a correct resistance of the
apparatus.
[0031] The temperature dependence of conductors can be described by
the approximation below.
.rho. ( T ) = .rho. 0 [ 1 + .alpha. 0 ( T - T 0 ) ] ##EQU00003##
where ##EQU00003.2## .alpha. 0 = 1 .rho. 0 [ .delta..rho. .delta. T
] T = T 0 ##EQU00003.3##
[0032] .rho.0 just corresponds to the specific resistance
temperature coefficient at a specified reference value (normally
T=0.degree. C.).
[0033] A positive temperature coefficient refers to materials that
experience an increase in electrical resistance when their
temperature is raised. Materials which have useful engineering
applications usually show a relatively rapid increase with
temperature, i.e. a higher coefficient. The higher the coefficient,
the greater an increase in electrical resistance for a given
temperature increase.
[0034] Several exemplary embodiments are provided below to describe
an internal structure of the measuring apparatus of the
disclosure.
[0035] FIG. 2A is a diagram illustrating a partial package
structure of a measuring apparatus according to another exemplary
embodiment of the disclosure. Referring to FIG. 2A, the measuring
apparatus 1000 of the present exemplary embodiment includes a chip
1100, a circuit layer 1200, a heater 1210, a stress sensor 1220 and
a circuit layer 1230. The chip 1100 has a plurality of through
silicon vias 1110, a surface 1120 and a surface 1130 opposite to
the surface 1120, though a number of the through silicon vias 1110
can be only one. The circuit layer 1200 is disposed on the surface
1120. The heater 1210 is disposed on the surface 1120 and is
electrically connected to the circuit layer 1200. The stress sensor
1220 is disposed on the surface 1120 and is electrically connected
to the circuit layer 1200. The circuit layer 1230 is disposed on
the surface 1130.
[0036] By using the heater 1210, the measuring apparatus 1000 can
measure a temperature coefficient of resistance (TCR) curve of the
chip 1100 under various temperatures, and a basic principle thereof
is to vary a temperature of a conductor or a semiconductor
material, so that a resistance thereof is slightly varied, and a
TCR of the conductor is first calibrated before an actual
measurement, so as to facilitate measuring the temperature of the
chip and converting it to a thermal resistance of the chip.
[0037] Here, the circuit layer 1200 is a general term of all
circuits disposed on the surface 1120, and the circuit layer 1200
may include a plurality of independent circuits. The heater 1210
obtains an operation power through the circuit layer 1200, and the
stress sensor 1220 outputs a sensing signal through the circuit
layer 1200. The circuit layer 1230 is a general term of all
circuits disposed on the surface 1130, and the circuit layer 1230
may include a plurality of independent circuits. The heater 1210
is, for example, formed by a circuit, which may provide a heating
effect due to its own resistance. The stress sensor 1220 can be a
commonly used strain gauge or other types of stress sensors in the
market, and the commonly used strain gauge in the market is also
formed by a circuit with a special layout pattern, so as to
facilitate obtaining stress information of various directions.
[0038] The measuring apparatus 1000 of the present exemplary
embodiment may further include a plurality of conductor devices
1240 disposed in the through silicon vias 1110. A number of the
conductor devices 1240 is determined according to a number of the
through silicon vias 1110. The conductor devices 1240 can be only
connected to the circuit layer 1200, or can be only connected to
the circuit layer 1230, or can be simultaneously connected to both
of the circuit layers 1200 and 1230, electrically. When the upper
and lower surfaces of the chip 1100 have other devices disposed
thereon, the conductor devices 1240 can be used to only connect the
other devices on the upper and lower surfaces of the chip 1100
without connecting the circuit layers 1200 and 1230. The measuring
apparatus 1000 of the present exemplary embodiment may further
include a heater 1250, which is disposed on the surface 1130 and is
electrically connected to the circuit layer 1230, and a function of
the heater 1250 is similar to that of the heater 1210. The
measuring apparatus 1000 of the present exemplary embodiment may
further include a stress sensor 1260, which is disposed on the
surface 1130 and is electrically connected to the circuit layer
1230, and a function of the stress sensor 1260 is similar to that
of the stress sensor 1220.
[0039] The stress sensors 1220 and 1260 may sense resistances of
the upper surface 1120 of the chip 1100, and generate corresponding
sensing signals, for example, the sensing signals S1 in FIG. 1A. In
the present exemplary embodiment, the stress sensors 1220 and 1260
can be fabricated through a conductor and semiconductor material
technique or a wafer thick-film and a semiconductor fabrication
technique, and a material thereof is a material with relatively
great resistance such as copper, aluminium, polysilicon, etc. In
the disclosure, since the stress sensors can transmit the sensing
signals to the output terminal through the conductor devices and
the bumps, in some exemplary embodiments of the disclosure, the
stress sensors can also be disposed at any positions on the
chip.
[0040] In the present exemplary embodiment, since the stress
sensors 1220 and 1260 can be respectively disposed at corresponding
positions on the upper and lower surfaces 1120 and 1130 of the chip
1100, not only stresses/strains of the upper surface 1120 and the
lower surface 1130 of the chip 1100 can be sensed, stresses/strains
of the chip 1100 in three-dimensional directions can also be
analysed.
[0041] FIG. 2B is a three-dimensional view of the testing apparatus
of FIG. 2A, though FIG. 2A is not a single cross-sectional view of
FIG. 2B. Distributions of various devices on a surface 1120 of the
chip 1100 can be obtained according to FIG. 2B, for example,
tracing of the heater 1210, the plurality of stress sensors 1220
within the dash line area and the circuit layer 1200. The circuit
layer 1200 can be connected to internal devices of the chip 1100
and devices on another surface of the chip 1100 through the through
silicon vias 1110.
[0042] FIG. 3A is a schematic diagram illustrating stresses/strains
of the chip in three-dimensional directions. According to FIG. 3A,
it is obvious that the upper surface 1120 of the chip 1100 bears a
stress, so that a strain is generated on an X-Y plane, and a
displacement thereof is assumed to be u1. Moreover, the lower
surface 1130 of the chip 1100 also generates a strain on the X-Y
plane due to the stress, and a displacement thereof can be u2.
While the upper surface 1120 and the lower surface 1130 of the chip
1100 generate the strains, the chip 1100 may generate a strain
along a Z-direction. According to FIGS. 3A and 3B, it is obvious
that a thickness of the chip 1100 along the Z-direction is changed
from z1 to z2.
[0043] A Pythagorean theorem can be used to obtain a length of z2,
and a mathematic equation thereof is as follows:
z2= {square root over (z1.sup.2+(u1-u2).sup.2)} (2)
[0044] An equivalent geometric figure thereof is as that shown in
FIG. 3B. Therefore, in the present exemplary embodiment, as long as
the stresses/strains of the upper surface 1120 and the lower
surface 1130 of the chip 1100 are calculated, the stresses/strains
of the chip 1100 in the three-dimensional directions can be
simultaneously obtained.
[0045] A material of the conductor device 1240 can be a
piezoelectric material, and the material of the conductor devices
1240 can also be a polysilicon material or silicon doped with
phosphor. As described above, the stress sensor 1220 can measure
stresses/strains of the chip 1100 in two-dimensional directions. By
using the stress sensors 1220 and 1260, stresses/strains of the
chip 1100 in three-dimensional directions can be further measured.
Moreover, by measuring a resistance variation of the conductor
device 1240, a stress/strain of the chip 1100 in a thickness
direction can be obtained. Since the conductor device 1240 directly
passes through the internal of the chip 1100, the stress/strain of
the chip 1100 in the thickness direction can be accurately
measured. In addition, when the conductor device 1240 is used for
measuring the stress/strain, even if the stress sensor 1220 is not
used, the stresses/strains of the chip 1100 in the
three-dimensional directions can still be measured.
[0046] FIG. 4 is a diagram illustrating a partial package structure
of a measuring apparatus according to another exemplary embodiment
of the disclosure. Referring to FIG. 4, the measuring apparatus
1002 of the present exemplary embodiment is similar to the
measuring apparatus 1000 of FIG. 2A, so that only differences there
between are introduced below. The measuring apparatus 1002 of the
present exemplary embodiment further includes a substrate 1300, a
plurality of pads 1310 and a circuit layer 1320. The chip 1100 is
disposed on the substrate 1300 through a plurality of bumps 1330.
The pads 1310 and the circuit layer 1320 are disposed on the
substrate 1300, and the circuit layer 1230 is electrically
connected to the pads 1310 through the bumps 1330 and the circuit
layer 1320. A signal detected by the stress sensor 1220 can be
transmitted to the pads 1310 sequentially through the circuit layer
1200, the conductor devices 1240, the bumps 1330 and the circuit
layer 1320. The analysis module 104 of FIG. 1A obtains the signal
detected by the stress sensor 1220 through the pads 1310, and
analyses the signal to obtain the stress/strain of the chip 1100.
Similarly, a signal detected by the stress sensor 1260 can be
transmitted to the pads 1310 sequentially through the circuit layer
1230, the bumps 1330 and the circuit layer 1320. Moreover, the
substrate 1300 may also have through substrate vias 1340, and
conductor devices 1350 are disposed in the through substrate vias
1340. A circuit layer 1360 can be disposed on another surface of
the substrate 1300. The circuit layer 1360 is electrically
connected to the conductor devices 1350 and the pads 1310 on the
same surface of the substrate 1300.
[0047] FIG. 5 is a diagram illustrating a partial package structure
of a measuring apparatus according to another exemplary embodiment
of the disclosure. Referring to FIG. 5, the measuring apparatus
1004 of the present exemplary embodiment is similar to the
measuring apparatus 1000 of FIG. 2A, so that only differences there
between are introduced below. The measuring apparatus 1004 of the
present exemplary embodiment further includes a chip 1400, circuit
layers 1410 and 1420, heaters 1430 and 1440, stress sensors 1450
and 1460, and a plurality of bumps 1470. The chip 1400 has a
plurality of through silicon vias 1402 and surfaces 1404 and 1406
opposite to each other. The circuit layer 1410 is disposed on the
surface 1404. The heater 1430 and the stress sensor 1450 are
disposed on the surface 1404 and are electrically connected to the
circuit layer 1410. The heater 1440 and the stress sensor 1460 are
disposed on the surface 1406 and are electrically connected to the
circuit layer 1420. The chip 1400 is stacked on the chip 1100
through the bumps 1470, and the circuit layer 1410 is electrically
connected to the circuit layer 1200 through the bumps 1470. The
circuit layer 1420 is disposed on the surface 1406. The measuring
apparatus 1004 of the present exemplary embodiment may further
includes a plurality of conductor devices 1480 disposed in the
through silicon vias 1402. The conductor devices 1480 are
electrically connected to the circuit layer 1410 and/or the circuit
layer 1420. A function of the conductor devices 1480 is similar to
that of the conductor devices 1240 of FIG. 2A, so that detailed
descriptions thereof are not repeated. The measuring apparatus 1004
of the present exemplary embodiment is a three-dimensional
stacking-type chip structure, so that stresses/strains of an actual
three-dimension stacking-type chip structure having the same
structure under various temperatures can be simulated and
measured.
[0048] FIG. 6 is a diagram illustrating a partial package structure
of a measuring apparatus according to another exemplary embodiment
of the disclosure. Referring to FIG. 6, the measuring apparatus
1006 of the present exemplary embodiment is approximately a
combination of the measuring apparatus 1002 of FIG. 4 and the
measuring apparatus 1004 of FIG. 5. Namely, the measuring apparatus
1006 of the present exemplary embodiment is mainly formed by
stacking the chip 1400, the chip 1100 and the substrate 1300.
[0049] In summary, in the aforementioned exemplary embodiments, the
sensors are used to measure resistances of the chip when the chip
is deformed, and accordingly generate the sensing signals. The
sensing signals can be transmitted to the output terminal of the
substrate through the conductor devices and the bumps. In this way,
the stresses/strains of the chip can be analysed and calculated
according to the sensing signals.
[0050] Moreover, since the sensing signals are transmitted through
the conductor devices and the bumps, it is unnecessary to transmit
the sensing signals through an additional wire bonding approach, so
that allocation of the sensors can be more flexible. Further, since
allocation of the sensors is more flexible, the stresses/strains of
the chip in the three-dimensional directions can be measured.
[0051] Moreover, the measuring apparatus of the disclosure may use
heaters to simulate various operating temperatures, and a TCR of
the conductor is first calibrated before an actual measurement, so
as to facilitate measuring the temperature of the chip and
converting it to a thermal resistance of the chip.
[0052] Since the measuring apparatus of the disclosure has the
through silicon vias, when a temperature and a stress/strain
variation of the upper surface of the chip are required to be
measured, the corresponding signals can be directly transmitted to
the pads on the substrate through the through silicon vias without
using a wire bonding process to transmit the signals of the upper
surface of the chip to the substrate. Therefore, not only the
temperatures and stress/strain variations of the upper and lower
surfaces of any layer of the chip can be obtained, the signal
variation in internal of each chip can also be directly obtain. The
through silicon vias of the disclosure can also be used to measure
a stress/strain of the chip in a thickness direction, so as to
measure the stresses/strains of the chip in the three-dimensional
directions in collaboration with the sensor 1220.
[0053] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
disclosure without departing from the scope or spirit of the
disclosure. In view of the foregoing, it is intended that the
disclosure cover modifications and variations of this disclosure
provided they fall within the scope of the following claims and
their equivalents.
* * * * *