U.S. patent application number 12/904799 was filed with the patent office on 2011-04-14 for semiconductor package and process for fabricating same.
This patent application is currently assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC.. Invention is credited to CHIA-CHENG CHEN, KUANG-HSIUNG CHEN, TZU-HUI CHEN, CHIA-HSIUNG HSIEH, PAO-MING HSIEH, SHIH-FU HUANG, YUAN-CHANG SU.
Application Number | 20110084370 12/904799 |
Document ID | / |
Family ID | 43854165 |
Filed Date | 2011-04-14 |
United States Patent
Application |
20110084370 |
Kind Code |
A1 |
SU; YUAN-CHANG ; et
al. |
April 14, 2011 |
SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING SAME
Abstract
A package carrier includes: (a) a dielectric layer defining a
plurality of openings; (b) patterned electrically conductive layer,
embedded in the dielectric layer and disposed adjacent to a first
surface of the dielectric layer; a plurality of electrically
conductive posts, disposed in respective ones of the openings,
wherein the openings extend between a second surface of the
dielectric layer to the patterned electrically conductive layer,
the electrically conductive posts a connected to the patterned
electrically conductive layer, and an end of each of the
electrically conductive posts has a curved profile and is faced
away from the patterned electrically conductive layer; and (d) a
patterned solder resist layer, disposed adjacent to the first
surface of the dielectric layer and exposing portions of the
patterned electrically conductive layer corresponding to contact
pads. A semiconductor package includes the package carrier, a chip,
and an encapsulant covering the chip and the package carrier.
Inventors: |
SU; YUAN-CHANG; (Luzhu
Township, TW) ; HUANG; SHIH-FU; (Zhudong Township,
TW) ; CHEN; CHIA-CHENG; (Zhongli City, TW) ;
HSIEH; CHIA-HSIUNG; (Yanshui Township, TW) ; CHEN;
TZU-HUI; (Taitung City, TW) ; CHEN; KUANG-HSIUNG;
(Taoyuan City, TW) ; HSIEH; PAO-MING; (Zhubei
City, TW) |
Assignee: |
ADVANCED SEMICONDUCTOR ENGINEERING,
INC.
KAOHSIUNG
TW
|
Family ID: |
43854165 |
Appl. No.: |
12/904799 |
Filed: |
October 14, 2010 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
61251396 |
Oct 14, 2009 |
|
|
|
61294519 |
Jan 13, 2010 |
|
|
|
Current U.S.
Class: |
257/669 ;
257/673; 257/676; 257/E21.499; 257/E23.033; 257/E23.056;
438/123 |
Current CPC
Class: |
H05K 1/111 20130101;
H01L 2221/68345 20130101; H01L 24/29 20130101; H01L 2224/32188
20130101; H01L 2924/181 20130101; H01L 2924/0105 20130101; H01L
2924/01029 20130101; H01L 2224/83051 20130101; H01L 23/3128
20130101; H01L 2224/48091 20130101; H01L 2924/01082 20130101; H01L
2224/484 20130101; H01L 2224/32225 20130101; H01L 2924/078
20130101; H01L 2924/01075 20130101; H01L 2224/48227 20130101; H01L
24/14 20130101; H01L 2924/01079 20130101; H01L 2924/01033 20130101;
H01L 2924/01005 20130101; H01L 2924/01028 20130101; H01L 2924/01078
20130101; H01L 2924/15311 20130101; H01L 24/32 20130101; H01L 24/48
20130101; H01L 2924/01047 20130101; H01L 23/49816 20130101; H01L
2924/00014 20130101; H01L 2224/27013 20130101; H01L 2924/01046
20130101; H01L 21/6835 20130101; H01L 2924/014 20130101; H01L 24/73
20130101; H01L 2224/48228 20130101; H01L 2224/73265 20130101; H01L
23/49827 20130101; H01L 2224/484 20130101; H01L 2924/00014
20130101; H01L 2224/48091 20130101; H01L 2924/00014 20130101; H01L
2224/48091 20130101; H01L 2924/00014 20130101; H01L 2924/15311
20130101; H01L 2224/73265 20130101; H01L 2224/32225 20130101; H01L
2224/48227 20130101; H01L 2924/00012 20130101; H01L 2224/73265
20130101; H01L 2224/32225 20130101; H01L 2224/48227 20130101; H01L
2924/00012 20130101; H01L 2924/00014 20130101; H01L 2224/45099
20130101; H01L 2924/181 20130101; H01L 2924/00012 20130101 |
Class at
Publication: |
257/669 ;
257/676; 257/673; 438/123; 257/E23.033; 257/E23.056;
257/E21.499 |
International
Class: |
H01L 23/495 20060101
H01L023/495; H01L 21/48 20060101 H01L021/48 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 15, 2010 |
TW |
99107472 |
Claims
1. A semiconductor package, comprising: a package carrier,
including: a dielectric layer having a plurality of openings; a
conductive layer disposed adjacent to a first surface of the
dielectric layer; and a plurality of conductive posts disposed in
respective ones of the openings, wherein each conductive post is
connected to the conductive layer and extends away from the
conductive layer without protruding from the respective opening;
and a chip attached to the package carrier and connected to the
conductive layer.
2. The semiconductor package as claimed in claim 1, wherein the
conductive layer is embedded in the dielectric layer, and the
openings extend between a second surface of the dielectric layer to
the conductive layer.
3. The semiconductor package as claimed in claim 1, wherein an end
of each conductive post has a curved profile and is faced away from
the conductive layer.
4. The semiconductor package as claimed in claim 1, further
comprising: a solder resist layer, disposed adjacent to the first
surface of the dielectric layer and exposing portions of the
conductive layer corresponding to contact pads, and wherein the
chip is connected to the contact pads exposed by the solder resist
layer.
5. The semiconductor package as claimed in claim 4, further
comprising: an adhesive layer, disposed between the chip and the
solder resist layer.
6. The semiconductor package as claimed in claim 4, wherein the
solder resist layer has an opening disposed adjacent to the chip
and exposing a portion of the conductive layer, and further
comprising: an adhesive layer, disposed in the opening of the
solder resist layer and disposed between the chip and the portion
of the conductive layer exposed by the solder resist layer.
7. The semiconductor package as claimed in claim 1, wherein a
height of each conductive post is substantially equal to a depth of
the respective opening.
8. The semiconductor package as claimed in claim 1, further
comprising: a plurality of conductive bumps, disposed adjacent to a
second surface of the dielectric layer and connected to respective
ones of the conductive posts.
9. The semiconductor package as claimed in claim 8, wherein a
portion of each conductive bump is disposed within the respective
opening.
10. The semiconductor package as claimed in claim 1, wherein the
conductive posts are configured to relieve stress attributable to
external forces.
11. A semiconductor package, comprising: a substrate, including: a
dielectric layer having a plurality of openings; a conductive layer
disposed adjacent to the dielectric layer; and a plurality of
conductive vias disposed in respective ones of the openings; a chip
attached to the substrate and connected to the conductive layer;
and a plurality of conductive bumps disposed adjacent to respective
ones of the conductive vias, wherein a first end of each conductive
via is connected to the conductive layer, and a second end of the
conductive via is connected to the respective conductive bump such
that the second end of the conductive via does not protrude from
the respective opening.
12. The semiconductor package as claimed in claim 11, wherein the
conductive layer is disposed adjacent to a top surface of the
dielectric layer and covers a top end of each opening, and further
comprising: an etching stop layer, disposed in the openings and
disposed between the conductive vias and the conductive layer.
13. The semiconductor package as claimed in claim 11, wherein a
bottom end of each conductive via is aligned with a bottom surface
of the dielectric layer.
14. The semiconductor package as claimed in claim 11, wherein the
conductive vias are configured to relieve stress attributable to
external forces.
15. A semiconductor fabrication process, comprising: providing a
conductive layer and a plurality of conductive posts disposed
adjacent to the conductive layer; disposing a dielectric layer
having a plurality of openings on the conductive layer, wherein the
openings are coincident with the conductive posts; and patterning
the conductive layer.
16. The process as claimed in claim 15, wherein patterning the
conductive layer is carried out subsequent to disposing the
dielectric layer on the conductive layer.
17. The process as claimed in claim 15, wherein patterning the
conductive layer is carried out prior to disposing the dielectric
layer on the conductive layer.
18. The process as claimed in claim 15, further comprising:
subsequent to disposing the dielectric layer on the conductive
layer, removing a portion of each conductive post such that a
height of the conductive post is less than a thickness of the
dielectric layer.
19. The process as claimed in claim 15, further comprising:
subsequent to disposing the dielectric layer on the conductive
layer, removing a portion of each conductive post such that a
height of the conductive post is substantially equal to a thickness
of the dielectric layer.
20. The process as claimed in claim 15, wherein disposing the
dielectric layer on the conductive layer includes: providing the
dielectric layer with the openings being pre-defined in the
dielectric layer; and laminating the dielectric layer adjacent to
the conductive posts, wherein the conductive posts extend through
respective ones of the openings.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional
Application No. 61/251,396, filed on Oct. 14, 2009, U.S.
Provisional Application No. 61/294,519, filed on Jan. 13, 2010, and
Taiwan Application No. 99107472, filed on Mar. 15, 2010, the
disclosures of which are incorporated herein by reference in their
entirety.
FIELD OF THE INVENTION
[0002] The present invention relates to a semiconductor package.
More particularly, the present invention relates to a package
carrier, a package structure, and a process for fabricating a
package carrier and a package structure.
BACKGROUND
[0003] A chip package serves to protect a bare chip, reduce a
density of chip contacts, and provide a good heat dissipation
effect for the chip. A common packaging process is to install the
chip onto a package carrier, and contacts of the chip are
electrically connected to the package carrier. Therefore,
distribution of the contacts of the chip can be rearranged through
the package carrier to cope with a contact distribution of a next
stage external device.
[0004] As light weight, compactness, and high efficiency have
become typical requirements of consumer electronic and
communication products, chip packages should provide superior
electrical properties, small overall volume, and a large number of
I/O ports. Package carriers used in these chip packages often have
multiple metal layers that can be electrically connected through
interconnections. As the size of chip packages decreases, these
interconnections can become smaller and more closely spaced, which
can increase the cost and complexity of packaging processes.
[0005] It is against this background that a need arose to develop
the package carriers, the package structures, and processes
described herein.
SUMMARY
[0006] Embodiments of the present invention provide a semiconductor
package for packaging a chip. Embodiments of the present invention
also provide a process for fabricating the aforementioned
semiconductor package.
[0007] In one embodiment, a semiconductor package includes: (1) a
package carrier, including: a dielectric layer having a plurality
of openings; a conductive layer disposed adjacent to a first
surface of the dielectric layer; and a plurality of conductive
posts disposed in respective ones of the openings, wherein each
conductive post is connected to the conductive layer and extends
away from the conductive layer without protruding from the
respective opening; and (2) a chip attached to the package carrier
and connected to the conductive layer.
[0008] In another embodiment, a semiconductor package includes: (1)
a substrate, including: a dielectric layer having a plurality of
openings; a conductive layer disposed adjacent to the dielectric
layer; and a plurality of conductive vias disposed in respective
ones of the openings; (2) a chip attached to the substrate and
connected to the conductive layer; and (3) a plurality of
conductive bumps disposed adjacent to respective ones of the
conductive vias, wherein a first end of each conductive via is
connected to the conductive layer and a second end of the
conductive via is connected to the respective conductive bump such
that the second end of the conductive via does not protrude from
the respective opening.
[0009] In a further embodiment, a process of fabricating a
semiconductor package includes: (1) providing a conductive layer
and a plurality of conductive posts disposed adjacent to the
conductive layer; (2) disposing a dielectric layer having a
plurality of openings on the conductive layer, wherein the openings
are coincident with the conductive posts; and (3) patterning the
conductive layer.
[0010] As to the above, certain embodiments of the present
invention first form a plurality of electrically conductive posts
connected to an electrically conductive layer (or a patterned
electrically conductive layer) and then form a dielectric layer on
the conductive layer (or the patterned conductive layer), wherein
the dielectric layer exposes a portion of each of the conductive
posts. A semiconductor package described herein has the advantages
of reduced package size while coping with a particular circuit
layout, and controlling the cost and complexity of packaging
processes.
[0011] Other aspects and embodiments of the invention are also
contemplated. The foregoing summary and the following detailed
description are not meant to restrict the invention to any
particular embodiment but are merely meant to describe some
embodiments of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] For a better understanding of the nature and objects of some
embodiments of the invention, reference should be made to the
following detailed description taken in conjunction with the
accompanying drawings. In the drawings, like reference numbers
denote like elements, unless the context clearly dictates
otherwise.
[0013] FIG. 1A is a cross-sectional view of a semiconductor package
according to an embodiment of the present invention.
[0014] FIG. 1B to FIG. 1H are cross-sectional views of packages
according to various embodiments of the present invention.
[0015] FIG. 2A is a cross-sectional view of a package according to
another embodiment of the present invention.
[0016] FIG. 2B to FIG. 2D are cross-sectional views of packages
according to various embodiments of the present invention.
[0017] FIG. 3A to FIG. 3R illustrate a process of fabricating a
package carrier according to an embodiment of the present
invention.
[0018] FIG. 4A to FIG. 4Q illustrate a process of fabricating a
package carrier according to another embodiment of the present
invention.
[0019] FIG. 5A to FIG. 5M illustrate a process of fabricating a
package carrier according to another embodiment of the present
invention.
[0020] FIG. 6A to FIG. 6M illustrate a process of fabricating a
package carrier according to another embodiment of the present
invention.
DETAILED DESCRIPTION
[0021] FIG. 1A is a cross-sectional view of a semiconductor package
10a according to an embodiment of the present invention. Referring
to FIG. 1A, in the present embodiment, the package 10a includes a
package carrier 100a (or other substrate), a set of solder balls
102 (or other electrically conductive bumps), a chip 104 (or other
active or passive semiconductor device), a set of conductive wires
106, and an encapsulant 108.
[0022] Specifically, the package carrier 100a includes a dielectric
layer 110, a patterned electrically conductive layer 120, a set of
electrically conductive vias, and a patterned solder resist layer
140a. In the illustrated embodiment, the conductive vias correspond
to electrically conductive posts 130a, although pillars and other
hollow or solid structures can be used. The dielectric layer 110
includes a first surface 112 and a second surface 114 faced away
from the first surface 112, and defines a set of openings 116. A
material of the dielectric layer 110 can include a resin, such as
Ammonium Bifluoride, Ajinomoto build-up film (ABF), Bismaleimide
Triazine (BT), Polyimide (PI), liquid crystal polymer (LCP), epoxy
resin, or a combination thereof. These resin materials can be mixed
with glass fibers, such as in the form of a fiber pad or other
types of fibers to strengthen the dielectric layer 110.
[0023] The patterned conductive layer 120 is embedded in the
dielectric layer 110 and is disposed adjacent to the first surface
112 of the dielectric layer 110. In other words, the patterned
conductive layer 120 can be taken as an embedded circuit, and an
exposed surface (e.g., a top surface) of the patterned conductive
layer 120 is aligned (e.g., substantially aligned) with the first
surface 112 of the dielectric layer 110. The patterned conductive
layer 120 can include a metal, a metal alloy, or other electrically
conductive material. The conductive posts 130a are respectively
disposed in the openings 116, wherein the openings 116 extend from
the second surface 114 of the dielectric layer 110 to the patterned
conductive layer 120, and the conductive posts 130a are connected
to the patterned conductive layer 120. The conductive posts 130a
can include a metal (e.g., copper), a metal alloy, or other
electrically conductive material. In the present embodiment, a
height (or other characteristic vertical extent) of each of the
conductive posts 130a is less than a depth (or other characteristic
vertical extent) of the corresponding opening 116, such that the
conductive posts 130a do not protrude from the corresponding
openings 116. The patterned solder resist layer 140a is disposed
adjacent to the first surface 112 of the dielectric layer 110 and
exposes a portion of the patterned conductive layer 120. The
exposed portion of the patterned conductive layer 120 can be taken
as a set of contact pads.
[0024] The solder balls 102 are disposed adjacent to the second
surface 114 of the dielectric layer 110 and are located adjacent to
their respective conductive posts 130a. In the present embodiment,
since the height of each of the conductive posts 130a is less than
the depth of the corresponding opening 116, a portion (e.g., a top
portion) of each of the solder balls 102 is located in the
corresponding opening 116.
[0025] The chip 104 is mounted adjacent to the package carrier 100a
and located adjacent to the first surface 112 of the dielectric
layer 110. In the present embodiment, the package 10a further
includes an adhesive layer 109a, wherein the adhesive layer 109a is
disposed between the chip 104 and the patterned solder resist layer
140a to bond the chip 104 to the package carrier 100a.
[0026] The chip 104 is electrically connected to the portion of the
patterned conductive layer 120 exposed by the patterned solder
resist layer 140a through the conductive wires 106. The encapsulant
108 covers the chip 104, the conductive wires 106, and a portion of
the package carrier 100a.
[0027] By forming connections to the patterned conductive layer 120
(i.e., the embedded circuit) through the conductive posts 130a, the
package 10a of the present embodiment has the advantages of reduced
package size while coping with a particular circuit layout (e.g.,
the layout of the patterned conductive layer 120), and controlling
the cost and complexity of packaging processes. In addition, by
forming the conductive posts 130a within the dielectric layer 110,
the stress imparted by external forces, such as attributable to
mechanical shock, is compensated for, and the reliability of the
package 10a is improved.
[0028] An overall thickness of the package carrier 100a can be in
the range of about 40 .mu.m to about 150 .mu.m, and can also be in
one of the ranges of about 40 .mu.m to about 60 .mu.m, about 60
.mu.m to about 80 .mu.m, about 80 .mu.m to about 100 .mu.m, about
80 .mu.m to about 120 .mu.m, and about 40 .mu.m to about 130 .mu.m,
although the thickness of the package carrier 100a is not
constrained to any of these ranges. At the same time, the package
carrier 100a can also be sufficiently strong and rigid so that
warpage is sufficiently small to meet practical application
requirements. In some embodiments, the tensile modulus or Young's
modulus of the package carrier 100a (or a portion thereof, such as
the dielectric layer 110) can be in the range of about 10 GPa to
about 40 GPa, such as from about 15 GPa to about 40 GPa, from about
20 GPa to about 40 GPa, or from about 30 GPa to about 40 GPa.
[0029] FIG. 1B is a cross-sectional view of a package 10b according
to another embodiment of the present invention. Referring to both
FIG. 1A and FIG. 1B, the package 10b of FIG. 1B is similar to the
package 10a of FIG. 1A. At least one difference is that an adhesive
layer 109b of the package 10b of FIG. 1B is disposed between the
chip 104 and a portion of the patterned conductive layer 120
exposed by a patterned solder resist layer 140b of a package
carrier 100b.
[0030] FIG. 1C is a cross-sectional view of a package 10c according
to another embodiment of the present invention. Referring to both
FIG. 1A and FIG. 1C, in the present embodiment, the package 10c of
FIG. 1C is similar to the package 10a of FIG. 1A. At least one
difference is that a height of each conductive post 130b of a
package carrier 100c of FIG. 1C is substantially equal to a depth
of the corresponding opening 116. In other words, an end (e.g., a
lower end) of each conductive post 130b is aligned (e.g.,
substantially aligned or coplanar) with the second surface 114 of
the dielectric layer 110, and the solder balls 102 are disposed
adjacent to their respective conductive posts 130b, with little or
no portions of the solder balls 102 disposed in the openings
116.
[0031] FIG. 1D is a cross-sectional view of a package 10d according
to another embodiment of the present invention. Referring to both
FIG. 1A and FIG. 1D, the package 10d of FIG. 1D is similar to the
package 10a of FIG. 1A. At least one difference is that the
adhesive layer 109b of the package 10d of FIG. 1D is disposed
between the chip 104 and a portion of the patterned conductive
layer 120 exposed by the patterned solder resist layer 140b of a
package carrier 100d. In addition, the height of each conductive
post 130b of the package carrier 100d is substantially equal to the
depth of the corresponding opening 116. In other words, an end
(e.g., a lower end) of each conductive post 130b is aligned (e.g.,
substantially aligned or coplanar) with the second surface 114 of
the dielectric layer 110, and the solder balls 102 are disposed
adjacent to their respective conductive posts 130b, with little or
no portions of the solder balls 102 disposed in the openings
116.
[0032] FIG. 1E is a cross-sectional view of a package 10e according
to another embodiment of the present invention. Referring to both
FIG. 1A and FIG. 1E, the package 10e of FIG. 1E is similar to the
package 10a of FIG. 1A. At least one difference is that the solder
balls 102 of the package 10e include a set of first solder balls
102a and a second solder ball 102b. An orthographic projection of
the second solder ball 102b on the first surface 112 of the
dielectric layer 110 is overlapped with an orthographic projection
of the chip 104 on the first surface 112 of the dielectric layer
110. In other words, a lateral periphery of the second solder ball
102b overlaps to at least some degree with a lateral periphery of
the chip 104, when viewed from the top or the bottom of the package
10e. Also, a size (e.g., a characteristic lateral extent) of each
of the first solder balls 102a is smaller than a size of the second
solder ball 102b, and a size (e.g., a characteristic lateral
extent) of a conductive post 130a associated with each of the first
solder balls 102a is smaller than a size of a conductive post 130a
associated with the second solder ball 102b.
[0033] FIG. 1F is a cross-sectional view of a package 10f according
to another embodiment of the present invention. Referring to both
FIG. 1A and FIG. 1F, the package 10f of FIG. 1F is similar to the
package 10a of FIG. 1A. At least one difference is that the
adhesive layer 109b of the package 10f of FIG. 1F is disposed
between the chip 104 and a portion of the patterned conductive
layer 120 exposed by the patterned solder resist layer 140b. In
addition, the solder balls 102 of the package 10f include the first
solder balls 102a and the second solder ball 102b, similar to that
of the package 10e of FIG. 1E.
[0034] FIG. 1G is a cross-sectional view of a package 10g according
to another embodiment of the present invention. Referring to both
FIG. 1A and FIG. 1G, the package 10g of FIG. 1G is similar to the
package 10a of FIG. 1A. At least one difference is that the solder
balls 102 of the package 10g include the first solder balls 102a
and the second solder ball 102b, similar to that of the package 10e
of FIG. 1E. In addition and referring to FIG. 1G, the height of
each conductive post 130b is substantially equal to the depth of
the corresponding opening 116. In other words, an end (e.g., a
lower end) of each conductive post 130b is aligned (e.g.,
substantially aligned or coplanar) with the second surface 114 of
the dielectric layer 110, and the solder balls 102 are disposed
adjacent to their respective conductive posts 130b, with little or
no portions of the solder balls 102 disposed in the openings
116.
[0035] FIG. 1H is a cross-sectional view of a package 10h according
to another embodiment of the present invention. Referring to both
FIG. 1A and FIG. 1H, the package 10h of FIG. 1H is similar to the
package 10a of FIG. 1A. At least one difference is that the
adhesive layer 109b of the package 10h of FIG. 1H is disposed
between the chip 104 and a portion of the patterned conductive
layer 120 exposed by the patterned solder resist layer 140b. In
addition, the solder balls 102 of the package 10h include the first
solder balls 102a and the second solder ball 102b, similar to that
of the package 10e of FIG. 1E. In addition and referring to FIG.
1H, the height of each conductive post 130b is substantially equal
to the depth of the corresponding opening 116. In other words, an
end (e.g., a lower end) of each conductive post 130b is aligned
(e.g., substantially aligned or coplanar) with the second surface
114 of the dielectric layer 110, and the solder balls 102 are
disposed adjacent to their respective conductive posts 130b, with
little or no portions of the solder balls 102 disposed in the
openings 116.
[0036] FIG. 2A is a cross-sectional view of a package 20a according
to another embodiment of the present invention. Referring to FIG.
2A, in the present embodiment, the package 20a includes a package
carrier 200a, a set of solder balls 202, a chip 204, a set of
conductive wires 206, and an encapsulant 208. Certain aspects of
the package 20a can be similar to that previously discussed for
FIG. 1A through FIG. 1H, and those aspects are not repeated
below.
[0037] Specifically, the package carrier 200a includes a dielectric
layer 210, a patterned electrically conductive layer 220, a set of
electrically conductive posts 230a, a patterned etching stop layer
240 (or other barrier layer), and a patterned solder resist layer
250a. The dielectric layer 210 includes a first surface 212 and a
second surface 214 faced away from the first surface 212, and
defines a set of through holes 216 extending from the first surface
212 to the second surface 214. The patterned conductive layer 220
is disposed adjacent to and above the first surface 212 of the
dielectric layer 210 and covers an end of each of the through holes
216. In other words, the patterned conductive layer 220 can be
taken as an non-embedded circuit. The conductive posts 230a are
respectively disposed in the through holes 216. In the present
embodiment, a height of each of the conductive posts 230a is less
than a depth of the corresponding through hole 216. The patterned
etching stop layer 240 is disposed in the through holes 216 and
located between the conductive posts 230a and the patterned
conductive layer 220, wherein the conductive posts 230a can be
connected to the patterned conductive layer 220 through the
patterned etching stop layer 240 that is formed of, for example,
nickel or another electrically conductive material. The patterned
solder resist layer 250a is disposed adjacent to the first surface
212 of the dielectric layer 210 and covers the patterned conductive
layer 220, wherein the patterned solder resist layer 250a exposes a
portion of the patterned conductive layer 220. The exposed portion
of the patterned conductive layer 220 can be taken as a set of
contact pads.
[0038] The solder balls 202 are disposed adjacent to the second
surface 214 of the dielectric layer 210 and are located adjacent to
their respective conductive posts 230a. In the present embodiment,
since the height of each of the conductive posts 230a is less than
the depth of the corresponding through hole 216, a portion (e.g., a
top portion) of each of the solder balls 202 is located in the
corresponding through hole 216.
[0039] The chip 204 is mounted adjacent to the package carrier 200a
and located adjacent to the first surface 212 of the dielectric
layer 210. In the present embodiment, the package 20a further
includes an adhesive layer 209a, wherein the adhesive layer 209a is
disposed between the chip 204 and the patterned solder resist layer
250a to bond the chip 204 to the package carrier 200a.
[0040] The chip 204 is electrically connected to the portion of the
patterned conductive layer 220 exposed by the patterned solder
resist layer 250a through the conductive wires 206. The encapsulant
208 covers the chip 204, the conductive wires 206, and a portion of
the package carrier 200a.
[0041] By forming connections to the patterned conductive layer 220
(i.e., the non-embedded circuit) through the conductive posts 230a,
the package 20a of the present embodiment has the advantages of
reduced package size while coping with a particular circuit layout
(e.g., the layout of the patterned conductive layer 220), and
controlling the cost and complexity of packaging processes.
[0042] FIG. 2B is a cross-sectional view of a package 20b according
to another embodiment of the present invention. Referring to both
FIG. 2A and FIG. 2B, the package 20b of FIG. 2B is similar to the
package 20a of FIG. 2A. At least one difference is that an adhesive
layer 209b of the package 20b of FIG. 2B is disposed between the
chip 204 and a portion of the patterned conductive layer 220
exposed by a patterned solder resist layer 250b of a package
carrier 200b.
[0043] FIG. 2C is a cross-sectional view of a package 20c according
to another embodiment of the present invention. Referring to both
FIG. 2A and FIG. 2C, the package 20c of FIG. 2C is similar to the
package 20a of FIG. 2A. At least one difference is that a height of
each conductive post 230b of a package carrier 200c of FIG. 2C is
substantially equal to a depth of the corresponding through hole
216. In other words, an end (e.g., a lower end) of each conductive
post 230b is aligned (e.g., substantially aligned or coplanar) with
the second surface 214 of the dielectric layer 210, and the solder
balls 202 are disposed adjacent to their respective conductive
posts 230b, with little or no portions of the solder balls 202
disposed in the through holes 216.
[0044] FIG. 2D is a cross-sectional view of a package 20d according
to another embodiment of the present invention. Referring to both
FIG. 2A and FIG. 2D, the package 20d of FIG. 2D is similar to the
package 20a of FIG. 2A. At least one difference is that the
adhesive layer 209b of the package 20d of FIG. 2D is disposed
between the chip 204 and a portion of the patterned conductive
layer 220 exposed by the patterned solder resist layer 250b of a
package carrier 200d. In addition, the height of each conductive
post 230b is substantially equal to the depth of the corresponding
through hole 216. In other words, an end (e.g., a lower end) of
each conductive post 230b is aligned (e.g., substantially aligned
or coplanar) with the second surface 214 of the dielectric layer
210, and the solder balls 202 are disposed adjacent to their
respective conductive posts 230b, with little or no portions of the
solder balls 202 disposed in the through holes 216.
[0045] In some embodiments, a surface finishing or passivation
layer (not shown) can be disposed adjacent to an exposed surface of
a patterned conductive layer to facilitate wire-bonding, which
surface passivation layer can include nickel/gold,
nickel/cadmium/gold, nickel/silver, gold, tin, alloys thereof
(e.g., a tin-lead alloy), silver, electroless nickel electroless
palladium immersion gold (ENEPIG), or a combination thereof.
[0046] Although the chip 104 or 204 in the aforementioned
embodiments is electrically connected to the patterned conductive
layer 120 or 220 through a wire-bonding technique, the chip 104 or
204 can also be electrically connected to the patterned conductive
layer 120 or 220 through a flip-chip bonding technique, such as by
having an exposed surface of the patterned conductive layer 120 or
220 located below the chip 104 or 204. In particular, the chip 104
or 204 can be connected to the exposed surface of the patterned
conductive layer 120 or 220 through conductive bumps, such as
solder bumps, copper pillars, copper stud bumps, or golden stud
bumps. Moreover, an underfill material can be disposed between the
chip 104 or 204 and a package carrier for encapsulating or wrapping
the conductive bumps.
[0047] Processes of fabricating package carriers 300, 400, 500 and
600 are illustrated in the following embodiments accompanying FIG.
3A to FIG. 3R, FIG. 4A to FIG. 4Q, FIG. 5A to FIG. 5M, and FIG. 6A
to FIG. 6M.
[0048] FIG. 3A to FIG. 3R illustrate a process of fabricating the
package carrier 300 according to an embodiment of the present
invention. Referring to FIG. 3A, in the present embodiment, an
initial electrically conductive layer 302 including a first surface
303a and a second surface 303b faced away from the first surface
303a is provided. The initial conductive layer 302 can be a copper
foil, or can be formed of another metal, a metal alloy, or other
suitable electrically conductive material.
[0049] Then, referring to FIG. 3B, a first carrier 306 and a first
dry film layer 304 are disposed adjacent to the first surface 303a
of the initial conductive layer 302, wherein the first dry film
layer 304 is located between the first carrier 306 and the initial
conductive layer 302.
[0050] Next, referring to FIG. 3C, an etching stop layer 308 is
formed adjacent to the second surface 303b of the initial
conductive layer 302, such as by deposition or lamination. The
etching stop layer 308 can be formed of nickel, or can be formed of
another metal, a metal alloy, or other suitable electrically
conductive material.
[0051] Then, referring to FIG. 3D, an electrically conductive layer
312 is formed adjacent to the etching stop layer 308, such as by
deposition or lamination. The conductive layer 312 can be formed of
copper, or can be formed of another metal, a metal alloy, or other
suitable electrically conductive material.
[0052] Next, referring to FIG. 3E, the first carrier 306 is removed
to expose the first dry film layer 304, and a second carrier 316
and a second dry film layer 314 are disposed adjacent to the
conductive layer 312, wherein the second dry film layer 314 is
located between the second carrier 316 and the conductive layer
312.
[0053] Referring to both FIG. 3E and FIG. 3F, the initial
conductive layer 302 is patterned to form a set of electrically
conductive posts 302a. In the present embodiment, patterning the
initial conductive layer 302 includes patterning the first dry film
layer 304 to form a first patterned dry film layer (not shown), and
etching the initial conductive layer 302 to form the conductive
posts 302a, by using the first patterned dry film as an etching
mask and exposing the etching stop layer 308. Then, the first
patterned dry film layer is removed.
[0054] Next, referring to FIG. 3G, a portion of the etching stop
layer 308 exposed outside the conductive posts 302a is removed to
expose a portion of the conductive layer 312, and a patterned
etching stop layer 308a is accordingly formed under the conductive
posts 302a.
[0055] Then, referring to both FIG. 3H and FIG. 3I, a dielectric
layer 318 is laminated over the conductive layer 312 and then
compressed onto the conductive layer 312 by a thermal compressing
process, wherein the conductive posts 302a respectively extend
through a set of openings 318a pre-defined in the dielectric layer
318 and are exposed by the dielectric layer 318. The dielectric
layer 318 can be, for example, a prepreg.
[0056] Next, referring to FIG. 3J, a portion of each of the
conductive posts 302a is removed to form a set of truncated
conductive posts 302b, wherein a sum of a height of one of the
conductive posts 302b and a thickness of the patterned etching stop
layer 308a is less than a thickness of the dielectric layer 318. In
the present embodiment, a portion of each of the conductive posts
302a can be removed by etching or another material removal
technique, such that an end of each of the conductive posts 302b
facing away from the conductive layer 312 is concave or has another
curved profile.
[0057] Then, referring to FIG. 3K, a third d layer 322 is disposed
adjacent to the dielectric layer 318.
[0058] Next, referring to FIG. 3L, the second carrier 316 adjacent
to the second dry film layer 314 is removed, and a third carrier
324 is disposed adjacent to the third dry film layer 322, wherein
the third dry film layer 322 is located between the third carrier
324 and the dielectric layer 318.
[0059] Then, referring to both FIG. 3L and FIG. 3M, the conductive
layer 312 is patterned to form a patterned electrically conductive
layer 312a. In the present embodiment, patterning the conductive
layer 312 includes patterning the second dry film layer 314 to form
a second patterned dry film layer (not shown), and etching the
conductive layer 312 to form the patterned conductive layer 312a,
by using the second patterned dry film as an etching mask and
exposing a portion of the dielectric layer 318. Then, the second
patterned dry film layer is removed.
[0060] Next, referring to FIG. 3N, a patterned solder resist layer
326 is formed adjacent to the dielectric layer 318, wherein the
patterned solder resist layer 326 exposes a portion of the
patterned conductive layer 312a.
[0061] Then, referring to FIG. 3O, a surface passivation layer 328
is formed adjacent to and covers the portion of the patterned
conductive layer 312a exposed by the patterned solder resist layer
326. It is noted that the surface passivation layer 328 can reduce
the oxidation rate of the patterned conductive layer 312a and can
enhance bonding between the patterned conductive layer 312a and
conductive wires (not shown), when the patterned conductive layer
312a serves as bonding pads for a wire-bonding technique. The
surface passivation layer 328 can include nickel/gold,
nickel/cadmium/gold, nickel/silver, gold, tin, alloys thereof
(e.g., a tin-lead alloy), silver, ENEPIG, or a combination
thereof.
[0062] Next, referring to FIG. 3P, the third carrier 324 is removed
to expose the third dry film layer 322.
[0063] Then, referring to FIG. 3Q, the third dry film layer 322 is
removed to expose the dielectric layer 318 and the conductive posts
302b.
[0064] After that, referring to FIG. 3R, a surface passivation
layer 332 is formed adjacent to the conductive posts 302b, wherein
the surface passivation layer 332 can be an anti-oxidation layer,
such as an Organic Solderability Preservative (OSP) to reduce the
oxidation rate of the conductive posts 302b. The OSP can include
benzotriazole, benzimidazoles, or combinations and derivatives
thereof. In such manner, the package carrier 300 is formed.
[0065] The present embodiment forms the conductive posts 302a that
are connected to the conductive layer 312, compresses the
dielectric layer 318 onto the conductive layer 312 while exposing a
portion of each of the conductive posts 302a, and then forms the
patterned conductive layer 312a to obtain the package carrier 300
including a non-embedded circuit and the conductive posts 302b.
[0066] Once the package carrier 300 is fabricated, a package
according to an embodiment of the invention can be fabricated by
disposing a chip (e.g., the chip 204 in FIG. 2A) adjacent to the
package carrier 300, electrically connecting the chip to the
patterned conductive layer 312a, and disposing solder balls (e.g.,
the solder balls 202 of FIG. 2A) adjacent to the conductive posts
302b. By forming connections to the patterned conductive layer 312a
(i.e., the non-embedded circuit) through the conductive posts 302b,
the resulting package has the advantages of reduced package size
while coping with a particular circuit layout (e.g., the layout of
the patterned conductive layer 312a), and controlling the cost and
complexity of packaging processes.
[0067] FIG. 4A to FIG. 4Q illustrate a process of fabricating the
package carrier 400 according to an embodiment of the present
invention. Referring to FIG. 4A, in the present embodiment, an
initial electrically conductive layer 402 including a first surface
403a and a second surface 403b faced away from the first surface
403a is provided. The initial conductive layer 402 can be a copper
foil, or can be formed of another metal, a metal alloy, or other
suitable electrically conductive material.
[0068] Then, referring to FIG. 4B, a first carrier 406 and a first
dry film layer 404 are disposed adjacent to the first surface 403a
of the initial conductive layer 402, wherein the first dry film
layer 404 is located between the first carrier 406 and the initial
conductive layer 402.
[0069] Next, referring to FIG. 4C, an etching stop layer 408 is
formed adjacent to the second surface 403b of the initial
conductive layer 402, such as by deposition or lamination. The
etching stop layer 408 can be formed of nickel, or can be formed of
another metal, a metal alloy, or other suitable electrically
conductive material.
[0070] Then, referring to FIG. 4D, an electrically conductive layer
412 is formed adjacent to the etching stop layer 408, such as by
deposition or lamination. The conductive layer 412 can be formed of
copper, or can be formed of another metal, a metal alloy, or other
suitable electrically conductive material.
[0071] Next, referring to FIG. 4E, the first carrier 406 is removed
to expose the first dry film layer 404, and a second carrier 416
and a second dry film layer 414 are disposed adjacent to the
conductive layer 412, wherein the second dry film layer 414 is
located between the second carrier 416 and the conductive layer
412.
[0072] Referring to both FIG. 4E and FIG. 4F, the initial
conductive layer 402 is patterned to form a set of electrically
conductive posts 402a. In the present embodiment, patterning the
initial conductive layer 402 includes patterning the first dry film
layer 404 to form a first patterned dry film layer (not shown), and
etching the initial conductive layer 402 to form the conductive
posts 402a, by using the first patterned dry film as an etching
mask and exposing the etching stop layer 408. Then, the first
patterned dry film layer is removed.
[0073] Next, referring to FIG. 4G, a portion of the etching stop
layer 408 exposed outside the conductive posts 402a is removed to
expose a portion of the conductive layer 412, and a patterned
etching stop layer 408a is accordingly formed under the conductive
posts 402a.
[0074] Then, referring to both FIG. 4H and FIG. 4I, a dielectric
layer 418 is laminated over the conductive layer 412 and then
compressed onto the conductive layer 412 by a thermal compressing
process, wherein the conductive posts 402a respectively extend
through a set of openings 418a pre-defined in the dielectric layer
418 and are exposed by the dielectric layer 418. The dielectric
layer 418 can be, for example, a prepreg. In the present
embodiment, a sum of a height of one of the conductive posts 402a
and a thickness of the patterned etching stop layer 408a is
substantially equal to a thickness of the dielectric layer 418.
Also, a portion of each of the conductive posts 402a can be removed
by etching or another material removal technique, such that an end
of each of the conductive posts 402a facing away from the
conductive layer 412 is concave or has another curved profile.
[0075] Then, referring to FIG. 4J, a third dry film layer 422 is
disposed adjacent to the dielectric layer 418, wherein an end of
each of the conductive posts 402a directly contacts the third dry
film layer 422.
[0076] Next, referring to FIG. 4K, the second carrier 416 adjacent
to the second dry film layer 414 is removed, and a third carrier
424 is disposed adjacent to the third dry film layer 422, wherein
the third dry film layer 422 is located between the third carrier
424 and the dielectric layer 418.
[0077] Then, referring to both FIG. 4K and FIG. 4L, the conductive
layer 412 is patterned to form a patterned electrically conductive
layer 412a. In the present embodiment, patterning the conductive
layer 412 includes patterning the second dry film layer 414 to form
a second patterned dry film layer (not shown), and etching the
conductive layer 412 to form the patterned conductive layer 412a,
by using the second patterned dry film as an etching mask and
exposing a portion of the dielectric layer 418. Then, the second
patterned dry film layer is removed.
[0078] Next, referring to FIG. 4M, a patterned solder resist layer
426 is formed adjacent to the dielectric layer 418, wherein the
patterned solder resist layer 426 exposes a portion of the
patterned conductive layer 412a.
[0079] Then, referring to FIG. 4N, a surface passivation layer 428
is formed adjacent to and covers the portion of the patterned
conductive layer 412a exposed by the patterned solder resist layer
426. It is noted that the surface passivation layer 428 can reduce
the oxidation rate of the patterned conductive layer 412a and can
enhance bonding between the patterned conductive layer 412a and
conductive wires (not shown), when the patterned conductive layer
412a serves as bonding pads for a wire-bonding technique. The
surface passivation layer 428 can include nickel/gold,
nickel/cadmium/gold, nickel/silver, gold, tin, alloys thereof
(e.g., a tin-lead alloy), silver, ENEPIG, or a combination
thereof.
[0080] Next, referring to FIG. 4O, the third carrier 424 is removed
to expose the third dry film layer 422.
[0081] Then, referring to FIG. 4P, the third dry film layer 422 is
removed to expose the dielectric layer 418 and the conductive posts
402a.
[0082] After that, referring to FIG. 4Q, a surface passivation
layer 432 is formed adjacent to the conductive posts 402a, wherein
the surface passivation layer 432 can be an anti-oxidation layer,
such as an OSP to reduce the oxidation rate of the conductive posts
402a. In such manner, the package carrier 400 is formed.
[0083] Once the package carrier 400 is fabricated, a package
according to an embodiment of the invention can be fabricated by
disposing a chip (e.g., the chip 204 in FIG. 2C) adjacent to the
package carrier 400, electrically connecting the chip to the
patterned conductive layer 412a, and disposing solder balls (e.g.,
the solder balls 202 of FIG. 2C) adjacent to the conductive posts
402a.
[0084] FIG. 5A to FIG. 5M illustrate a process of fabricating the
package carrier 500 according to an embodiment of the present
invention. Referring to FIG. 5A, in the present embodiment, an
initial electrically conductive layer 502 including a first surface
503a and a second surface 503b faced away from the first surface
503a is provided. The initial conductive layer 502 can be a copper
foil, or can be formed of another metal, a metal alloy, or other
suitable electrically conductive material.
[0085] Next, referring to FIG. 5B, a first carrier 504 is disposed
adjacent to the second surface 503b of the initial conductive layer
502.
[0086] Then, referring to FIG. 5C, a patterned electrically
conductive layer 506 is formed adjacent to the first surface 503a
of the initial conductive layer 502 by a semi-additive process.
Specifically, a dielectric material, a photo-resist, or another
applicable material serving as a temporary mask is disposed
adjacent to the initial conductive layer 502. Then, the mask is
patterned to form a set of openings at locations corresponding to
the patterned conductive layer 506. The patterned conductive layer
506 is then formed in the openings in a plating process, by using
the initial conductive layer 502 as an electrode (e.g., a cathode).
After that, the mask for plating is removed.
[0087] Then, referring to FIG. 5D, a set of electrically conductive
posts 508 are formed adjacent to the patterned conductive layer 506
by a semi-additive process. Specifically, a dielectric material, a
photo-resist, or another applicable material serving as a temporary
mask is disposed adjacent to the structure of FIG. 5C. Then, the
mask is patterned to form a set of openings at locations
corresponding to the conductive posts 508. The conductive posts 508
are then formed in the openings in a plating process, by using the
initial conductive layer 502 and the patterned conductive layer 506
as an electrode (e.g., a cathode). After that, the mask for plating
is removed.
[0088] Then, referring to both FIG. 5E and FIG. 5F, a dielectric
layer 512 is laminated over the first surface 503a of the initial
conductive layer 502 and then compressed onto the first surface
503a of the initial conductive layer 502 by a thermal compressing
process, wherein the conductive posts 508 respectively extend
through a set of openings 512a pre-defined in the dielectric layer
512 and are exposed by the dielectric layer 512. The dielectric
layer 512 can be, for example, a prepreg.
[0089] Next, referring to FIG. 5G, a portion of each of the
conductive posts 508 is removed to form a set of truncated
conductive posts 508a, wherein a sum of a height of one of the
conductive posts 508a and a thickness of the patterned conductive
layer 506 is less than a thickness of the dielectric layer 512. In
the present embodiment, a portion of each of the conductive posts
508 can be removed by etching or another material removal
technique, such that an end of each of the conductive posts 508a
facing away from the patterned conductive layer 506 is concave or
has another curved profile.
[0090] Next, referring to FIG. 5H, the first carrier 504 is removed
to expose the second surface 503b of the initial conductive layer
502, and a second carrier 516 and a dry film layer 514 are disposed
adjacent to the dielectric layer 512, wherein the dry film layer
514 is located between the second carrier 516 and the dielectric
layer 512.
[0091] Then, referring to FIG. 5I, the initial conductive layer 502
is removed to expose the dielectric layer 512 and the patterned
conductive layer 506. The initial conductive layer 502 can be
removed by etching or another material removal technique.
[0092] Next, referring to FIG. 5J, a patterned solder resist layer
518 is formed adjacent to the dielectric layer 512, wherein the
patterned solder resist layer 518 exposes a portion of the
patterned conductive layer 506.
[0093] Afterwards, referring to FIG. 5K, a surface passivation
layer 522 is formed adjacent to and covers the portion of the
patterned conductive layer 506 exposed by the patterned solder
resist layer 518. It is noted that the surface passivation layer
522 can reduce the oxidation rate of the patterned conductive layer
506 and can enhance bonding between the patterned conductive layer
506 and conductive wires (not shown), when the patterned conductive
layer 506 serves as bonding pads for a wire-bonding technique.
[0094] Then, referring to FIG. 5L, the second carrier 516 and the
dry film layer 514 are removed to expose the dielectric layer 512
and the conductive posts 508a.
[0095] After that, referring to FIG. 5M, a surface passivation
layer 524 is formed adjacent to the conductive posts 508a, wherein
the surface passivation layer 524 can be an anti-oxidation layer,
such as an OSP to reduce the oxidation rate of the conductive posts
508a. In such manner, the package carrier 500 is formed.
[0096] The present embodiment forms the conductive posts 508 that
are connected to the patterned conductive layer 506, compresses the
dielectric layer 512 onto the patterned conductive layer 506 while
exposing a portion of each of the conductive posts 508, thereby
obtaining the package carrier 500 including an embedded circuit and
the conductive posts 508a.
[0097] Once the package carrier 500 is fabricated, a package
according to an embodiment of the invention can be fabricated by
disposing a chip (e.g., the chip 104 in FIG. 1A) adjacent to the
package carrier 500, electrically connecting the chip to the
patterned conductive layer 506, and disposing solder balls (e.g.,
the solder balls 102 of FIG. 1A) adjacent to the conductive posts
508a. By forming connections to the patterned conductive layer 506
(i.e., the embedded circuit) through the conductive posts 508a, the
resulting package has the advantages of reduced package size while
coping with a particular circuit layout (e.g., the layout of the
patterned conductive layer 506), and controlling the cost and
complexity of packaging processes.
[0098] FIG. 6A to FIG. 6M illustrate a process of fabricating the
package carrier 600 according to an embodiment of the present
invention. Referring to FIG. 6A, in the present embodiment, an
initial electrically conductive layer 602 including a first surface
603a and a second surface 603b faced away from the first surface
603a is provided. The initial conductive layer 602 can be a copper
foil, or can be formed of another metal, a metal alloy, or other
suitable electrically conductive material.
[0099] Next, referring to FIG. 6B, a first carrier 604 is disposed
adjacent to the second surface 603b of the initial conductive layer
602.
[0100] Next, referring to FIG. 6C, a patterned electrically
conductive layer 606 is formed adjacent to the first surface 603a
of the initial conductive layer 602 by a semi-additive process,
similar to that discussed above for FIG. 5C.
[0101] Then, referring to FIG. 6D, a set of electrically conductive
posts 608 are formed adjacent to the patterned conductive layer 606
by a semi-additive process, similar to that discussed above for
FIG. 5D.
[0102] Then, referring to both FIG. 6E and FIG. 6F, a dielectric
layer 612 is laminated over the first surface 603a of the initial
conductive layer 602 and then compressed onto the first surface
603a of the initial conductive layer 602 by a thermal compressing
process, wherein the conductive posts 608 respectively extend
through a set of openings 612a pre-defined in the dielectric layer
612 and are exposed by the dielectric layer 612. The dielectric
layer 612 can be, for example, a prepreg.
[0103] Next, referring to FIG. 6G, a portion of each of the
conductive posts 608 is removed to form a set of truncated
conductive posts 608a, wherein a sum of a height of one of the
conductive posts 608a and a thickness of the patterned conductive
layer 606 is substantially equal to a thickness of the dielectric
layer 612. In the present embodiment, a portion of each of the
conductive posts 608 can be removed by etching or another material
removal technique, such that an end of each of the conductive posts
608a facing away from the patterned conductive layer 606 is concave
or has another curved profile.
[0104] Next, referring to FIG. 6H, the first carrier 604 is removed
to expose the second surface 603b of the initial conductive layer
602, and a second carrier 616 and a dry film layer 614 are disposed
adjacent to the dielectric layer 612, wherein the dry film layer
614 is located between the second carrier 616 and the dielectric
layer 612.
[0105] Then, referring to FIG. 6I, the initial conductive layer 602
is removed to expose the dielectric layer 612 and the patterned
conductive layer 606. The initial conductive layer 602 can be
removed by etching or another material removal technique.
[0106] Next, referring to FIG. 6J, a patterned solder resist layer
618 is formed adjacent to the dielectric layer 612, wherein the
patterned solder resist layer 618 exposes a portion of the
patterned conductive layer 606.
[0107] Afterwards, referring to FIG. 6K, a surface passivation
layer 622 is formed adjacent to and covers the portion of the
patterned conductive layer 606 exposed by the patterned solder
resist layer 618. It is noted that the surface passivation layer
622 can reduce the oxidation rate of the patterned conductive layer
606 and can enhance bonding between the patterned conductive layer
606 and conductive wires (not shown), when the patterned conductive
layer 606 serves as bonding pads for a wire-bonding technique.
[0108] Then, referring to FIG. 6L, the second carrier 616 and the
dry film layer 614 are removed to expose the dielectric layer 612
and the conductive posts 608a.
[0109] After that, referring to FIG. 6M, a surface passivation
layer 624 is formed adjacent to the conductive posts 608a, wherein
the surface passivation layer 624 can be an anti-oxidation layer,
such as an OSP to reduce the oxidation rate of the conductive posts
608a. In such manner, the package carrier 600 is formed.
[0110] Once the package carrier 600 is fabricated, a package
according to an embodiment of the invention can be fabricated by
disposing a chip (e.g., the chip 104 in FIG. 1C) adjacent to the
package carrier 600, electrically connecting the chip to the
patterned conductive layer 606, and disposing solder balls (e.g.,
the solder balls 102 of FIG. 1C) adjacent to the conductive posts
608a.
[0111] It should be recognized that similar operations as discussed
for FIG. 3A to FIG. 3R, FIG. 4A to FIG. 4Q, FIG. 5A to FIG. 5M, and
FIG. 6A to FIG. 6M can be used to fabricate other package carriers
and packages (e.g., as illustrated in FIG. 1B, FIG. 1D to FIG. 1H,
FIG. 2B, and FIG. 2D).
[0112] In summary, in a package carrier of some embodiments of the
invention, electrically conductive posts can be used so as to
effectively reduce a package size and a package area, while
controlling the cost and complexity of packaging processes.
[0113] While the invention has been described with reference to the
specific embodiments thereof, it should be understood by those
skilled in the art that various changes may be made and equivalents
may be substituted without departing from the true spirit and scope
of the invention. In addition, modifications may be made to adapt a
particular situation, material, composition of matter, method, or
process, within the scope of the claims, including variances or
tolerances attributable to manufacturing processes and techniques.
In particular, while the methods disclosed herein have been
described with reference to particular operations performed in a
particular order, it will be understood that these operations may
be combined, sub-divided, or re-ordered to form an equivalent
method and resultant structure consistent with the teachings of the
invention.
* * * * *