U.S. patent application number 12/965301 was filed with the patent office on 2011-04-07 for microfeature workpieces and methods for forming interconnects in microfeature workpieces.
This patent application is currently assigned to MICRON TECHNOLOGY, INC.. Invention is credited to Ross S. Dando, William M. Hiatt.
Application Number | 20110079900 12/965301 |
Document ID | / |
Family ID | 37804834 |
Filed Date | 2011-04-07 |
United States Patent
Application |
20110079900 |
Kind Code |
A1 |
Hiatt; William M. ; et
al. |
April 7, 2011 |
MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN
MICROFEATURE WORKPIECES
Abstract
Methods for forming interconnects in microfeature workpieces,
and microfeature workpieces having such interconnects are disclosed
herein. The microfeature workpieces may have a terminal and a
substrate with a first side carrying the terminal and a second side
opposite the first side. In one embodiment, a method includes (a)
constructing an electrically conductive interconnect extending from
the terminal to at least an intermediate depth in the substrate
with the interconnect electrically connected to the terminal, and
(b) removing material from the second side of the substrate so that
a portion of the interconnect projects from the substrate.
Inventors: |
Hiatt; William M.; (Eagle,
ID) ; Dando; Ross S.; (Nampa, ID) |
Assignee: |
MICRON TECHNOLOGY, INC.
Boise
ID
|
Family ID: |
37804834 |
Appl. No.: |
12/965301 |
Filed: |
December 10, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11217169 |
Sep 1, 2005 |
7863187 |
|
|
12965301 |
|
|
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Current U.S.
Class: |
257/737 ;
257/E23.068 |
Current CPC
Class: |
H01L 2224/13025
20130101; H01L 21/76898 20130101; H01L 23/481 20130101 |
Class at
Publication: |
257/737 ;
257/E23.068 |
International
Class: |
H01L 23/498 20060101
H01L023/498 |
Claims
1. A microfeature workpiece, comprising: a substrate having a first
side and a second side opposite the first side; a microelectronic
die formed in and/or on the substrate, the die including a terminal
at the first side of the substrate and an integrated circuit
operably coupled to the terminal; and an electrically conductive
interconnect extending from the terminal through the substrate and
projecting from the second side of the substrate, wherein the
interconnect is electrically coupled to the terminal and has an
exposed surface at the second side of the substrate.
2. The microfeature workpiece of claim 1 wherein: the substrate
further comprises a hole; the electrically conductive interconnect
comprises a conductive fill material in the hole and a conductive
layer in the hole between the conductive fill material and the
substrate; the conductive fill material and the conductive layer
each include an exposed surface; and the exposed surface of the
conductive fill material is recessed relative to the exposed
surface of the conductive layer.
3. The microfeature workpiece of claim 1, further comprising a
dielectric structure covering the second side of the substrate and
the portion of the interconnect projecting from the substrate.
4. The microfeature workpiece of claim 1, further comprising a
dielectric structure covering the second side of the substrate,
wherein the exposed surface of the interconnect is not covered by
the dielectric structure.
5. The microfeature workpiece of claim 1, further comprising a
dielectric structure covering the second side of the substrate and
having an exterior surface, wherein the exposed surface of the
interconnect is not covered by the dielectric structure, and
wherein a portion of the interconnect projects from the exterior
surface of the dielectric structure.
6. The microfeature workpiece of claim 1, further comprising a
dielectric structure covering the second side of the substrate and
having an exterior surface, wherein the exposed surface of the
interconnect is not covered by the dielectric structure, and
wherein the exposed surface of the interconnect is generally
coplanar with the exterior surface of the dielectric structure.
7. The microfeature workpiece of claim 1, further comprising a
layer of parylene disposed on the second side of the substrate.
8. The microfeature workpiece of claim 1, further comprising a
conductive member formed on the portion of the interconnect
projecting from the substrate.
9. The microfeature workpiece of claim 1, further comprising a
conductive cap formed on the portion of the interconnect projecting
from the substrate.
10. The microfeature workpiece of claim 1 wherein the interconnect
projects between approximately 5 and 10 microns from the
substrate.
11. The microfeature workpiece of claim 1 wherein: the substrate
further comprises a hole; the electrically conductive interconnect
comprises a conductive fill material in the hole, a conductive
layer in the hole between the conductive fill material and the
substrate, and a recess at the second side of the substrate; and
the workpiece further comprises a dielectric material disposed in
the recess.
12. A microfeature workpiece, comprising: a substrate having a
first side and a second side opposite the first side; a
microelectronic die formed in and/or on the substrate, the die
including a terminal at the first side of the substrate and an
integrated circuit operably coupled to the terminal; a hole
extending through the terminal and the substrate; a dielectric
layer on the second side of the substrate defining a plane; and an
electrically conductive interconnect including a conductive fill
material in the hole and a conductive layer in the hole between the
conductive fill material and the substrate, both the conductive
fill material and the conductive layer being electrically coupled
to the terminal and extending from the terminal through the
substrate and projecting from the substrate such that the
conductive fill material and the conductive layer intersect the
plane.
13. The microfeature workpiece of claim 12 wherein: the conductive
fill material and the conductive layer each include an exposed
surface; and the exposed surface of the conductive fill material is
recessed relative to the exposed surface of the conductive
layer.
14. The microfeature workpiece of claim 12 wherein: the conductive
fill material and the conductive layer each include an exposed
surface; the exposed surface of the conductive fill material is
recessed relative to the exposed surface of the conductive layer
such that the conductive fill material and the conductive layer
define a recess in the interconnect; and the dielectric layer
further includes a section disposed in the recess.
15. The microfeature workpiece of claim 12 wherein: the conductive
fill material and the conductive layer each include an exposed
surface; and the exposed surface of the conductive fill material is
generally coplanar with the exposed surface of the conductive
layer.
16. The microfeature workpiece of claim 12 wherein the dielectric
layer further covers the interconnect.
17. The microfeature workpiece of claim 12 wherein the dielectric
layer has an exterior surface, and wherein the interconnect
includes a portion projecting from the exterior surface.
18. The microfeature workpiece of claim 12 wherein the dielectric
layer has an exterior surface, and wherein the interconnect
includes an exposed surface generally coplanar with the exterior
surface.
19. The microfeature workpiece of claim 12, further comprising a
conductive member formed on the portion of the interconnect that
projects from the substrate.
20. A microfeature workpiece, comprising: a substrate having a
first side and a second side opposite the first side; a
microelectronic die formed in and/or on the substrate, the die
including a terminal at the first side of the substrate and an
integrated circuit operably coupled to the terminal; and an
electrically conductive interconnect including a conductive fill
material in the hole and a conductive layer in the hole between the
conductive fill material and the substrate, both the conductive
fill material and the conductive layer being electrically coupled
to the terminal and extending from the terminal through the
substrate and projecting from the substrate, wherein the conductive
fill material is recessed relative to the conductive layer at the
second side of the substrate.
21. The microfeature workpiece of claim 20 wherein the conductive
fill material and the conductive layer each include an exposed
surface.
22. The microfeature workpiece of claim 20, further comprising a
dielectric layer disposed on the second side of the substrate.
23. The microfeature workpiece of claim 20, further comprising a
dielectric layer disposed on the second side of the substrate and
including a section disposed in a recess defined by the conductive
fill material and the conductive layer.
24. The microfeature workpiece of claim 20, further comprising a
dielectric layer covering the interconnect.
25. The microfeature workpiece of claim 20, further comprising a
dielectric layer covering the second side of the substrate, wherein
the dielectric layer has an exterior surface and the interconnect
includes a portion projecting from the exterior surface.
26. The microfeature workpiece of claim 20, further comprising a
dielectric layer covering the second side of the substrate, wherein
the dielectric layer has an exterior surface and the interconnect
includes an exposed surface generally coplanar with the exterior
surface.
27. The microfeature workpiece of claim 20, further comprising a
conductive member formed on the portion of the interconnect that
projects from the substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of U.S. application Ser.
No. 11/217,169 filed Sep. 1, 2005, which is incorporated herein by
reference in its entirety.
TECHNICAL FIELD
[0002] The present invention relates to methods for forming
interconnects in microfeature workpieces and microfeature
workpieces formed using such methods.
BACKGROUND
[0003] Microelectronic devices, micromechanical devices, and other
devices with microfeatures are typically formed by constructing
several layers of components on a workpiece. In the case of
microelectronic devices, a plurality of dies are fabricated on a
single workpiece, and each die generally includes an integrated
circuit and a plurality of bond-pads coupled to the integrated
circuit. The dies are separated from each other and packaged to
form individual microelectronic devices that can be attached to
modules or installed in other products.
[0004] One aspect of fabricating and packaging such dies is forming
interconnects that electrically couple conductive components
located in different layers. In some applications, it may be
desirable to form interconnects that extend completely through the
dies or through a significant portion of the dies. Such
interconnects electrically couple bond-pads or other conductive
elements proximate to one side of the dies to conductive elements
proximate to the other side of the dies. Through-wafer
interconnects, for example, are constructed by forming deep vias on
the front side and/or backside of the workpiece and in alignment
with corresponding bond-pads at the front side of the workpiece.
The vias are often blind vias in that they are closed at one end.
The blind vias are then filled with a conductive fill material.
After further processing, the workpiece is thinned to reduce the
thickness of the final dies. Solder balls or other external
electrical contacts are subsequently attached to the through-wafer
interconnects at the backside and/or the front side of the
workpiece. The solder balls or external contacts can be attached
either before or after singulating the dies from the workpiece.
[0005] Conventional processes for forming external contacts on
through-wafer interconnects include (a) depositing a dielectric
layer on the backside of the workpiece, (b) forming a photoresist
on the dielectric layer, (c) patterning and developing the
photoresist, (d) etching the dielectric layer to form holes aligned
with corresponding interconnects, (e) removing the photoresist from
the workpiece, and (f) forming conductive external contacts in the
holes in the dielectric layer. One concern with forming external
contacts on the backside of a workpiece is that conventional
processes are relatively expensive because patterning the
photoresist requires a mask. Masks are expensive and time-consuming
to construct because they require very expensive photolithography
equipment to achieve the tolerances required in semiconductor
devices. Accordingly, there is a need to reduce the cost of forming
external contacts on workpieces with through-wafer
interconnects.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIGS. 1A-1I illustrate stages of a method for forming
interconnects in a microfeature workpiece in accordance with one
embodiment of the invention.
[0007] FIG. 1A is a schematic side cross-sectional view of a
portion of the workpiece at an intermediate stage after partially
forming a plurality of interconnects.
[0008] FIG. 1B is a schematic side cross-sectional view of the area
1B shown in FIG. 1A with the workpiece flipped over.
[0009] FIG. 1C is a schematic side cross-sectional view of the
portion of the workpiece after thinning the substrate from the
second side.
[0010] FIG. 1D is a schematic side cross-sectional view of the
portion of the workpiece after selectively removing additional
material from the second side of the substrate so that the
interconnect projects from the substrate.
[0011] FIG. 1E is a schematic side cross-sectional view of the area
1E shown in FIG. 1D after forming a recess in the second end
portion of the interconnect.
[0012] FIG. 1F is a schematic side cross-sectional view of the
portion of the workpiece after forming a dielectric structure
across the second side of the substrate and the second end portion
of the interconnect.
[0013] FIG. 1G is a schematic side cross-sectional view of the
portion of the workpiece after removing sections of the
interconnect and the dielectric structure.
[0014] FIG. 1H is a schematic side cross-sectional view of the
portion of the workpiece after removing the section of the first
dielectric layer from the recess in the interconnect.
[0015] FIG. 1I is a schematic side cross-sectional view of the
portion of the workpiece after forming a conductive member at the
second end portion of the interconnect.
[0016] FIGS. 2A-2C illustrate stages in a method for forming
interconnects in a microfeature workpiece in accordance with
another embodiment of the invention.
[0017] FIG. 2A is a schematic side cross-sectional view of a
portion of the workpiece at an intermediate stage after partially
forming an interconnect.
[0018] FIG. 2B is a schematic side cross-sectional view of the
portion of the workpiece after removing sections of the
interconnect and the dielectric structure.
[0019] FIG. 2C is a schematic side cross-sectional view of the
portion of the workpiece after forming the conductive member on the
exposed surface of the interconnect.
[0020] FIGS. 3A-3C illustrate stages in a method for forming
interconnects in a microfeature workpiece in accordance with
another embodiment of the invention.
[0021] FIG. 3A is a schematic side cross-sectional view of a
portion of the workpiece at an intermediate stage after partially
forming an interconnect.
[0022] FIG. 3B is a schematic side cross-sectional view of the
portion of the workpiece after removing sections of the
interconnect and the dielectric structure.
[0023] FIG. 3C is a schematic side cross-sectional view of the
workpiece after forming a conductive member on the exposed surface
of the interconnect.
DETAILED DESCRIPTION
A. Overview
[0024] The following disclosure describes several embodiments of
methods for forming interconnects in microfeature workpieces, and
microfeature workpieces having such interconnects. One aspect of
the invention is directed to methods of forming an interconnect in
a microfeature workpiece having a terminal and a substrate with a
first side carrying the terminal and a second side opposite the
first side. An embodiment of one such method includes (a)
constructing an electrically conductive interconnect extending from
the terminal to at least an intermediate depth in the substrate,
and (b) removing material from the second side of the substrate so
that a portion of the interconnect projects from the substrate. The
material can be removed from the second side of the substrate by
thinning the substrate so that a surface of the interconnect is
exposed and selectively etching the substrate so that the portion
of the interconnect projects from the substrate.
[0025] In another embodiment, a method includes providing a
microfeature workpiece having (a) a substrate with a first side and
a second side opposite the first side, (b) a terminal carried by
the first side of the substrate, and (c) an electrically conductive
interconnect extending from the terminal through the substrate and
projecting from the second side of the substrate. The method
further includes applying a dielectric layer to the second side of
the substrate and the portion of the interconnect projecting from
the second side of the substrate, and removing a section of the
dielectric layer to expose a surface of the interconnect with the
interconnect intersecting a plane defined by the remaining section
of the dielectric layer.
[0026] In another embodiment, a method includes forming an
electrically conductive interconnect having a first portion at the
terminal and a second portion at an intermediate depth in the
substrate. The electrically conductive interconnect is electrically
connected to the terminal. The method further includes thinning the
substrate from the second side to at least the second portion of
the interconnect, applying a dielectric layer to the second side of
the substrate and the second portion of the interconnect, and
exposing a surface of the second portion of the interconnect
without photolithography.
[0027] Another aspect of the invention is directed to microfeature
workpieces. In one embodiment, a microfeature workpiece includes a
substrate and a microelectronic die formed in and/or on the
substrate. The substrate has a first side and a second side
opposite the first side. The die includes a terminal at the first
side of the substrate and an integrated circuit operably coupled to
the terminal. The workpiece further includes an electrically
conductive interconnect extending from the terminal through the
substrate such that a portion of the interconnect projects from the
second side of the substrate. The interconnect is electrically
coupled to the terminal.
[0028] In another embodiment, a microfeature workpiece includes a
substrate and a microelectronic die formed in and/or on the
substrate. The substrate has a first side and a second side
opposite the first side. The die includes a terminal at the first
side of the substrate and an integrated circuit operably coupled to
the terminal. The workpiece further includes (a) a hole extending
through the terminal and the substrate, (b) a dielectric layer on
the second side of the substrate defining a plane, and (c) an
electrically conductive interconnect. The interconnect includes a
conductive fill material in the hole and a conductive layer in the
hole between the conductive fill material and the substrate. Both
the conductive fill material and the conductive layer are
electrically coupled to the terminal and extend from the terminal
through the substrate. Moreover, both the conductive fill material
and the conductive layer project from the substrate such that the
conductive fill material and the conductive layer intersect the
plane.
[0029] Specific details of several embodiments of the invention are
described below with reference to interconnects extending from a
terminal proximate to the front side of a workpiece, but the
methods and interconnects described below can be used for other
types of interconnects within microelectronic workpieces. Several
details describing well-known structures or processes often
associated with fabricating microelectronic devices are not set
forth in the following description for purposes of clarity. Also,
several other embodiments of the invention can have different
configurations, components, or procedures than those described in
this section. A person of ordinary skill in the art, therefore,
will accordingly understand that the invention may have other
embodiments with additional elements, or the invention may have
other embodiments without several of the elements shown and
described below with reference to FIGS. 1A-3C.
[0030] The term "microfeature workpiece" is used throughout to
include substrates upon which and/or in which microelectronic
devices, micromechanical devices, data storage elements, optics,
and other features are fabricated. For example, microfeature
workpieces can be semiconductor wafers, glass substrates,
dielectric substrates, or many other types of substrates. Many
features on such microfeature workpieces have critical dimensions
less than or equal to 1 .mu.m, and in many applications the
critical dimensions of the smaller features are less than 0.25
.mu.m or even less than 0.1 .mu.m. Where the context permits,
singular or plural terms may also include the plural or singular
term, respectively. Moreover, unless the word "or" is expressly
limited to mean only a single item exclusive from other items in
reference to a list of at least two items, then the use of "or" in
such a list is to be interpreted as including (a) any single item
in the list, (b) all of the items in the list, or (c) any
combination of the items in the list. Additionally, the term
"comprising" is used throughout to mean including at least the
recited feature(s) such that any greater number of the same
features and/or types of other features and components are not
precluded.
B. Embodiments of Methods for Forming Interconnects in Microfeature
Workpieces
[0031] FIGS. 1A-1I illustrate stages of a method for forming
interconnects in a microfeature workpiece 100 in accordance with
one embodiment of the invention. FIG. 1A, for example, is a
schematic side cross-sectional view of a portion of the workpiece
100 at an intermediate stage after partially forming a plurality of
interconnects 140. The workpiece 100 can include a substrate 110
and a plurality of microelectronic dies 120 formed in and/or on the
substrate 110. The substrate 110 has a first side 112 and a second
side 114 opposite the first side 112. The substrate 110 is
generally a semiconductor wafer, and the dies 120 are arranged in a
die pattern on the wafer. The individual dies 120 include
integrated circuitry 122 (shown schematically) and a plurality of
terminals 124 (e.g., bond-pads) electrically coupled to the
integrated circuitry 122. The terminals 124 shown in FIG. 1A are
external features at the first side 112 of the substrate 110. In
other embodiments, however, the terminals 124 can be internal
features that are embedded at an intermediate depth within the
substrate 110. Moreover, in additional embodiments, the dies 120
can have different features to perform different functions. For
example, the individual dies may further include an image sensor
(e.g., CMOS image sensor or CCD image sensor) for capturing
pictures or other images in the visible spectrum, or detecting
radiation in other spectrums (e.g., IR or UV ranges).
[0032] In previous processing steps, a first dielectric layer 130
was applied to the first side 112 of the substrate 110, and the
interconnects 140 were partially formed in the workpiece 100. The
first dielectric layer 130 can be a polyimide material or other
suitable nonconductive materials. For example, the first dielectric
layer 130 can be parylene, a low temperature chemical vapor
deposition (low temperature CVD) material such as silicon nitride
(Si.sub.3N.sub.4), silicon oxide (SiO.sub.2), and/or other suitable
materials. The foregoing list of dielectric materials is not
exhaustive. The conductive interconnects 140 extend from the first
dielectric layer 130 to an intermediate depth in the substrate 110.
As described in greater detail below with regard to FIG. 1B, the
conductive interconnects 140 can include several layers of
conductive material that are electrically coupled to corresponding
terminals 124. Suitable methods for forming the portion of the
interconnects 140 illustrated in FIG. 1A are disclosed in U.S.
patent application Ser. Nos. 10/713,878; 10/867,352; 10/879,398;
11/027,443; 11/056,211; 11/169,546; 11/217,877; and 11/218,243,
which are incorporated herein by reference. After partially forming
the interconnects 140, the workpiece 100 can optionally be attached
to a support member 190 with an adhesive 192 to provide rigidity to
the workpiece 100 during subsequent processing steps.
[0033] FIG. 1B is a schematic side cross-sectional view of the area
1B shown in FIG. 1A with the workpiece 100 flipped over. The
workpiece 100 includes an interconnect hole 180 extending from the
terminal 114 to an intermediate depth in the substrate 110, a
second dielectric layer 132 in the interconnect hole 180, and a
vent hole 182 extending from the interconnect hole 180 to the
second side 114 of the substrate 110. The second dielectric layer
132 electrically insulates components in the substrate 110 from the
interconnect 140. The second dielectric layer 132 can be an ALD
(atomic layer deposition) aluminum oxide material applied using a
suitable deposition process or another suitable low temperature CVD
oxide. In another embodiment, the second dielectric layer 132 can
include a silane-based and/or an aluminum-based oxide material. In
still further embodiments, the second dielectric layer 132 can
include other suitable dielectric materials.
[0034] The illustrated interconnect 140 is formed in the
interconnect hole 180 and has a first end portion 142 at the first
dielectric layer 130 and a second end portion 144 at an
intermediate depth in the substrate 110. The illustrated
interconnect 140 includes a diffusion barrier layer 150 deposited
over the second dielectric layer 132 in the hole 180, a seed layer
152 formed over the barrier layer 150 in the hole 180, a conductive
layer 154 deposited over the seed layer 152 in the hole 180, and a
conductive fill material 152 formed over the conductive layer 154
in the hole 180. The diffusion barrier layer 150 can be a layer of
tantalum that is deposited onto the workpiece 100 using physical
vapor deposition (PVD) and has a thickness of approximately 150
Angstroms. In other embodiments, the barrier layer 150 may be
deposited onto the workpiece 100 using other vapor deposition
processes, such as CVD, and/or may have a different thickness. In
either case, the barrier layer 150 is not limited to tantalum, but
rather may be composed of tungsten or other suitable materials that
help contain the conductive fill material 156 in the interconnect
hole 180.
[0035] The seed layer 152 can be deposited using vapor deposition
techniques, such as PVD, CVD, atomic layer deposition, and/or
plating. The seed layer 152 can be composed of Cu or other suitable
materials. The thickness of the seed layer 152 may be about 2000
Angstroms, but could be more or less depending on the depth and
aspect ratio of the hole 180. The conductive layer 154 can be Cu
that is deposited onto the seed layer 152 in an electroless plating
operation, electroplating operation, or another suitable method.
The thickness of the conductive layer 154 can be about 1 micron,
however, in other embodiments the conductive layer 154 can have a
different thickness and/or include other suitable materials. In
additional embodiments, the workpiece 100 may include a second
conductive layer (not shown) that is deposited over the conductive
layer 154 in the hole 180. The second conductive layer can be Ni or
other suitable materials that function as a wetting agent for
facilitating deposition of subsequent materials into the hole
180.
[0036] The conductive fill material 156 can include Cu, Ni, Co, Ag,
Au, SnAgCu solder, AuSn solder, a solder having a different
composition, or other suitable materials or alloys of materials
having the desired conductivity. The conductive fill material 156
may be deposited into the hole 180 using plating processes, solder
wave processes, screen printing processes, reflow processes, vapor
deposition processes, or other suitable techniques. In other
embodiments, the interconnects may have a different structure. For
example, the interconnects may have additional layers in lieu of or
in addition to the layers described above.
[0037] FIG. 1C is a schematic side cross-sectional view of the
portion of the workpiece 100 after thinning the substrate 110 from
the second side 114. The substrate 110 can be thinned by grinding,
dry etching, chemical etching, chemical polishing,
chemical-mechanical polishing, or other suitable processes. The
thinning process may also remove a section of the second end
portion 114 of the interconnect 140. For example, in one
embodiment, the initial thickness of the substrate 110 is
approximately 750 microns and the interconnect 140 extends to an
intermediate depth of approximately 150 microns in the substrate
110, and the post-thinning thickness T of the substrate 110 is
approximately 140 microns. These thicknesses can be different in
other embodiments. After thinning the workpiece 100, the
illustrated interconnect 140 includes an exposed surface 146 at the
second end portion 144.
[0038] FIG. 1D is a schematic side cross-sectional view of the
portion of the workpiece 100 after selectively removing additional
material from the second side 114 of the substrate 110 so that the
interconnect 140 projects from the substrate 110. The additional
material can be removed via a plasma etch with SF.sub.6 or another
suitable etchant that is selective to silicon. Alternatively, the
additional material can be removed with other processes. In either
case, after thinning the substrate 110, the second end portion 144
of the interconnect 140 projects a first distance D.sub.1 from the
second side of the substrate 110. In several embodiments, the first
distance D.sub.1 is between approximately 5 and 10 microns,
although the first distance D.sub.1 can be less than 5 microns or
more than 10 microns in other embodiments. The first distance
D.sub.1 is selected based on the subsequent processing and
application requirements.
[0039] FIG. 1E is a schematic side cross-sectional view of the area
1E shown in FIG. 1D after forming a recess 158 in the second end
portion 144 of the interconnect 140. In the illustrated embodiment,
the recess 158 is formed by removing a portion of the conductive
fill material 156 from the interconnect 140. The conductive fill
material 156 can be removed by a wet etch process with an etchant
that is selective to the conductive fill material 156 and,
consequently, removes the conductive fill material 156 at a faster
rate than the seed and/or conductive layers 152 and/or 154. The
illustrated recess 158 extends from the surface 146 of the
interconnect 140 to a surface 157 of the conductive fill material
156, and has a depth D.sub.2 less than the first distance D.sub.1.
The depth D.sub.2 of the recess 158 is selected based on the
subsequent processing and application requirements. In other
embodiments, such as the embodiments described below with reference
to FIGS. 2A-3C, the interconnects may not include a recess in the
second end portion 144.
[0040] FIG. 1F is a schematic side cross-sectional view of the
portion of the workpiece 100 after forming a dielectric structure
170 across the second side 114 of the substrate 110 and the second
end portion 144 of the interconnect 140. The illustrated dielectric
structure 170 includes a first dielectric layer 172 and a second
dielectric layer 174 deposited on the first dielectric layer 172.
The first dielectric layer 172 can be parylene HT and have a
thickness of approximately 0.5 micron. In other embodiments, other
dielectric materials can be used and/or have different thicknesses.
The second dielectric layer 174 can be an oxide such as silicon
oxide (SiO.sub.2) and/or other suitable materials that are
deposited by chemical vapor deposition and/or other suitable
processes. In additional embodiments, the dielectric structure 170
can include a different number of layers.
[0041] FIG. 1G is a schematic side cross-sectional view of the
portion of the workpiece 100 after removing sections of the
interconnect 140 and the dielectric structure 170. The sections of
the interconnect 140 and the dielectric structure 170 can be
removed by grinding, dry etching, chemical etching, chemical
polishing, chemical-mechanical polishing, or other suitable
processes. In the illustrated embodiment, the workpiece 100 is
polished to remove portions of the second dielectric layer 132, the
barrier layer 150, the seed layer 152, the conductive layer 154,
the first dielectric layer 172, and the second dielectric layer
174. The volume of material removed is selected so that (a) the
recess 158 in the interconnect 140 has a desired depth D.sub.3, and
(b) the interconnect 140 projects a desired distance D.sub.4 from
an exterior surface 175 of the dielectric structure 170. In other
embodiments, such as the embodiment described below with reference
to FIGS. 3A-3C, the interconnect may not project from the exterior
surface 175 of the dielectric structure 170. In either case, the
interconnect 140 intersects a plane defined by the dielectric
structure 170.
[0042] FIG. 1H is a schematic side cross-sectional view of the
portion of the workpiece 100 after removing the section of the
first dielectric layer 172 from the recess 158 in the interconnect
140. The section of the first dielectric layer 172 can be removed
from the recess 158 by a plasma etching process (e.g., O.sub.2
plasma) or another suitable method that selectively removes the
first dielectric layer 172 without significantly effecting the
dielectric structure 170 formed on the substrate 110.
[0043] FIG. 1I is a schematic side cross-sectional view of the
portion of the workpiece 100 after forming a conductive member 160
on the second end portion 144 of the interconnect 140. The
illustrated conductive member 160 is a cap disposed in the recess
158 and extending over the barrier layer 150, the seed layer 152,
and the conductive layer 154. The cap projects a desired distance
D.sub.5 from the substrate 110 and forms an external contact for
connection to an external device. The conductive member 160 can be
electrolessly plated onto the second end portion 144 of the
interconnect 140 or formed using other suitable processes. The
conductive member 160 can include Ni or other suitable conductive
materials. In other embodiments, the interconnect 140 may not
include the conductive member 160. For example, the second end
portion 144 of the interconnects 140 can be attached directly to an
external device, or a conductive coupler (e.g., a solder ball) can
be attached directly to the second end portion 144.
[0044] One feature of the method illustrated in FIGS. 1A-1I is that
the interconnect 140 projects from the substrate 110. As a result,
the section of the dielectric structure 170 covering the
interconnect 140 can be removed by a simple polishing process
without exposing the backside of the substrate 110. The resulting
exposed surface 146 on the interconnect 140 may form an external
contact to which an external device can be attached. Alternatively,
the conductive member 160 can be disposed on the exposed surface
146 and form the external contact. In either case, an advantage of
this feature is that the illustrated method does not require
expensive and time-consuming photolithography processes to form
external contacts on the backside of the workpiece 100.
[0045] Another advantage of the method illustrated in FIGS. 1A-1I
is that the interconnect 140 can be sized to project a desired
distance from the external surface 175 of the dielectric structure
170. The distance can be selected based on the application
requirements for the die 110. For example, in applications in which
the die 110 is stacked on another die, the distance may be selected
to provide a desired gap between the two dies.
C. Additional Embodiments of Methods for Forming Interconnects in
Microfeature Workpieces
[0046] FIGS. 2A-2C illustrate stages in a method for forming
interconnects in a microfeature workpiece 200 in accordance with
another embodiment of the invention. FIG. 2A, for example, is a
schematic side cross-sectional view of a portion of the workpiece
200 at an intermediate stage after partially forming an
interconnect 240. The illustrated workpiece 200 is generally
similar to the workpiece 100 described above with reference to
FIGS. 1A-1F. For example, the illustrated workpiece 200 includes a
substrate 110, an interconnect 240 extending through and projecting
from the substrate 110, and a dielectric structure 270 formed over
the substrate 110 and the interconnect 240. The illustrated
interconnect 240, however, does not include a recess at the second
end portion 244.
[0047] FIG. 2B is a schematic side cross-sectional view of the
portion of the workpiece 200 after removing sections of the
interconnect 240 and the dielectric structure 270. The sections of
the interconnect 240 and the dielectric structure 170 can be
removed by grinding, dry etching, chemical etching, chemical
polishing, chemical-mechanical polishing, or other suitable
processes. The volume of the material removed is selected so that
the interconnect 240 projects a desired distance D.sub.6 from an
exterior surface 275 of the dielectric structure 270. The
illustrated interconnect 240 includes a generally planar exposed
surface 246 extending across the barrier layer 150, the seed layer
152, the conductive layer 154, and the conductive fill material
156.
[0048] FIG. 2C is a schematic side cross-sectional view of the
portion of the workpiece 200 after forming a conductive member 260
on the generally planar exposed surface 246 of the interconnect
240. The conductive member 260 forms part of the electrically
conductive interconnect 240 and, accordingly, is electrically
coupled to the terminal 114 (FIG. 1B).
[0049] FIGS. 3A-3C illustrate stages in a method for forming
interconnects in a microfeature workpiece 300 in accordance with
another embodiment of the invention. FIG. 3A, for example, is a
schematic side cross-sectional view of a portion of the workpiece
300 at an intermediate stage after partially forming an
interconnect 340. The illustrated workpiece 300 is generally
similar to the workpiece 200 described above with reference to FIG.
2A. For example, the illustrated workpiece 300 includes a substrate
110, an interconnect 340 extending through and projecting from the
substrate 110, and a dielectric structure 370 formed over the
substrate 110 and the interconnect 340.
[0050] FIG. 3B is a schematic side cross-sectional view of the
portion of the workpiece 300 after removing sections of the
interconnect 340 and the dielectric structure 370. The sections of
the interconnect 340 and the dielectric structure 370 are removed
to form a generally planar surface across the workpiece 300 such
that an exposed surface 346 of the interconnect 340 is generally
coplanar with an exterior surface 375 of the dielectric structure
370.
[0051] FIG. 3C is a schematic side cross-sectional view of the
workpiece 300 after forming a conductive member 360 on the exposed
surface 346 of the interconnect 340. The conductive member 360
forms part of the electrically conductive interconnect 340 and,
accordingly, is electrically coupled to the terminal 114 (FIG.
1B).
[0052] From the foregoing, it will be appreciated that specific
embodiments of the invention have been described herein for
purposes of illustration, but that various modifications may be
made without deviating from the spirit and scope of the invention.
For example, many of the elements of one embodiment can be combined
with other embodiments in addition to or in lieu of the elements of
the other embodiments. Accordingly, the invention is not limited
except as by the appended claims.
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