U.S. patent application number 12/583804 was filed with the patent office on 2010-03-04 for circuit substrate having power/ground plane with grid holes.
Invention is credited to Hung-Hsiang Cheng, Chih-Yi Huang.
Application Number | 20100051341 12/583804 |
Document ID | / |
Family ID | 41723654 |
Filed Date | 2010-03-04 |
United States Patent
Application |
20100051341 |
Kind Code |
A1 |
Cheng; Hung-Hsiang ; et
al. |
March 4, 2010 |
Circuit substrate having power/ground plane with grid holes
Abstract
The present invention relates to a circuit substrate having a
first conductive layer. The first conductive layer includes at
least one power/ground plane. The power/ground plane includes at
least one plane edge and plurality of grid lines. Each grid line
has a width. The grid lines intersect each other to define a
plurality of first grid holes, wherein the distance between the
first grid hole that is closest to the plane edge and the plane
edge is 1.5 times the width. Thus, the influence on the resistance
of power signal and ground signal caused by the first grid holes is
reduced, power integrity is improved, and heat generation is
reduced.
Inventors: |
Cheng; Hung-Hsiang;
(Kaohsiung, TW) ; Huang; Chih-Yi; (Kaohsiung,
TW) |
Correspondence
Address: |
MCCRACKEN & FRANK LLP
311 S. WACKER DRIVE, SUITE 2500
CHICAGO
IL
60606
US
|
Family ID: |
41723654 |
Appl. No.: |
12/583804 |
Filed: |
August 26, 2009 |
Current U.S.
Class: |
174/261 |
Current CPC
Class: |
H01L 23/13 20130101;
H01L 23/49816 20130101; H01L 2924/0002 20130101; H05K 2201/09681
20130101; H05K 1/0253 20130101; H05K 1/0224 20130101; H01L 23/49827
20130101; H05K 1/0265 20130101; H01L 2924/0002 20130101; H05K
2201/093 20130101; H01L 2924/00 20130101; H01L 23/49838
20130101 |
Class at
Publication: |
174/261 |
International
Class: |
H05K 1/11 20060101
H05K001/11 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 27, 2008 |
TW |
097132717 |
Claims
1. A circuit substrate, having a first conductive layer, wherein
the first conductive layer comprises: at least one power/ground
plane, having at least one plane edge and a plurality of grid
lines, wherein each grid line has a width, the grid lines intersect
each other to define a plurality of first grid holes, and the
distance between the first grid hole that is closest to the plane
edge and the plane edge is greater than 1.5 times the width.
2. The circuit substrate as claimed in claim 1, wherein the
material of the power/ground plane is copper.
3. The circuit substrate as claimed in claim 1, wherein the first
conductive layer further comprises a layout, and the layout
comprises a plurality of fingers, a plurality of I/O ball pads, a
plurality of power/ground ball pads and a plurality of conductive
traces, wherein the I/O ball pads are electrically connected to
some of the fingers by some of the conductive traces, the
power/ground ball pads are disposed on the power/ground plane, and
the power/ground plane are electrically connected to the other
fingers by the other conductive traces.
4. The circuit substrate as claimed in claim 3, wherein the fingers
are electrically connected to a chip, and a plurality of solder
balls are formed on the I/O ball pads and the power/ground ball
pads.
5. The circuit substrate as claimed in claim 3, wherein the
power/ground ball pads are disposed on a position of the
power/ground plane that does not have the first grid holes.
6. The circuit substrate as claimed in claim 3, further comprising
a second conductive layer and a dielectric layer, wherein the
second conductive layer is disposed under the first conductive
layer and has a plurality of second grid holes and a projection
layout, the projection layout is a region formed by projecting the
layout of the first conductive layer onto the second conductive
layer, the dielectric layer is disposed between the first
conductive layer and the second conductive layer and has a
thickness, and the distance between the second grid hole of the
second conductive layer that is closest to the projection layout
and the projection layout is greater than the thickness of the
dielectric layer.
7. A circuit substrate, having a first conductive layer, wherein
the first conductive layer comprises: at least one power/ground
plane, having at least one plane edge and a grid distribution area,
wherein the grid distribution area has a plurality of grid lines
and a border, each grid line has a width, the grid lines intersect
each other to define a plurality of first grid holes, and the
distance between the border of the grid distribution area and the
plane edge of the power/ground plane is greater than 1.5 times the
width.
8. The circuit substrate as claimed in claim 7, wherein the
material of the power/ground plane is copper.
9. The circuit substrate as claimed in claim 7, wherein the first
conductive layer further comprises a layout, and the layout
comprises a plurality of fingers, a plurality of I/O ball pads, a
plurality of power/ground ball pads and a plurality of conductive
traces, wherein the I/O ball pads are electrically connected to
some of the fingers by some of the conductive traces, the
power/ground ball pads are disposed on the power/ground plane, and
the power/ground plane are electrically connected to the other
fingers by the other conductive traces.
10. The circuit substrate as claimed in claim 9, wherein the
fingers are electrically connected to a chip, and a plurality of
solder balls are formed on the I/O ball pads and the power/ground
ball pads.
11. The circuit substrate as claimed in claim 9, wherein the
power/ground ball pads are disposed on a position of the
power/ground plane that does not have the first grid holes.
12. The circuit substrate as claimed in claim 9, further comprising
a second conductive layer and a dielectric layer, wherein the
second conductive layer is disposed under the first conductive
layer and has a plurality of second grid holes and a projection
layout, the projection layout is a region formed by projecting the
layout of the first conductive layer onto the second conductive
layer, the dielectric layer is disposed between the first
conductive layer and the second conductive layer and has a
thickness, and the distance between the second grid hole of the
second conductive layer that is closest to the projection layout
and the projection layout is greater than the thickness of the
dielectric layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a circuit substrate, and
more particularly to a circuit substrate having a power/ground
plane with grid holes.
[0003] 2. Description of the Related Art
[0004] FIG. 1 shows a top view of a conventional circuit substrate.
The conventional circuit substrate 1 is a substrate for window ball
grid array (WBGA) package, which comprises a window 11, a plurality
of power/ground planes 12, a plurality of fingers 13, a plurality
of I/O ball pads 14, a plurality of power/ground ball pads 15 and a
plurality of conductive traces 16. The fingers 13 are disposed at
the periphery of the window 11. Each power/ground plane 12 has a
plurality of grid lines 121, and the grid lines 121 intersect each
other to define a plurality of grid holes 122. The material of the
power/ground planes 12 is copper, and the grid lines 121 and the
grid holes 122 are formed by etching a large area made of copper.
For reliability, the grid lines 121 and the grid holes 122 are
evenly distributed, so as to increase air dissipation and the
bonding strength between two laminated layers.
[0005] The I/O ball pads 14 are electrically connected to some of
the fingers 13 by some of the conductive traces 16. The
power/ground ball pads 15 are disposed on the power/ground planes
12, and the power/ground planes 12 are electrically connected to
the other fingers 13 by the other conductive traces 16. The fingers
13 are electrically connected to a chip (not shown), and a
plurality of solder balls (not shown) are formed on the I/O ball
pads 14 and the power/ground ball pads 15.
[0006] The disadvantage of the conventional circuit substrate 1 is
described as follows. Since the power/ground plane 12 is an
important source of power signal and ground signal, the grid holes
122 disposed thereon will influence the resistance of power signal
and ground signal, thereby reducing power integrity.
[0007] Therefore, it is necessary to provide a circuit substrate
having a power/ground plane with grid holes to solve the above
problem.
SUMMARY OF THE INVENTION
[0008] The present invention is directed to a circuit substrate
having at least one power/ground plane. The power/ground plane has
at least one plane edge and a plurality of grid lines. Each grid
line has a width. The grid lines intersect each other to define a
plurality of first grid holes, and the distance between the first
grid hole that is closest to the plane edge and the is plane edge
is more than 1.5 times the width. Thus, the influence on the
resistance of power signal and ground signal caused by the first
grid holes is reduced, power integrity is improved, and heat
generation is reduced.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 is a top view of a conventional circuit
substrate;
[0010] FIG. 2 is a top view of a circuit substrate having a
plurality of power/ground planes with grid holes according to the
present invention;
[0011] FIG. 3 is a cross-sectional view of the circuit substrate
having a power/ground plane with grid holes according to the
present invention; and
[0012] FIG. 4 is a top view of a second conductive layer of the
circuit substrate in FIG. 3.
DETAILED DESCRIPTION OF THE INVENTION
[0013] FIG. 2 shows a top view of a circuit substrate having a
plurality of power/ground planes with grid holes according to the
present invention. In the embodiment, the circuit substrate 2 is a
substrate for window ball grid array (WBGA) package. It is
understood that the circuit substrate 2 may be other types of
circuit substrate. The circuit substrate 2 is, for example, a
single-layered substrate or a multi-layered substrate. The circuit
substrate 2 comprises a first conductive layer 20. The first
conductive layer 20 comprises a window 21, a plurality of
power/ground planes 22 and a layout. The layout comprises a
plurality of fingers 23, a plurality of I/O ball pads 24, a
plurality of power/ground ball pads 25 and a plurality of
conductive traces 26. The fingers 23 are disposed at the periphery
of the window 21.
[0014] The I/O ball pads 24 are electrically connected to some of
the fingers 23 by some of the conductive traces 26. The
power/ground ball pads 25 are disposed on the power/ground planes
22, and the power/ground planes 22 are electrically connected to
the other fingers 23 by the other conductive traces 26. The fingers
23 are electrically connected to a chip (not shown), and a
plurality of solder balls (not shown) are formed on the I/O ball
pads 24 and the power/ground ball pads 25.
[0015] Each power/ground plane 22 has at least one plane edge 223
and a grid distribution area 28. The grid distribution area 28 has
a plurality of grid lines 221 and a border 281. The grid lines 221
intersect each other to define a plurality of first grid holes 222.
Preferably, the material of the power/ground planes 22 is copper,
and the grid lines 221 and the first grid holes 222 are formed by
etching a large area made of copper. Each grid line 221 has a width
W, that is, the distance between two adjacent first grid holes 222
is W.
[0016] In the present invention, the distance D1 between the first
grid hole 222 that is closest to the plane edge 223 and the plane
edge 223 is more than 1.5 times the width W; in other words, if the
width W is 100 .mu.m, the distance D1 is 150 .mu.m. Alternatively,
the distance D2 between the border 281 of the grid distribution
area 28 and the plane edge 223 of the power/ground planes 22 is
more than 1.5 times the width W. Therefore, the circuit substrate 2
has a solid portion, which spans a distance of more than 1.5 times
W measured from the plane edge 223 of the power/ground planes 22
inward, and the solid portion does not have any first grid holes.
The principle of the design is to reserve the solid portion, which
spans a distance of more than 1.5 times W inside the plane edge
223, for a return current path 27 of power signal and ground
signal, and the return current path 27 does not have any first grid
holes. Therefore, the influence on the resistance of power signal
and ground signal caused by the first grid holes is reduced, power
integrity is improved, and heat generation is reduced.
[0017] Preferably, the power/ground ball pads 25 are disposed on a
position of the power/ground planes 22 that does not have the first
grid holes.
[0018] FIG. 3 shows a cross-sectional view of the circuit substrate
having a power/ground plane with grid holes according to the
present invention. The circuit substrate 3 is a double-layered
substrate, which comprises a first conductive layer 31, a second
conductive layer 32 and a dielectric layer 33. The top view of the
first conductive layer 31 is the same as that of the first
conductive layer 20 in FIG. 2. The first conductive layer 31 has at
least one power/ground plane 22 and a layout. The second conductive
layer 32 is disposed under the first conductive layer 31. The
dielectric layer 33 is disposed between the first conductive layer
31 and the second conductive layer 32, and has a thickness T.
[0019] In the first conductive layer 31, each power/ground plane 22
has at least one plane edge 223, and a grid distribution area 28.
The grid distribution area 28 has a plurality of grid lines 221 and
a border 281. The grid lines 221 intersect each other to define a
plurality of first grid holes 222. Preferably, the material of the
power/ground plane 22 is copper, and the grid lines 221 and the
first grid holes 222 are formed by etching a large area made of
copper. Each grid line 221 has a width W, that is, the distance
between two adjacent first grid holes 222 is W. The distance D1
between the first grid hole 222 that is closest to the plane edge
223 and the plane edge 223 is more than 1.5 times the width W; in
other words, if the width W is 100 .mu.m, the distance D1 is 150
.mu.m. Alternatively, the distance D2 between the border 281 of the
grid distribution area 28 and the plane edge 223 of the
power/ground plane 22 is more than 1.5 times the width W.
[0020] FIG. 4 shows a top view of the second conductive layer of
the circuit substrate in FIG. 3. The second conductive layer 32 has
a window 321, a plurality of second grid holes 322 and a projection
layout 323. The position of the window 321 corresponds to the
window 21 of the first conductive layer 20. Preferably, the second
conductive layer 32 is a whole piece of copper foil, and the second
grid holes 322 are formed by selectively etching the whole piece of
copper foil. The projection layout 323 is a region formed by
projecting the layout of the first conductive layer 20 onto the
second conductive layer 32. In other words, the projection layout
323 is merely a region encompassed by the "mirror image" of the
layout of the first conductive layer 20; it does not have an actual
layout. The distance D3 between the second grid hole 322 of the
second conductive layer 32 that is closest to the projection layout
323 and the projection layout 323 is greater than the thickness T
of the dielectric layer 33. Therefore, the second conductive layer
32 has a solid portion, which spans a distance of more than T
measured from the edge of the projection layout 323 inward, and the
solid portion does not have any second grid holes.
[0021] While several embodiments of the present invention have been
illustrated and described, various modifications and improvements
can be made by those skilled in the art. The embodiments of the
present invention are therefore described in an illustrative but
not restrictive sense. It is intended that the present invention
should not be limited to the particular forms as illustrated, and
that all modifications which maintain the spirit and scope of the
present invention are within the scope defined in the appended
claims.
* * * * *