U.S. patent application number 12/165340 was filed with the patent office on 2009-12-31 for method of fabricating stacked wire bonded semiconductor package with low profile bond line.
Invention is credited to Shrikar Bhagath, Hem Takiar.
Application Number | 20090325344 12/165340 |
Document ID | / |
Family ID | 41447955 |
Filed Date | 2009-12-31 |
United States Patent
Application |
20090325344 |
Kind Code |
A1 |
Takiar; Hem ; et
al. |
December 31, 2009 |
METHOD OF FABRICATING STACKED WIRE BONDED SEMICONDUCTOR PACKAGE
WITH LOW PROFILE BOND LINE
Abstract
A method of fabricating a low profile semiconductor package is
disclosed including at least first and second stacked semiconductor
die mounted to a substrate. The first and/or second semiconductor
die may be fabricated with a plurality of redistribution pads
formed over and electrically coupled to a plurality of bond pads.
After the semiconductor die are formed and diced from the wafer,
the die may be mounted to the substrate using a low profile reverse
wire bond according to the present invention. In particular, a
wedge bond may be formed between the wire and the redistribution
pad without having to use a second wire bond ball on the die bond
pad as in conventional reverse ball bonding processes.
Inventors: |
Takiar; Hem; (Fremont,
CA) ; Bhagath; Shrikar; (San Jose, CA) |
Correspondence
Address: |
VIERRA MAGEN/SANDISK CORPORATION
575 MARKET STREET, SUITE 2500
SAN FRANCISCO
CA
94105
US
|
Family ID: |
41447955 |
Appl. No.: |
12/165340 |
Filed: |
June 30, 2008 |
Current U.S.
Class: |
438/109 ;
257/E21.509 |
Current CPC
Class: |
H01L 2224/48844
20130101; H01L 2924/01079 20130101; H01L 2224/4569 20130101; H01L
2224/48647 20130101; H01L 2924/01019 20130101; H01L 2224/04042
20130101; H01L 2224/05556 20130101; H01L 2224/48465 20130101; H01L
2225/06562 20130101; H01L 2924/014 20130101; H01L 24/97 20130101;
H01L 2224/32014 20130101; H01L 2924/01322 20130101; H01L 2224/48091
20130101; H01L 2924/01005 20130101; H01L 2924/01033 20130101; H01L
2924/181 20130101; H01L 24/06 20130101; H01L 24/85 20130101; H01L
2224/48644 20130101; H01L 2224/48747 20130101; H01L 2224/48855
20130101; H01L 2924/01006 20130101; H01L 2224/05644 20130101; H01L
2224/48227 20130101; H01L 24/45 20130101; H01L 2224/05655 20130101;
H01L 2924/01078 20130101; H01L 24/48 20130101; H01L 25/0657
20130101; H01L 2224/48755 20130101; H01L 2924/1433 20130101; H01L
2924/01013 20130101; H01L 2224/73265 20130101; H01L 2924/00014
20130101; H01L 2924/01028 20130101; H01L 2224/05647 20130101; H01L
2224/45144 20130101; H01L 24/73 20130101; H01L 2224/32145 20130101;
H01L 2224/4554 20130101; H01L 2224/48479 20130101; H01L 2924/14
20130101; H01L 24/49 20130101; H01L 2224/45124 20130101; H01L
2224/45147 20130101; H01L 2224/85201 20130101; H01L 2225/06575
20130101; H01L 2924/01082 20130101; H01L 2924/01029 20130101; H01L
2224/05554 20130101; H01L 2224/48655 20130101; H01L 2225/06527
20130101; H01L 2224/2919 20130101; H01L 2224/85986 20130101; H01L
2224/49175 20130101; H01L 2224/023 20130101; H01L 2224/05553
20130101; H01L 2224/48847 20130101; H01L 2224/85205 20130101; H01L
24/05 20130101; H01L 2224/97 20130101; H01L 2224/45015 20130101;
H01L 2224/85051 20130101; H01L 2225/0651 20130101; H01L 2224/48471
20130101; H01L 2224/45124 20130101; H01L 2924/00014 20130101; H01L
2224/45144 20130101; H01L 2924/00014 20130101; H01L 2224/45147
20130101; H01L 2924/00014 20130101; H01L 2224/48091 20130101; H01L
2924/00014 20130101; H01L 2224/48091 20130101; H01L 2924/00014
20130101; H01L 2224/05644 20130101; H01L 2924/01013 20130101; H01L
2224/05644 20130101; H01L 2924/01047 20130101; H01L 2224/05644
20130101; H01L 2924/01079 20130101; H01L 2224/05644 20130101; H01L
2924/01028 20130101; H01L 2224/85986 20130101; H01L 2224/85051
20130101; H01L 2224/85186 20130101; H01L 2224/48479 20130101; H01L
2224/48471 20130101; H01L 2224/2919 20130101; H01L 2924/0665
20130101; H01L 2224/97 20130101; H01L 2224/73265 20130101; H01L
2224/73265 20130101; H01L 2224/32145 20130101; H01L 2224/48227
20130101; H01L 2924/00014 20130101; H01L 2224/78 20130101; H01L
2924/00 20130101; H01L 2224/48465 20130101; H01L 2224/48227
20130101; H01L 2224/48465 20130101; H01L 2224/48227 20130101; H01L
2924/00 20130101; H01L 2224/49175 20130101; H01L 2224/48227
20130101; H01L 2924/00 20130101; H01L 2224/49175 20130101; H01L
2224/48471 20130101; H01L 2924/00 20130101; H01L 2224/49175
20130101; H01L 2224/48465 20130101; H01L 2924/00 20130101; H01L
2224/85205 20130101; H01L 2224/45147 20130101; H01L 2924/00
20130101; H01L 2224/85205 20130101; H01L 2224/45144 20130101; H01L
2924/00 20130101; H01L 2924/00 20130101; H01L 2224/85205 20130101;
H01L 2224/45124 20130101; H01L 2924/00 20130101; H01L 2924/00
20130101; H01L 2224/85205 20130101; H01L 2224/48465 20130101; H01L
2924/00 20130101; H01L 2924/00 20130101; H01L 2224/48227 20130101;
H01L 2224/48479 20130101; H01L 2224/48471 20130101; H01L 2924/00
20130101; H01L 2224/48227 20130101; H01L 2224/48471 20130101; H01L
2924/00 20130101; H01L 2224/48844 20130101; H01L 2924/00 20130101;
H01L 2224/45144 20130101; H01L 2924/00 20130101; H01L 2224/48479
20130101; H01L 2224/45147 20130101; H01L 2924/00 20130101; H01L
2224/48855 20130101; H01L 2924/00 20130101; H01L 2924/00 20130101;
H01L 2924/00 20130101; H01L 2224/48644 20130101; H01L 2924/00
20130101; H01L 2924/00 20130101; H01L 2924/00 20130101; H01L
2224/48647 20130101; H01L 2924/00 20130101; H01L 2924/00 20130101;
H01L 2924/00 20130101; H01L 2224/48655 20130101; H01L 2924/00
20130101; H01L 2224/48227 20130101; H01L 2224/48847 20130101; H01L
2924/00 20130101; H01L 2224/45144 20130101; H01L 2924/00 20130101;
H01L 2224/48747 20130101; H01L 2924/00 20130101; H01L 2224/45144
20130101; H01L 2924/00 20130101; H01L 2224/48744 20130101; H01L
2924/00 20130101; H01L 2224/48227 20130101; H01L 2924/00012
20130101; H01L 2224/48755 20130101; H01L 2924/00 20130101; H01L
2224/45144 20130101; H01L 2924/00 20130101; H01L 2224/48479
20130101; H01L 2224/48471 20130101; H01L 2224/45144 20130101; H01L
2924/00 20130101; H01L 2224/48479 20130101; H01L 2224/48471
20130101; H01L 2224/45124 20130101; H01L 2924/00 20130101; H01L
2224/48479 20130101; H01L 2224/48471 20130101; H01L 2224/45147
20130101; H01L 2924/00 20130101; H01L 2224/48479 20130101; H01L
2224/48471 20130101; H01L 2224/48227 20130101; H01L 2924/00
20130101; H01L 2224/73265 20130101; H01L 2224/32145 20130101; H01L
2224/48227 20130101; H01L 2924/00012 20130101; H01L 2224/73265
20130101; H01L 2224/32225 20130101; H01L 2224/48227 20130101; H01L
2924/00012 20130101; H01L 2224/97 20130101; H01L 2224/73265
20130101; H01L 2224/32225 20130101; H01L 2224/48227 20130101; H01L
2924/00 20130101; H01L 2224/48465 20130101; H01L 2224/48091
20130101; H01L 2924/00 20130101; H01L 2224/45015 20130101; H01L
2924/00 20130101; H01L 2224/45144 20130101; H01L 2924/00015
20130101; H01L 2224/45147 20130101; H01L 2924/00015 20130101; H01L
2224/48844 20130101; H01L 2924/00 20130101; H01L 2224/48847
20130101; H01L 2924/00 20130101; H01L 2224/48855 20130101; H01L
2924/00 20130101; H01L 2924/00014 20130101; H01L 2224/05556
20130101; H01L 2924/181 20130101; H01L 2924/00012 20130101; H01L
2224/97 20130101; H01L 2224/73265 20130101; H01L 2224/32145
20130101; H01L 2224/48227 20130101; H01L 2924/00 20130101; H01L
2224/023 20130101; H01L 2924/0001 20130101 |
Class at
Publication: |
438/109 ;
257/E21.509 |
International
Class: |
H01L 21/60 20060101
H01L021/60 |
Claims
1. A method of fabricating a semiconductor device, comprising the
steps of: (a) affixing a first semiconductor die to a substrate,
the first semiconductor die including a pad for receiving a wire
bond and the substrate including a pad for receiving a wire bond;
(b) wire bonding a first end of a wire to a pad on the substrate by
forming an end of the wire into a ball and coupling the ball to the
substrate pad; and (c) wire bonding a second portion of the wire,
spaced from the first end of the wire, directly to a pad on the
first semiconductor die.
2. A method as recited in claim 1, wherein said step (b) of wire
bonding a first end of a wire to a pad on the substrate comprises
the step of bonding the ball to the substrate pad by applying one
or more of heat, force and ultrasonic energy at the interface
between the ball and substrate pad.
3. A method as recited in claim 1, wherein said step (c) of wire
bonding a second portion of the wire directly to a pad on the first
semiconductor die comprises the step of pulling the bond wire into
contact with an upper surface of the first semiconductor die.
4. A method as recited in claim 3, further comprising the step of
providing electrical insulation between the wire and the first
semiconductor die by a passivation layer formed on the first
semiconductor die at a location where the wire contacts the first
semiconductor die.
5. A method as recited in claim 1, wherein said step (c) of wire
bonding a second portion of the wire directly to a pad on the first
semiconductor die comprises the step of forming a wedge bond
between the wire and pad on the first semiconductor die.
6. A method as recited in claim 1, wherein said step (c) of wire
bonding a second portion of the wire directly to a pad on the first
semiconductor die comprises the step of forming a wire bond having
a height above the first semiconductor die approximately equal to
the diameter of the wire.
7. A method as recited in claim 1, wherein said step (c) of wire
bonding a second portion of the wire directly to a pad on the first
semiconductor die comprises the step of bonding the wire to the
semiconductor die pad by applying one or more of heat, force and
ultrasonic energy at the interface between the wire and
semiconductor die pad.
8. A method as recited in claim 1, further comprising the step (d)
of affixing an intermediate layer to a surface of the first
semiconductor die opposite a surface of the first semiconductor die
affixed to the substrate.
9. A method as recited in claim 8, wherein said step (d) of
affixing the intermediate layer to a surface of the first
semiconductor die comprises the step of affixing an intermediate
layer having a thickness slightly greater than a diameter of the
wire.
10. A method as recited in claim 8, wherein said step (d) of
affixing the intermediate layer to a surface of the first
semiconductor die comprises the step of affixing an intermediate
layer on the first semiconductor die at an area spaced from the
semiconductor die pad.
11. A method as recited in claim 8, wherein said step (d) of
affixing the intermediate layer to a surface of the first
semiconductor die comprises the step of affixing an adhesive epoxy
on the first semiconductor die covering the semiconductor pad and
wire bond.
12. A method as recited in claim 8, further comprising the step (e)
of affixing a second semiconductor die to the intermediate
layer.
13. A method as recited in claim 12, further comprising the steps
of: (f) wire bonding a first end of a wire to a second pad on the
substrate by forming an end of the wire into a ball and coupling
the ball to the second substrate pad; and (g) wire bonding a second
portion of the wire, spaced from the first end of the wire,
directly to a pad on the second semiconductor die.
14. A method as recited in claim 1, further comprising the step (h)
of affixing a second semiconductor die to the spacer layer.
15. A method as recited in claim 14, further comprising the steps
of: (j) wire bonding a first end of a wire to a second pad on the
substrate by forming an end of the wire into a ball and coupling
the ball to the second substrate pad; and (k) wire bonding a second
portion of the wire, spaced from the first end of the wire,
directly to a pad on the second semiconductor die.
16. A method of fabricating a semiconductor device, the
semiconductor device including a semiconductor die and a substrate,
the semiconductor die including a redistribution pad deposited over
a die bond pad and having a larger size than the bond pad, and the
substrate including a contact pad, the method comprising the steps
of: (a) affixing the semiconductor die to the substrate; (b) wire
bonding a first end of a wire to the contact pad on the substrate
by forming an end of the wire into a ball and coupling the ball to
the contact pad; and (c) wire bonding a second portion of the wire,
spaced from the first end of the wire, directly to a pad on the
semiconductor in a wedge bond, said step (c) including the step of
pulling the wire taut against a surface of the semiconductor
die.
17. A method as recited in claim 16, further comprising the step of
providing electrical insulation between the wire and the
semiconductor die by a passivation layer formed on the
semiconductor die at a location where the wire contacts the
semiconductor die.
18. A method as recited in claim 16, wherein said step (c) of wire
bonding a second portion of the wire directly to a pad on the
semiconductor die comprises the step of forming a wire bond having
a height above the semiconductor die approximately equal to the
diameter of the wire.
19. A method as recited in claim 16, wherein said step (c) of wire
bonding a second portion of the wire directly to a pad on the
semiconductor die comprises the step of bonding the wire to the
semiconductor die pad by applying one or more of heat, force and
ultrasonic energy at the interface between the wire and
semiconductor die pad.
20. A method of fabricating a semiconductor device, comprising the
steps of: (a) forming a semiconductor die including the step of
defining die bond pads on a surface of the semiconductor die; (b)
enlarging an electrically conductive area of each die bond pad
formed in said step (a); (c) affixing the semiconductor die to a
substrate, the substrate including a contact pad for a receiving a
wire bond; (d) wire bonding a first end of a wire to a contact pad
on the substrate by forming an end of the wire into a ball and
coupling the ball to the contact pad; (e) wire bonding a second
portion of the wire, spaced from the first end of the wire,
directly to the electrically conductive area on the semiconductor
die in a wedge bond; and (f) encapsulating the semiconductor die
and at least a portion of the substrate in molding compound.
21. A method as recited in claim 20, wherein said step (b)
comprises the steps of: i. forming a first passivation layer on the
surface of the semiconductor die, the first passivation layer
having openings corresponding to the positions of the contact pads;
ii. depositing redistribution pads over the contact pads, the
redistribution pads having a larger area than the contact pads; and
iii. forming a second passivation layer on the surface of the first
passivation layer, the second passivation layer having openings
corresponding to the positions of the redistribution pads.
22. A method as recited in claim 20, wherein said step (b)
comprises the step of increasing the length but not the width of
the contact pads.
23. A method as recited in claim 20, wherein said step (e) of wire
bonding a second portion of the wire directly to the electrically
conductive area on the semiconductor die comprises the step of
pulling the bond wire taut against an upper surface of the first
semiconductor die.
24. A method as recited in claim 23, further comprising the step of
providing electrical insulation between the wire and the
semiconductor die by a passivation layer formed on the
semiconductor die at a location where the wire contacts the first
semiconductor die.
25. A method as recited in claim 20, wherein said step (e) of wire
bonding a second portion of the wire directly to the electrically
conductive area on the semiconductor die comprises the step of
forming a wedge bond between the wire and the conductive area on
the semiconductor die.
26. A method as recited in claim 20, wherein said step (e) of wire
bonding a second portion of the wire directly to the electrically
conductive area on the semiconductor die comprises the step of
forming a wire bond having a height above the semiconductor die
approximately equal to the diameter of the wire.
27. A method as recited in claim 20, wherein said step (e) of wire
bonding a second portion of the wire directly to the electrically
conductive area on the semiconductor die comprises the step of
bonding the wire to the conductive area by applying one or more of
heat, force and ultrasonic energy at the interface between the wire
and semiconductor die pad.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The following application is cross-referenced and
incorporated by reference herein in its entirety:
[0002] U.S. patent application Ser. No. ______ [Attorney Docket No.
SAND-01319US1], entitled "Stacked Wire Bonded Semiconductor Package
with Low Profile Bond Line," by Takiar, et al., filed on even date
herewith.
BACKGROUND OF THE INVENTION
[0003] 1. Field of the Invention
[0004] Embodiments of the present invention relate to a low profile
semiconductor device and method of fabricating same.
[0005] 2. Description of the Related Art
[0006] The strong growth in demand for portable consumer
electronics is driving the need for high-capacity storage devices.
Non-volatile semiconductor memory devices, such as flash memory
storage cards, are becoming widely used to meet the ever-growing
demands on digital information storage and exchange. Their
portability, versatility and rugged design, along with their high
reliability and large capacity, have made such memory devices ideal
for use in a wide variety of electronic devices, including for
example digital cameras, digital music players, video game
consoles, PDAs and cellular telephones.
[0007] While a wide variety of packaging configurations are known,
flash memory storage cards may in general be fabricated as
system-in-a-package (SiP) or multichip modules (MCM), where a
plurality of die are mounted on a substrate. The substrate may in
general include a rigid, dielectric base having a conductive layer
etched on one or both sides. Electrical connections are formed
between the die and the conductive layer(s), and the conductive
layer(s) provide an electric lead structure for connection of the
die to a host device. Once electrical connections between the die
and substrate are made, the assembly is then typically encased in a
molding compound to provide a protective package.
[0008] An edge view of a conventional semiconductor package 20
(without molding compound) is shown in prior art FIGS. 1 and 2.
Typical packages include a plurality of semiconductor die 22, 24
mounted to a substrate 26. Although not shown in FIGS. 1 and 2, the
semiconductor die are formed with die bond pads (40 in FIGS. 3 and
4). Substrate 26 may be formed of an electrically insulating core
sandwiched between upper and lower conductive layers. The upper
and/or lower conductive layers may be etched to form a conductance
patterns including electrical leads and contact pads (52, FIGS. 3
and 4). Wire bonds are soldered to the die bond pads 40 of the
semiconductor die 22, 24 and contact pads 52 of the substrate 26 as
explained hereinafter to electrically couple the semiconductor die
to the substrate.
[0009] It is known to layer semiconductor die on top of each other
either with an offset (prior art FIG. 1) or in a stacked
configuration (prior art FIG. 2). In the offset configuration of
FIG. 1, the die are stacked with an offset so that the bond pads of
the next lower die are left exposed. Such configurations are shown
for example in U.S. Pat. No. 6,359,340 to Lin, et al., entitled,
"Multichip Module Having A Stacked Chip Arrangement." An offset
configuration provides an advantage of convenient access of the
bond pads on each of the semiconductor die. However, the offset
requires a greater footprint on the substrate, where space is at a
premium.
[0010] In the stacked configuration of FIG. 2, two or more
semiconductor die are stacked directly on top of each other,
thereby taking up less footprint on the substrate as compared to an
offset configuration. However, in a stacked configuration, space
must be provided between adjacent semiconductor die for the bond
wires 30. In addition to the height of the bond wires 30
themselves, additional space must be left above the bond wires, as
contact of the bond wires 30 of one die with the next die above may
result in an electrical short. As shown in FIG. 2, it is therefore
known to provide a dielectric spacer layer 34 to provide enough
room for the wire bond 30 to be bonded to the die bond pad on the
lower die 24. Instead of a spacer layer 34, it is also known to
bury the wire bond loops between two adjacent semiconductor die
within an adhesive layer between the respective die. Such
configurations are shown for example in U.S. Pat. No. 6,388,313 to
Lee et al., entitled, "Multi-Chip Module," and U.S. Pat. No.
7,037,756 to Jiang et al., entitled, "Stacked Microelectronic
Devices and Methods of Fabricating Same."
[0011] There is an ever-present drive to increase storage capacity
within memory modules. One method of increasing storage capacity is
to increase the number of memory die used within the package. In
portable memory packages, the number of die which may be used is
limited by the thickness of the package. There is accordingly a
keen interest in decreasing the thickness of the contents of a
package while increasing memory density.
[0012] The package 20 shown in prior art FIGS. 1 and 2 requires
that additional space be provided within the package to accommodate
the height of the wire bond loops. Further details relating to
conventional processes for forming wire bond loops 30 are explained
with reference to the perspective views of prior art FIGS. 3 and 4.
FIGS. 3 and 4 show lower semiconductor die 24 wire bonded to
substrate 26 via bond wires 30. The structure affixed atop
semiconductor die 24 can be another semiconductor die, such as die
22 of FIG. 1, or the structure can be a spacer layer, such as layer
34 of FIG. 2.
[0013] FIG. 3 shows bond wires 30 formed by a ball bonding process.
This process uses a wire bonding device referred to as a wire
bonding capillary. A length of wire (typically gold or copper) is
fed through a central cavity of the wire bonding capillary. The
wire protrudes through a tip of the capillary, where a high-voltage
electric charge is applied to the wire from a transducer associated
with the capillary tip. The electric charge melts the wire at the
tip and the wire forms into a ball (38 in FIG. 3) owing to the
surface tension of the molten metal.
[0014] As the ball solidifies, the capillary is lowered to the
surface of a die bond pad 40 formed on the surface of semiconductor
die 24. The surface of die 24 may be heated to facilitate a better
bond. The wire bond ball 38 is deposited on the die bond pad 40
under a load, while the transducer applies ultrasonic energy. The
combined heat, pressure, and ultrasonic energy create a bond
between the wire bond ball 38 and the die bond pad 40.
[0015] The wire bonding capillary is then pulled up and away from
the surface of semiconductor die 24, as wire is payed out through
the capillary. The capillary then moves over to a contact pad 44
receiving the second end of the wire bond on the substrate 26. The
second bond, referred to as a wedge or tail bond, is then formed on
contact pad 44 again using heat, pressure and ultrasonic energy,
but instead of forming a ball, the wire is crushed under pressure
to make the second bond. The wire bonding device then pays out a
small length of wire and tears the wire from the surface of the
second bond. The small tail of wire hanging from the end of the
capillary is then used to form the wire bond ball 38 for the next
subsequent wire bond. The above-described cycle can be repeated
about 20 to 30 times per second until all wire bond loops 30 are
formed between the semiconductor die and the substrate. It is
understood that there may be many more wire bond loops 30 than are
shown in FIGS. 3 and 4.
[0016] Due to the fact that the wire 30 must be pulled upwards from
ball 38 on each wire bond loop 30, the wire bonds shown in FIG. 3
formed by the ball bonding process have a relatively large height.
As indicated above, this height adds to the overall thickness of
the package where space is at a premium. Prior art FIG. 4 is a
perspective view of die 24, substrate 26 and wire bonds 30 formed
by a reverse ball bonding process. In a reverse ball bonding
process, a ball 50 is initially formed on the die bond pads 40 of
semiconductor die 24. Namely, the capillary forms the ball and
bonds it to the bond pad 40, but pulls away without paying out
wire. Thereafter, to form a first wire bond loop, a second ball 52
is formed on a contact pad 44 of the substrate, and the capillary
pulls up and away from the ball 52 while paying out wire. The
capillary then bonds the wire 30 to the corresponding ball 50 on
the die bond pad 40 using a wedge bond. As the capillary attaches
the wire 30 to the ball 50 using a flat wedge bond, the wire bond
has a lower profile than in the forward ball bonding process of
FIG. 3, where the wire was lifted up and away from the ball 38 on
the die bond pads.
[0017] Conventionally, the ball 50 is required on die bond pads 40
in the reverse ball bonding process of FIG. 4 for at least two
reasons. First, unlike the substrate contact pads 44, the die bond
pads 40 are too small to receive a wedge bond. Second, the die bond
pads are recessed slightly below the upper surface of the
semiconductor die, further preventing the capillary from forming a
wedge bond directly to the die bond pads. This problem is solved in
the prior art by first affixing the balls 50 to the die bond pads
40 of die 22 and then wedge bonding to the balls 50 in a reverse
ball bonding process.
SUMMARY OF THE INVENTION
[0018] An embodiment of the present invention relates to a low
profile semiconductor package including at least first and second
stacked semiconductor die mounted to a substrate. The first and/or
second semiconductor die may be fabricated with a plurality of
redistribution pads formed over and electrically coupled to a
plurality of bond pads. The redistribution pads may be formed by
redistribution layer (RDL) technology to overlay and increase the
size of the semiconductor die bond pads. An electrically insulating
passivation layer may cover the upper surface of the die with
openings where the redistribution pads are located.
[0019] After the semiconductor die are formed and diced from the
wafer, the die may be mounted to the substrate using a low profile
reverse wire bond according to the present invention. In
particular, a capillary device forms a ball at the end of the wire
which is bonded to a substrate pad. The capillary pulls up and away
from the bonded ball while paying out wire. The capillary then
bonds the wire to a designated redistribution pad on die using a
low height wedge bond. In accordance with the present invention,
the wedge bond may be formed between the wire and the
redistribution pad without having to use a second wire bond ball on
the die bond pad as in conventional reverse ball bonding processes.
Thus, the height required by the additional ball used in
conventional reverse ball bonding processes may be saved. Moreover,
the passivation layer provides electrical insulation, and allows
the bond wire to be pulled taut against the upper surface of the
semiconductor die without electrical shorting between the wire and
semiconductor die.
[0020] Once a first semiconductor die is wire bonded to the
substrate, one or more additional semiconductor die may be stacked
thereon and wire bonded to the substrate. One or more of the
semiconductor die in the die stack may be wire bonded using the low
height reverse wire bond process according to the present invention
as described above. The die may be stacked in either an offset
configuration, or stacked in a completely overlapping
configuration. In this latter embodiment, the die may be separated
by an intermediate layer, which may be a rigid spacer layer or a
curable epoxy adhesive.
DESCRIPTION OF THE DRAWINGS
[0021] FIG. 1 is a prior art edge view of a conventional
semiconductor device including a pair of semiconductor die stacked
in an offset relation.
[0022] FIG. 2 is a prior art edge view of a conventional
semiconductor device including a pair of semiconductor die stacked
in an overlapping relation and separated by a spacer layer.
[0023] FIG. 3 is a prior art partial perspective view of a
conventional semiconductor device including a semiconductor die
mounted and wire bonded to a substrate.
[0024] FIG. 4 is a prior art partial perspective view of a
conventional semiconductor device including a semiconductor die
mounted and wire bonded to a substrate using a reverse ball bonding
process.
[0025] FIG. 5 is a flowchart for forming a semiconductor die
according to embodiments of the present invention.
[0026] FIG. 6 is a top view of a semiconductor wafer from which a
plurality of semiconductor die according to embodiments of the
present invention may be fabricated.
[0027] FIG. 7 is a top view of a semiconductor die during
fabrication.
[0028] FIG. 8 is a top view of an alternative semiconductor die
during fabrication.
[0029] FIG. 9 is a top view of a semiconductor die during
fabrication.
[0030] FIG. 10 is an edge view of a semiconductor die during
fabrication.
[0031] FIG. 11 is a top view of a semiconductor die during
fabrication including redistribution pads.
[0032] FIG. 12 is an edge view of a semiconductor die during
fabrication including redistribution pads.
[0033] FIG. 13 is a top view of a semiconductor die upon completion
of fabrication including redistribution pads.
[0034] FIG. 15 is a top view of a semiconductor die upon completion
of fabrication including redistribution pads according to an
alternative embodiment.
[0035] FIG. 16 is a flowchart showing the fabrication of a
semiconductor device according to the present invention.
[0036] FIG. 17 is an edge view of a semiconductor device during
fabrication including a die wire bonded to a substrate.
[0037] FIG. 18 is a perspective view of a semiconductor device
during fabrication including a die wire bonded to a substrate.
[0038] FIG. 19 is a perspective view of a semiconductor device
during fabrication including a die wire bonded to a substrate and
an intermediate layer mounted to the semiconductor die.
[0039] FIG. 20 is an edge view of a finished semiconductor device
according to an embodiment of the present invention.
[0040] FIG. 21 is an edge view of a finished semiconductor device
according to an alternative embodiment of the present
invention.
DETAILED DESCRIPTION
[0041] Embodiments will now be described with reference to FIGS. 5
through 21, which relate to a low profile semiconductor package. It
is understood that the present invention may be embodied in many
different forms and should not be construed as being limited to the
embodiments set forth herein. Rather, these embodiments are
provided so that this disclosure will be thorough and complete and
will fully convey the invention to those skilled in the art.
Indeed, the invention is intended to cover alternatives,
modifications and equivalents of these embodiments, which are
included within the scope and spirit of the invention as defined by
the appended claims. Furthermore, in the following detailed
description of the present invention, numerous specific details are
set forth in order to provide a thorough understanding of the
present invention. However, it will be clear to those of ordinary
skill in the art that the present invention may be practiced
without such specific details.
[0042] A process for forming semiconductor die in accordance with
the present invention will now be described with reference to the
flowchart of FIG. 5, and the various top and edge views of FIGS. 6
through 15. FIG. 6 shows a top view of a semiconductor wafer 100
for batch processing a plurality of semiconductor die 102 (one of
which is labeled in FIG. 6). Each die 102 may be formed with bond
pads 104 as shown for example in the enlarged view of die 102 in
FIG. 7. Bond pads 104 are used to electrically couple the
semiconductor die 102 to another semiconductor die, or to a printed
circuit board, leadframe or other substrate as explained
hereinafter. While bond pads 104 are shown along a single edge of
die 102 in FIG. 7, it is understood that the bond pads 104 may be
formed along two opposed or adjacent edges as shown in FIG. 8. It
is also contemplated that the bond pads 104 may be formed along
three edges or all four edges of each die 102 in alternative
embodiments. It is understood that the number of bond pads 104
along a given edge of the semiconductor die 102 may be many more
than is shown in the figures.
[0043] Referring now to the flowchart of FIG. 5, the integrated
circuit components of semiconductor die 102 may be formed on wafer
100 in step 200 by known processes such as film deposition,
photolithography, patterning, and diffusion of impurities. Die bond
pads 104 may be formed in respective die in step 202 by known
processes including but not limited to plating, evaporation, screen
printing, or various deposition processes. A backgrind process may
be performed on wafer 100 in step 204 as is known in the art to
thin the die 102 to the desired thickness. The respective
semiconductor die may then be tested in step 208.
[0044] In accordance with the present invention, each of the bond
pads 104 is enlarged by forming a redistribution pad over the bond
pads 104. The following steps are described with respect to a
single die 102, but it is understood that the following steps are
applied to each die 102 on wafer 100. In step 210 and as shown in
the top and edge views of FIGS. 9 and 10, a passivation layer 106
may be applied to the semiconductor die 102, initially covering the
entire surface of the die 102. Passivation layer 106 may be any
number of dielectric materials, such as for example photo-definable
benzocyclobutane or other known suitable materials, applied in a
known process. In a step 212, passivation layer 106 may be etched
to expose all existing die bond pads 104 on semiconductor die 102
as best seen in FIG. 10. Passivation layer 106 may be etched using
known photolithography and etching techniques to expose die bond
pads 104 on semiconductor die 102.
[0045] Referring now to the top and edge views of FIGS. 11 and 12,
in step 214, an electrical conductor may be deposited on the die
bond pads 104 exposed in the etching process of step 212 to form a
redistribution pad 110 on the bond pads 104. The electrical
conductor may for example be gold, aluminum, copper, nickel or
alloys thereof. In embodiments using for example gold, a barrier
metal may be deposed between the bond pads and the gold layer to
enhance bonding and conductive properties of the redistribution pad
110. The redistribution pads 110 may be applied on bond pads 104 by
known deposition processes, such as for example sputtering.
[0046] Referring now to the top and edge views of FIGS. 13 and 14,
in step 214, a second passivation layer 112 may next be applied to
the top surface of semiconductor die 102, initially covering all of
the redistribution pads 110. Passivation layer 112 may be the same
as passivation layer 106 described above. In step 216, passivation
layer 112 may be etched to expose the final locations of the
redistribution pads 110 on the semiconductor die 102. The second
passivation layer 112 may be etched in step 218 using known
photolithography and etching techniques.
[0047] Bond pads 104 may have a width of approximately 60 to 70
microns (.mu.m), and a length of approximately 60 .mu.m to 70
.mu.m. The final exposed redistribution pads 110 over the bond pads
104 may have a width equal to approximately 60 .mu.m to 100 .mu.m,
and more particularly 80 .mu.m to 100 .mu.m (space between bond
pads allowing). The final exposed redistribution pads 110 may have
a length of 150 .mu.m to 300 .mu.m, and more particularly, 200
.mu.m to 250 .mu.m. It is understood that the length and width of
the redistribution pads may be smaller or larger than that in
alternative embodiments. The redistribution pads 110 may be spaced
the same distance from an edge 102a of the die 102 as are the bond
pads 104. However, it is understood that the redistribution pads
110 may be spaced a lesser or greater distance from edge 102a than
the bond pads 104. A portion 112a of the second passivation layer
112 exists on a top surface of the semiconductor die 102 at the
edge 102a. The portion 112a prevents shorting of a wire bond
against the top surface of the semiconductor die as explained
hereinafter.
[0048] In a step 220, the respective semiconductor die may be
tested, and the die 102 may be singulated from wafer 100 in a step
222. It is understood that the type of semiconductor die which may
be formed as described above may be any of a variety of
semiconductor die, including flash memory die and controller die
such as ASICs. The above-described steps are one of many possible
processes for forming redistribution pads 110 over bond pads
104.
[0049] In the embodiments described above, the redistribution pads
110 are formed directly over their corresponding bond pads 104.
However, in an alternative embodiment, it is contemplated that a
redistribution pad 110 may be spaced from its corresponding bond
pad 104. Such an embodiment is shown for example in FIG. 15. Here,
the spaced bond pads 104 may be coupled to their corresponding
repositioned redistribution pads 110 by conductive paths 116 formed
by conventional RDL techniques when the redistribution pad is
formed.
[0050] A process for forming a semiconductor package in accordance
with the present invention using the semiconductor die 102
described above will now be explained with reference to the
flowchart of FIG. 16, and the various views of FIGS. 17 through 21.
Referring initially to the edge and perspective views of FIGS. 17
and 18, a first semiconductor die 102 may be mounted on a substrate
120 in a step 300. The die 102 may be mounted to substrate 120 via
a die attach adhesive in a known adhesive or eutectic die bond
process. Although not shown, substrate 120 may be part of a panel
of substrates so that the semiconductor packages according to the
present invention may be batch processed for economies of scale.
Although fabrication of a single semiconductor package is described
below, it is understood that the following description may apply to
all packages formed on the substrate panel.
[0051] Although not critical to the present invention, substrate
120 may be a variety of different chip carrier mediums, including a
PCB, a leadframe or a tape automated bonded (TAB) tape. Where
substrate 120 is a PCB, the substrate may be formed of a core
having top and/or bottom conductive layers formed thereon. The core
may be various dielectric materials such as for example, polyimide
laminates, epoxy resins including FR4 and FR5, bismaleimide
triazine (BT), and the like.
[0052] The conductive layers may be formed of copper or copper
alloys, plated copper or plated copper alloys, Alloy 42
(42FE/58NI), copper plated steel or other metals or materials known
for use on substrates. The conductive layers may be etched into a
conductance pattern as is known for communicating signals between
the semiconductor die 102 and an external device (not shown).
Substrate 120 may additionally include exposed metal portions
forming contact pads 122 on an upper surface of the substrate 120.
Where the semiconductor package is a land grid array (LGA) package,
contact fingers (not shown) may also be defined on a lower surface
of the substrate 120. The contact pads 122 and/or contact fingers
may be plated with one or more gold layers, for example in an
electroplating process as is known in the art.
[0053] After semiconductor die 102 is affixed to substrate 120 in
step 300, bond wires 130 may be attached between redistribution
pads 110 on die 102 and contact pads 122 on substrate 120 in a
reverse ball bonding process in steps 302-304. In step 302, a wire
bonding capillary device of known construction (not shown) may form
and deposit a wire bond ball 134 on a contact pad 122. The ball 134
may be applied to the contact pad 122 under a load, while the
transducer applies ultrasonic energy. The combined heat, pressure,
and ultrasonic energy create a bond between the wire bond ball 134
and the contact pad 122. In step 304, the capillary pulls up and
away from the ball 134 while paying out wire. The capillary then
bonds the wire 130 to the corresponding redistribution pad 110 on
die 102 using a low height wedge bond. The wire 130 may be applied
to the redistribution pad 110 under a load, while the transducer
applies ultrasonic energy. The combined heat, pressure, and
ultrasonic energy create a bond between the wire 130 and the
redistribution pad 110.
[0054] In accordance with the present invention, the wedge bond may
be formed between the wire 130 and the redistribution pad 110
without having to use a second wire bond ball on the die bond pad
as in conventional reverse ball bonding processes. In particular,
given the large size of the redistribution pad 110, the pad 110 may
receive the wedge bond in the reverse ball bond process without
needing a wire bond ball formed thereon. Therefore, wire bond 130
may be provided at a lower height than is found in conventional
semiconductor packages. Removing the ball found on the bond pads in
a conventional reverse bonded semiconductor package allows the
height of the wire bond on the semiconductor die to be reduced 30
.mu.m to 50 .mu.m. Moreover, referring specifically to FIG. 17, as
the passivation layer 112 includes portion 112a on an upper surface
of the semiconductor die 102 between the redistribution pad 110 and
the front edge 102a of the die, the wire bond 130 may be pulled
taut against the portion 112a of the passivation layer 112, thus
effectively reducing the height of the wire bond to the thickness
of the wire 130. The electrically insulating portion 112a prevents
the wire bond 130 from electrically shorting against the surface of
die 102.
[0055] In the embodiments shown in the figures, wire bonds 130 are
provided along a single edge of die 102. In alternative embodiments
of the present invention, wire bonds 130 as described above may be
provided along one or more of two sides, three sides or all four
sides of die 102.
[0056] In embodiments where multiple die are stacked in a
completely overlapping relation, an intermediate layer 140 may be
applied onto the exposed surface of die 102 in step 308. In the
embodiment shown in FIGS. 19 and 20, the intermediate layer 140 may
be a dielectric spacer that is applied over a portion of the upper
surface of die 102 so as to leave the contact pads 122 and wire
bonds affixed thereto exposed. The thickness of the intermediate
layer need only be slightly greater than the height of the wire
bond on die 102. In embodiments, the bond wire may have a thickness
of approximately 25 .mu.m, and the thickness of intermediate layer
140 may be for example 30 .mu.m to 40 .mu.m. It is understood that
these dimensions are by way of example only, and may vary above or
below the stated range in alternative embodiments. The spacer layer
may be applied as a rigid material, or the spacer layer may be
applied as a soft material and later cured to a rigid material.
[0057] After the intermediate layer 140 is affixed to the die 102,
a second die 102 may be affixed atop the intermediate layer 140 in
step 310 and as shown in FIG. 20. In the embodiment shown, the
second semiconductor die 102 may also include redistribution pads
110 and be wire bonded to the substrate 120 in step 310 using the
same reverse ball bonding process as described above in steps 302
and 304. Thus, as shown in FIG. 20, both semiconductor die 102 in
the die stack may include low height wire bonds that are pulled
taut against the upper surface of the respective die. It is
understood that only one of the semiconductor die 102 in the die
stack may include redistribution pads 110 and ultra-low height
reverse wire bonds, while the other die may include a conventional
die affixed by a conventional wire bond process.
[0058] Embodiments of the present invention may include only the
pair of semiconductor die 102. However, in further embodiments,
more than two semiconductor die 102 may be stacked atop each other.
In such embodiments, as indicated by the dashed arrow in FIG. 16,
step 308 of applying an intermediate layer 140, step 310 of
attaching an additional die and step 312 of wire bonding the
additional die may be repeated for each additional semiconductor
die stacked on the die stack. One or more of the semiconductor die
in the completed die stack may include redistribution pads 110 and
an ultra-low reverse wire bond.
[0059] In the above-described embodiments, the bond wires may be
uncoated gold, though it may alternatively be copper, aluminum or
other metals. In a further embodiment of the present invention, the
bond wires may be pre-insulated with polymeric insulation that
makes the surface of the wire electrically non-conductive. Such
pre-insulated bond wire would allow the wire to be pulled tight
against the upper surface of the die 102 without the need for
passivation layer portion 112a at the edge of the die. Two examples
of a pre-insulated bond wire which is suitable for use in the
present invention are disclosed in U.S. Pat. No. 5,396,104,
entitled, "Resin Coated Bonding Wire, Method Of Manufacturing The
Same, And Semiconductor Device," and U.S. Published Patent
Application No. 2004/0124545, entitled, "High Density Integrated
Circuits And The Method Of Packaging the Same," both of which are
incorporated by reference herein in their entirety. In further
embodiments, both passivation layer portion 112a and pre-insulation
on bond wires 130 may be omitted. In such embodiments, a small
space may be provided between the wire bond and the upper surface
of the die to which the wire bond is affixed so as to prevent
electrical shorting of the wire bond against the semiconductor
die.
[0060] As further shown in FIG. 20, after forming the die stack and
electrically coupling the die stack to the substrate 120, the die
stack may be encased within the molding compound 150 in step 316,
and singulated from the panel in step 318, to form a finished
semiconductor die package 160. Molding compound 150 may be a known
epoxy such as for example available from Sumitomo Corp. and Nitto
Denko Corp., both having headquarters in Japan. In some
embodiments, the finished package 160 may optionally be enclosed
within a lid in step 320.
[0061] In the embodiment shown in FIG. 20, the intermediate layer
140 is a dielectric spacer layer positioned between adjacent
semiconductor die so as to leave the redistribution pads exposed.
In an alternative embodiment shown in FIG. 21, the intermediate
layer 140 may alternatively be an electrically insulative adhesive
epoxy of known composition which may extend to the edge 102a of the
semiconductor die 102 and cover the redistribution pads 110 and a
portion of the wire bond 130. Such an embodiment is shown in FIG.
21. Further details relating to such an electrically insulative
adhesive epoxy are disclosed in U.S. patent application Ser. No.
11/566,097, entitled "Method Of Fabricating A Film-On-Wire Bond
Semiconductor Device," (Applicant Docket No. SDA-1046), which
application is incorporated by reference herein in its entirety.
The intermediate layer 140 may be formed according to any of the
embodiments disclosed in the above-referenced application.
[0062] In a further alternative embodiment including an offset die
stack (not shown), the intermediate layer 140 may be omitted and
the package may include a second die mounted directly to the first
die. In such an embodiment, one or both of the die in the stack may
include redistribution pads 110 and ultra-low reverse wire bonds as
described above.
[0063] In embodiments, the semiconductor die 102 used within
package 160 may include one or more flash memory chips, and
possibly a controller such as an ASIC, so that the package 160 may
be used as a flash memory device. It is understood that the package
160 may include semiconductor die configured to perform other
functions in further embodiments of the present invention.
[0064] The foregoing detailed description of the invention has been
presented for purposes of illustration and description. It is not
intended to be exhaustive or to limit the invention to the precise
form disclosed. Many modifications and variations are possible in
light of the above teaching. The described embodiments were chosen
in order to best explain the principles of the invention and its
practical application to thereby enable others skilled in the art
to best utilize the invention in various embodiments and with
various modifications as are suited to the particular use
contemplated. It is intended that the scope of the invention be
defined by the claims appended hereto.
* * * * *