U.S. patent application number 12/464211 was filed with the patent office on 2009-09-24 for method for suppressing layout sensitivity of threshold voltage in a transistor array.
This patent application is currently assigned to SYNOPSYS, INC.. Invention is credited to Victor Moroz, Dipankar Pramanik.
Application Number | 20090236673 12/464211 |
Document ID | / |
Family ID | 40087168 |
Filed Date | 2009-09-24 |
United States Patent
Application |
20090236673 |
Kind Code |
A1 |
Moroz; Victor ; et
al. |
September 24, 2009 |
METHOD FOR SUPPRESSING LAYOUT SENSITIVITY OF THRESHOLD VOLTAGE IN A
TRANSISTOR ARRAY
Abstract
A method for smoothing variations in threshold voltage in an
integrated circuit layout. The method begins by identifying
recombination surfaces associated with transistors in the layout.
Such recombination surfaces are treated to affect the recombination
of interstitial atoms adjacent such surfaces, thus minimizing
variations in threshold voltage of transistors within the
layout
Inventors: |
Moroz; Victor; (Saratoga,
CA) ; Pramanik; Dipankar; (Saratoga, CA) |
Correspondence
Address: |
SYNOPSYS, INC. C/O HAYNES BEFFEL & WOLFELD LLP
P.O. BOX 366
HALF MOON BAY
CA
94019
US
|
Assignee: |
SYNOPSYS, INC.
Mountain View
CA
|
Family ID: |
40087168 |
Appl. No.: |
12/464211 |
Filed: |
May 12, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11757294 |
Jun 1, 2007 |
|
|
|
12464211 |
|
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Current U.S.
Class: |
257/390 ;
257/402; 257/411; 257/E27.06; 257/E29.255 |
Current CPC
Class: |
H01L 27/0207 20130101;
H01L 21/823412 20130101; H01L 21/823462 20130101; H01L 21/823481
20130101; H01L 29/7833 20130101 |
Class at
Publication: |
257/390 ;
257/402; 257/E27.06; 257/E29.255; 257/411 |
International
Class: |
H01L 27/088 20060101
H01L027/088; H01L 29/78 20060101 H01L029/78 |
Claims
1-9. (canceled)
10. A MOSFET array adapted for smoothing variations in threshold
voltage among transistors, comprising: diffusion areas, formed of
silicon, in a substrate; gate material overlying portions of
diffusion areas to define transistors; and shallow trench isolation
(STI) areas, formed of insulating material, separating the
diffusion areas; wherein recombination surfaces associated with
transistors in the array are treated to affect the recombination of
interstitial atoms adjacent such surfaces; whereby variations in
threshold voltage of transistors within the array are
minimized.
11. A MOSFET array according to claim 10, wherein selected gate
electrodes are treated adjacent to an identified surface to enhance
the recombination of interstitial atoms adjacent to such
surfaces.
12. A MOSFET array according to claim 10, wherein selected Si/STI
interfaces are treated to suppress the recombination of
interstitial atoms adjacent such surfaces.
13. A MOSFET array according to claim 10, wherein selected Si/STI
interfaces are treated to suppress the recombination of
interstitial atoms adjacent such surfaces; and selected gate
electrodes are treated adjacent to an identified surface to enhance
the recombination of interstitial atoms adjacent to such
surfaces.
14. A MOSFET array according to claim 11, wherein selected gate
electrodes are treated adjacent to an identified surface by
introducing a high-k material into the gate material to enhance the
recombination of interstitial atoms adjacent to such surfaces.
15. A MOSFET array according to claim 14, wherein the high-k
material is hafnium oxide (HfO2).
16. A MOSFET array according to claim 12, wherein selected Si/STI
interfaces are treated by introducing N or F atoms adjacent the
interface to suppress the recombination of interstitial atoms
adjacent such surfaces.
17. A MOSFET array according to claim 12, wherein selected Si/STI
interfaces are treated by employing oxynitride materials in the STI
to suppress the recombination of interstitial atoms adjacent such
interfaces.
18. A MOSFET array according to claim 12, wherein selected Si/STI
interfaces are treated by forming the STI having a nitride liner
adjacent the interface to suppress the recombination of
interstitial atoms adjacent such interfaces.
19. A MOSFET transistor, adapted for smoothing variations in
threshold voltage, comprising: source and drain regions, formed in
a silicon diffusion area; a channel region, lying between the
source and drain regions and overlain by gate material; and shallow
trench isolation (STI) areas, formed of insulating material,
abutting the diffusion area and separating the diffusion area from
adjacent diffusion areas; wherein recombination surfaces associated
with transistors in the layout are treated to affect the
recombination of interstitial atoms adjacent such surfaces; whereby
the threshold voltage of the transistor is adjusted.
20. A MOSFET transistor according to claim 19, wherein the gate
material is treated adjacent to an identified surface to enhance
the recombination of interstitial atoms adjacent to such
surface.
21. A MOSFET transistor according to claim 19, wherein the Si/STI
interfaces are treated to suppress the recombination of
interstitial atoms adjacent such surfaces.
22. A MOSFET transistor according to claim 19, wherein the Si/STI
interfaces are treated to suppress the recombination of
interstitial atoms adjacent such surfaces; and the gate material is
treated adjacent to the channel surface to enhance the
recombination of interstitial atoms adjacent to such surface.
23. A MOSFET transistor according to claim 20, wherein the gate
material is treated adjacent to the channel surface by introducing
a high-k material to enhance the recombination of interstitial
atoms adjacent to such surface.
24. A MOSFET transistor according to claim 23, wherein the high-k
material is hafnium oxide (HfO2).
25. A MOSFET transistor according to claim 19, wherein the Si/STI
material includes N or F atoms adjacent the interface to suppress
the recombination of interstitial atoms adjacent such surfaces.
26. A MOSFET transistor according to claim 19, wherein the Si/STI
includes oxynitride materials in the STI to suppress the
recombination of interstitial atoms adjacent such surfaces.
27. A MOSFET transistor, according to claim 19, wherein at least
one Si/STI interface includes a nitride liner adjacent the Si/STI
interface to suppress the recombination of interstitial atoms
adjacent such interfaces.
Description
BACKGROUND
[0001] The invention relates to integrated circuit devices, and
more particularly to the suppression of layout sensitivity in a
transistor array.
[0002] It has long been known that semiconductor materials such as
silicon and germanium exhibit the piezoelectric effect (mechanical
stress-induced changes in electrical resistance). See for example
C. S. Smith, "Piezoresistance effect in germanium and silicon",
Phys. Rev., vol. 94, pp. 42-49 (1954), incorporated by reference
herein. It has also been observed that stress variations in a
transistor array can produce variations in carrier mobility, which
in turn leads to variations in threshold voltage in the transistors
of the array. That problem, and a solution for it, are set out in
U.S. patent application Ser. No. 11/291,294, entitled "Analysis of
Stress Impact on Transistor Performance", assigned to the assignee
hereof.
[0003] Further study has shown, however, that beyond stress some
variation in threshold voltage remains, suggesting some additional
factor at work. Variations encountered have been far from trivial,
with swings of over 20 mV being common. The art has not suggested
any potential causes for such problems, not has it presented
solutions. Thus, it has remained for the present inventors to
discover the cause of such variations and to devise solutions, all
of which are set out below.
SUMMARY
[0004] An aspect of the claimed invention is a method for smoothing
variations in threshold voltage in an integrated circuit. The
method begins by identifying recombination surfaces associated with
transistors in the MOSFET array. Such recombination surfaces are
treated to affect the recombination of interstitial atoms adjacent
such surfaces, thus minimizing variations in threshold voltage of
transistors within the array
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1a illustrates an embodiment of a single transistor
constructed according to the claimed invention.
[0006] FIG. 1b illustrates an embodiment of a transistor array
constructed according to the claimed invention.
[0007] FIG. 2 is a plot of threshold voltage and drain current as
functions of the distance from the channel to an STI interface (for
isolated transistors) or to the next transistor (for nested
transistors)
[0008] FIG. 3 depicts the recombination of interstitial ions during
annealing, to repair lattice damage.
[0009] FIG. 4 depicts the recombination process shown in FIG. 3,
with the addition of enhancing and suppression regions according to
the claimed invention.
[0010] FIG. 5 shows the results achieved by the claimed invention,
reflected in the ion concentration patterns at each transistor, in
which the interstitial recombination rate is high at the
channel/gate oxide interface and low at the silicon/STI
interface.
[0011] FIG. 6 is a process flowchart of the method according to the
claimed invention.
DETAILED DESCRIPTION
[0012] The following detailed description is made with reference to
the figures. Preferred embodiments are described to illustrate the
present invention, not to limit its scope, which is defined by the
claims. Those of ordinary skill in the art will recognize a variety
of equivalent variations on the description that follows.
[0013] The claimed invention can best be understood by first
considering an illustrative MOS transistor 10, shown in FIG. 1a,
which shows both a plan view (upper portion) and a cross-section
taken on line A-A (bottom portion). There, a diffusion region 12
includes a source region 16 and drain region 18 formed in the
diffusion region, with a gap between these regions overlain by a
gate 14. The area under the gate is the channel 20. Spacers 22 lie
on either side of the gate (not shown in plan view). It will be
understood that materials and fabrication techniques relating to
these components, and to the MOS device as a whole, are wholly
known in the art and are thus not described in any detail here. It
is anticipated that the array would be formed in a Partially
Depleted, Silicon-on-Insulator (PDSOI MOSFET) substrate, but the
teachings of the present application apply to bulk configurations
as well. It will be noted that the drawings depict bulk MOSFET
devices. Further, it is well-known in the art that the MOSFET
channel is doped to adjust the threshold voltage that determines
when the MOSFET turns on and off. Channel dopants employed in
typical MOSFET devices include species such as boron. The
embodiment depicted in FIG. 1a has been so modified, employing ion
implantation techniques in general use. The resulting concentration
of B atoms in the crystal lattice of the diffusion region is
represented by concentration plot, which depicts an inner
high-concentration zone and an outer minimal concentration pattern.
As is generally known, concentration of dopant decreases from a
high concentration zone 23 near the channel surface, generally
outward into the channel, to a selected minimal concentration level
24. The concentration levels 23 and 24 are lines of equal dopant
concentration within the channel, grading from the regular, smooth
curve of the maximum concentration area and grading to the
irregular form of minimal concentration plot 24. Although not
shown, those in the art will understand that concentration grades
from maximum at line 23 to minimal at line 24. The transistor
arrays discussed below employ a number of individual transistors,
constructed as set out here. Details related here will be omitted
for the sake of focus and clarity in the discussion that
follows.
[0014] FIG. 1b depicts an array 100 of three transistors 110, 112
and 114. As previously described, the array is shown both in plan
and cross-section views and each individual transistor is
constructed consistent with the description above. As is commonly
seen, a transistor array is formed on a chip, on which are formed a
number a relatively large diffusion regions 102. These regions have
appropriate dopants added, by conventional processes such as ion
implantation, to produce extensive source and drain regions 104 and
106, respectively. Finally, gate material 108 is overlaid in
strips. Transistors are isolated to prevent any cross-coupling, by
areas of oxide insulator material, such as the Shallow Trench
Isolation (STI) areas 122. As the name implies, any suitable
insulator can be used in an STI, but tetraethyl orthosilicate
(TEOS) is preferred. It should be noted that the nature of
integrated circuits will result in some individual transistors
being isolated by themselves, such as transistor 114, while others
are nested into groups of two or more, such as transistors 110 and
112.
[0015] Surprisingly, it has been found that even after eliminating
stress-induced threshold voltage variations, a large amount of
variation remained within a transistor array. As reflected in FIG.
1b, measurements in a typical array revealed V.sub.t variation from
334 mV to 356 mV, a swing of 22 mV. Initial investigation did not
immediately uncover the cause of this variation, but it was noted
that the variation primarily occurred between individual isolated
transistors, such as transistor 114, and those in nested groups,
such as transistors 110 and 112.
[0016] It was noted that one difference between a point in the
channels of transistors 110 and 112, compared to a similar point in
transistor 114 is the distance from such a point to the two
surrounding STI walls. Further investigation led to the data
charted in FIG. 2, which shows both V.sub.t and I.sub.d as
functions of distance (in nm) from the channel to surrounding STI
walls (for isolated MOSFETs such as transistor 114), and to the
next MOSFET (for nested elements such as transistors 110 and 112).
As shown, at the distances seen in current fabrication
technologies, from 100-200 nm, considerable variation exists, but
that variation reduces steadily with increasing distance, and
becomes negligible at distances of about 500 nm.
[0017] A clue to what is happening at the lattice level can be
gained by returning to FIG. 1b. The bottom portion of that drawing
includes plots of channel dopant concentration, 110a, 112a, and
114a. As noted above, dopant such as boron is implanted in channel
128 to adjust threshold voltage. That operation generally is
accomplished by ion implantation. Although the implantation for
transistors 110, 112, and 114 proceeded identically, one can
observe an interesting result in FIG. 1b. Namely, the concentration
of dopant, as shown by the shape of the profile, skews toward the
nearer STI wall. Thus, in profile 110a, the dopant concentration
tilts toward the left, on the drawing page, while that of profile
112a tilts in the opposite direction, to right. In contrast,
isolated transistor 114 displays a symmetrical concentration
pattern 114a, tilting in neither direction.
[0018] Based on these results, it was hypothesized that the issue
could relate to recombination of damaged areas in the crystal
lattice. As shown in FIG. 3, and as noted above, dopants (such as
boron, phosphorous or arsenic) are introduced into the source and
drain regions, usually by ion implantation, to create highly
conductive layers in that area. The implantation process produces a
damaged area 130 in the target crystal lattice, where the newly
implanted ions have displaced the ions (generally Si ions)
previously occupying crystal lattice ion sites but the displaced
ions are still present within the lattice, as interstitial ions. It
is further known that the displaced interstitials tend to migrate
through a diffusion process toward a surface of the crystal
structure, such as the interface between the crystal structure and
the STI 122, or interface between silicon channel and gate stack
123, where displaced ions can recombine at the channel surface onto
free Si lattice sites that characterize a surface area. This occurs
at elevated temperature during the application of the thermal
annealing process. Ion paths in FIG. 3 are shown by arrows 132. As
can be seen, the distance that individual ions must travel to reach
a surface and there recombine are different, which makes it more
likely that ions located near such a surface will be able to
recombine quickly. Before the interstitials displaced by the
implantation recombine at the silicon surfaces, they move around
and enhance diffusivity of the dopants like boron, phosphorus, or
arsenic. This phenomenon is known as Transient Enhanced Diffusion
(TED). The amount of TED that the dopants experience in the channel
determines the concentration of dopants near the channel surface,
and therefore determines the threshold voltage. Therefore,
recombination of interstitials at different silicon surfaces
affects threshold voltages of the adjacent MOSFETs.
[0019] Referring back to FIG. 1b, it will be appreciated that the
expected recombination pattern for interstitial ions in the channel
of transistor 114 would be symmetrical, as the distances to an STI
wall are the same on either side of that transistor. For
transistors 110 and 112, however, application of this discovery
would lead one to expect concentration patterns skewed toward the
STI wall, and in fact that is exactly the result found.
[0020] FIG. 4 illustrates a solution to the variation problem
presented by the transistor structure of FIG. 3. At the interface
between the crystal structure and the STI, there is added a layer
of material 140 that suppresses recombination of displaced silicon
ions. Several materials are known to possess properties that would
serve in this role. Notably, an oxide layer containing species such
as N or F would tend to suppress interstitial recombination. The
exact amounts of these elements required in a specific application
to even out the TED effects between sides of a transistor adjacent
to an STI wall and the side distant from such a structure. In one
embodiment, oxynitrides are employed, produced by adding N to
SiO.sub.2. Additionally, the TEOS in an STI could be replaced by
nitride, or a nitride liner could be applied before the STI is
deposited, producing a layer 140. In either instance, nitride would
suppress interstitial recombination.
[0021] In addition to, or instead of suppression recombination at
the STI interface, recombination could be enhanced at the gate
interface. A sufficient enhancement would have the identical effect
as suppression at the STI. One embodiment of the claimed invention
employs materials including high-K dielectric material such as
hafnium oxide (HfO.sub.2).
[0022] Finally, it is possible to select dopants that are
insensitive to interstitial-driven TED effects, such as arsenic and
antimony. Such species diffuse in Si mainly by interacting with
lattice vacancies rather than with interstitials. Thus, they are
less sensitive to TED, which in turn results in lowered sensitivity
to layout variations in threshold voltage. As in known by those in
the art, implantation creates excess interstitials, not excess
vacancies, and thus the number of vacancies is determined by the
annealing temperature.
[0023] FIG. 5 illustrates the results of balancing the
recombination of interstitial ions. The interstitial recombination
rate at the channel/gate oxide interface is high, whereas it is low
at the silicon/STI interface. As can be seen, the ion concentration
profiles 110a, 112a and 114a are all symmetrical and very similar
to each other. Confirming the hypothesis underlying the claimed
invention, it can also be seen that the measured V.sub.t across the
three transistors now varies by only a single mV, not 22 mV.
[0024] A process 170 for implementing the claimed invention is
shown in FIG. 6. As seen there, the process includes two basic
steps: First, in step 172, the MOSFET array is analyzed to select
those individual transistors that require further processing. Then,
in step 174, action is taken to balance the recombination rate.
Each of those steps need consideration in detail.
[0025] The analysis and selection step requires determination of
which transistors are likely to exhibit imbalances. It is the
discovery underlying the claimed invention that one can accurately
select such transistors as those in nested configurations--that is,
those transistors having another transistor adjacent on one side
and an STI adjacent to the other side. That configuration, it has
been found, requires action. Fortunately, that configuration is
straightforward to identify in a transistor array, making it a
simple matter to make such a selection from a system layout, using
any of a number of automated design programs. In one embodiment, it
is preferred to apply both suppression and enhancement measures
globally to the entire MOSFET array. Other embodiments employ the
measures singly--that is, employing either recombination
enhancement at the gate surface or recombination suppression at the
Si/STI interface, but not both. Yet other embodiments use analysis
tools to identify particular target devices or sets of devices
where enhancement or suppression, or both, would be most
helpful.
[0026] Step 174 requires the implementation of one of the processes
identified above to accomplish the rebalancing of recombination
rates. For example, in one embodiment the TEOS material of the STI
is replaced by nitride, or in another embodiment a nitride layer is
deposited in the STI trench before the primary oxide is deposited.
In other embodiments, the balancing step is accomplished by
enhancing recombination at the gate interface. One method for
accomplishing that would be to increase the permittivity of the
oxide layer (increase k). Such an increase can be achieved by
substituting oxynitride for the SiO.sub.2 in the gate oxide,
producing a medium-k material that offered enhanced recombination.
Another embodiment first deposits or grows SiO.sub.2, followed by a
layer of high-k material, such as HfO.sub.2. In either event, it
will be helpful to avoid employing a nitrogen-based material, which
would tend to suppress recombination.
[0027] Yet another embodiment proceeds by combining both
enhancement of recombination at the gate interface and suppression
at the STI interface.
[0028] While the present invention is disclosed by reference to the
preferred embodiments and examples detailed above, it is understood
that these examples are intended in an illustrative rather than in
a limiting sense. It is contemplated that modifications and
combinations will readily occur to those skilled in the art, which
modifications and combinations will be within the spirit of the
invention and the scope of the following claims.
* * * * *