Moroz; Victor

Patent Applications and Registrations

Patent applications and USPTO patent grants for Moroz; Victor.The latest application filed is for "isolating ion implantation of silicon channels for integrated circuit layout".

Company Profile

31.158.163

Moroz; Victor - Saratoga CA
Moroz; Victor - Mountain View CA
- Saratoga CA US
Moroz; Victor - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Isolating Ion Implantation Of Silicon Channels For Integrated Circuit Layout App 20220302284 - Amoroso; Salvatore Maria ; et al.	2022-09-22
Adaptive Row Patterns For Custom-tiled Placement Fabrics For Mixed Height Cell Libraries App 20220180037 - SHERLEKAR; Deepak Dattatraya ; et al.	2022-06-09
Fin Patterning To Reduce Fin Collapse And Transistor Leakage App 20220172953 - Moroz; Victor ; et al.	2022-06-02
Josephson junction structures Grant 11,342,492 - Kawa , et al. May 24, 2	2022-05-24
Mixed Diffusion Break For Cell Design App 20220085018 - Sherlekar; Deepak Dattatraya ; et al.	2022-03-17
Power Harvesting For Integrated Circuits App 20220069007 - MOROZ; Victor ; et al.	2022-03-03
Crystal orientation engineering to achieve consistent nanowire shapes Grant 11,264,458 - Moroz , et al. March 1, 2	2022-03-01
Adaptive parallelization for multi-scale simulation Grant 11,249,813 - Smith , et al. February 15, 2	2022-02-15
Epitaxial Growth Of Source And Drain Materials In A Complementary Field Effect Transistor (cfet) App 20220020646 - LIN; Xi-Wei ; et al.	2022-01-20
Self-limiting Manufacturing Techniques To Prevent Electrical Shorts In A Complementary Field Effect Transistor (cfet) App 20220020647 - Lin; Xi-Wei ; et al.	2022-01-20
Placement and routing of cells using cell-level layout-dependent stress effects Grant 11,188,699 - Moroz November 30, 2	2021-11-30
Power harvesting for integrated circuits Grant 11,177,317 - Moroz , et al. November 16, 2	2021-11-16
Crystal orientation engineering to achieve consistent nanowire shapes Grant 11,139,402 - Moroz , et al. October 5, 2	2021-10-05
Magnetoresistive random access memory (MRAM) bit cell with a narrow write window distribution Grant 11,133,045 - Kawa , et al. September 28, 2	2021-09-28
Electro-thermal Method To Manufacture Monocrystalline Vertically Oriented Silicon Channels For Three-dimensional (3d) Nand Memories App 20210249437 - AMOROSO; Salvatore ; et al.	2021-08-12
First principles design automation tool Grant 11,068,631 - Oh , et al. July 20, 2	2021-07-20
FinFET cell architecture with insulator structure Grant 10,990,722 - Kawa , et al. April 27, 2	2021-04-27
Substrates and transistors with 2D material channels on 3D geometries Grant 10,950,736 - Moroz , et al. March 16, 2	2021-03-16
Crystal Orientation Engineering To Achieve Consistent Nanowire Shapes App 20200373388 - Moroz; Victor ; et al.	2020-11-26
Simulation scaling with DFT and non-DFT Grant 10,831,957 - Liu , et al. November 10, 2	2020-11-10
Nano-wire resistance model Grant 10,776,552 - Moroz , et al. Sept	2020-09-15
Mapping intermediate material properties to target properties to screen materials Grant 10,776,560 - Moroz , et al. Sept	2020-09-15
FinFET with heterojunction and improved channel control Grant 10,756,212 - Moroz , et al. A	2020-08-25
Method and apparatus for floating or applying voltage to a well of an integrated circuit Grant 10,741,538 - Moroz , et al. A	2020-08-11
Estimation of effective channel length for FinFETs and nano-wires Grant 10,706,209 - Moroz , et al.	2020-07-07
On-chip heating and self-annealing in FinFETs with anti-punch-through implants Grant 10,699,914 - Wong , et al.	2020-06-30
Multi-scale simulation including first principles band structure extraction Grant 10,685,156 - Liu , et al.	2020-06-16
Computationally efficient nano-scale conductor resistance model Grant 10,685,163 - El Sayed , et al.	2020-06-16
Placement And Routing Of Cells Using Cell-level Layout-dependent Stress Effects App 20200184136 - MOROZ; Victor	2020-06-11
Enhancing memory yield and performance through utilizing nanowire self-heating Grant 10,679,719 - Kawa , et al.	2020-06-09
Logic timing and reliability repair for nanowire circuits Grant 10,665,320 - Kawa , et al.	2020-05-26
Atomic scale grid for modeling semiconductor structures and fabrication processes Grant 10,606,968 - Moroz , et al.	2020-03-31
Adaptive Parallelization For Multi-scale Simulation App 20200089543 - Smith; Stephen Lee ; et al.	2020-03-19
Mapping Intermediate Material Properties to Target Properties to Screen Materials App 20200089841 - Moroz; Victor ; et al.	2020-03-19
Reversing the effects of hot carrier injection and bias threshold instability in SRAMs Grant 10,586,588 - Kawa , et al.	2020-03-10
Placement and routing of cells using cell-level layout-dependent stress effects Grant 10,572,615 - Moroz Feb	2020-02-25
Estimation of Effective Channel Length for FinFets and Nano-Wires App 20200004922 - Moroz; Victor ; et al.	2020-01-02
Substrates And Transistors With 2d Material Channels On 3d Geometries App 20200006578 - Moroz; Victor ; et al.	2020-01-02
Characterizing target material properties based on properties of similar materials Grant 10,516,725 - Moroz , et al. Dec	2019-12-24
2D material super capacitors Grant 10,504,988 - Kawa , et al. Dec	2019-12-10
First Principles Design Automation Tool App 20190362042 - Oh; Yong-Seog ; et al.	2019-11-28
Adaptive parallelization for multi-scale simulation Grant 10,489,212 - Smith , et al. Nov	2019-11-26
Enhancing Memory Yield and Performance Through Utilizing Nanowire Self-Heating App 20190355437 - KAWA; JAMIL ; et al.	2019-11-21
Automated resistance and capacitance extraction and netlist generation of logic cells Grant 10,482,212 - Qin , et al. Nov	2019-11-19
Method and apparatus with channel stop doped devices Grant 10,483,171 - Moroz Nov	2019-11-19
Crystal Orientation Engineering To Achieve Consistent Nanowire Shapes App 20190348541 - Moroz; Victor ; et al.	2019-11-14
Logic Timing and Reliability Repair for Nanowire Circuits App 20190333600 - Kawa; Jamil ; et al.	2019-10-31
Estimation of effective channel length for FinFETs and nano-wires Grant 10,417,373 - Moroz , et al. Sept	2019-09-17
Substrates and transistors with 2D material channels on 3D geometries Grant 10,411,135 - Moroz , et al. Sept	2019-09-10
First principles design automation tool Grant 10,402,520 - Oh , et al. Sep	2019-09-03
Logic timing and reliability repair for nanowire circuits Grant 10,388,397 - Kawa , et al. A	2019-08-20
Enhancing memory yield and performance through utilizing nanowire self-heating Grant 10,381,100 - Kawa , et al. A	2019-08-13
Pre-silicon design rule evaluation Grant 10,311,200 - Moroz , et al.	2019-06-04
Memory cells including vertical nanowire transistors Grant 10,312,229 - Moroz , et al.	2019-06-04
Atomic Scale Grid for Modeling Semiconductor Structures and Fabrication Processes App 20190147123 - Moroz; Victor ; et al.	2019-05-16
Cells having transistors and interconnects including nanowires or 2D material strips Grant 10,256,223 - Kawa , et al.	2019-04-09
Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same Grant 10,256,293 - Moroz , et al.	2019-04-09
Finfet with Heterojunction and Improved Channel Control App 20190043987 - Moroz; Victor ; et al.	2019-02-07
FinFet with heterojunction and improved channel control Grant 10,121,896 - Moroz , et al. November 6, 2	2018-11-06
Placement And Routing Of Cells Using Cell-level Layout-dependent Stress Effects App 20180314783 - MOROZ; Victor	2018-11-01
Atomic scale grid for modeling semiconductor structures and fabrication processes Grant 10,102,318 - Moroz , et al. October 16, 2	2018-10-16
Computationally Efficient Nano-Scale Conductor Resistance Model App 20180253524 - El Sayed; Karim ; et al.	2018-09-06
Automated Resistance and Capacitance Extraction and Netlist Generation of Logic Cells App 20180239857 - Qin; Zudian ; et al.	2018-08-23
Parameter extraction of DFT Grant 10,049,173 - Liu , et al. August 14, 2	2018-08-14
Method and Apparatus with Channel Stop Doped Devices App 20180226301 - Moroz; Victor	2018-08-09
Memory cell including vertical transistors and horizontal nanowire bit lines Grant 10,037,397 - Moroz , et al. July 31, 2	2018-07-31
Methods for manufacturing integrated circuit devices having features with reduced edge curvature Grant 10,032,859 - Moroz , et al. July 24, 2	2018-07-24
Substrates and Transistors with 2D Material Channels on 3D Geometries App 20180182898 - Moroz; Victor ; et al.	2018-06-28
Nano-wire Resistance Model App 20180157783 - Moroz; Victor ; et al.	2018-06-07
Simulation Scaling With DFT and Non-DFT App 20180144076 - Liu; Jie ; et al.	2018-05-24
Memory Cells Including Vertical Nanowire Transistors App 20180122793 - Moroz; Victor ; et al.	2018-05-03
Atomic Scale Grid for Modeling Semiconductor Structures and Fabrication Processes App 20180113968 - Moroz; Victor ; et al.	2018-04-26
One-time programmable memory using rupturing of gate insulation Grant 9,953,990 - Horch , et al. April 24, 2	2018-04-24
Method and apparatus with channel stop doped devices Grant 9,917,018 - Moroz March 13, 2	2018-03-13
Simulation scaling with DFT and non-DFT Grant 9,881,111 - Liu , et al. January 30, 2	2018-01-30
Logic Timing and Reliability Repair for Nanowire Circuits App 20180005707 - Kawa; Jamil ; et al.	2018-01-04
Enhancing Memory Yield and Performance Through Utilizing Nanowire Self-Heating App 20180005708 - Kawa; Jamil ; et al.	2018-01-04
Integrated Circuit Devices Having Features With Reduced Edge Curvature and Methods for Manufacturing the Same App 20170373136 - Moroz; Victor ; et al.	2017-12-28
2D Material Super Capacitors App 20170373134 - Kawa; Jamil ; et al.	2017-12-28
Atomic scale grid for modeling semiconductor structures and fabrication processes Grant 9,852,242 - Moroz , et al. December 26, 2	2017-12-26
Iterative simulation with DFT and non-DFT Grant 9,836,563 - Liu , et al. December 5, 2	2017-12-05
Method and Apparatus for Floating or Applying Voltage to a Well of an Integrated Circuit App 20170330872 - Moroz; Victor ; et al.	2017-11-16
Parameter Extraction of DFT App 20170329882 - Liu; Jie ; et al.	2017-11-16
Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits Grant 9,817,928 - Kawa , et al. November 14, 2	2017-11-14
Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same Grant 9,786,734 - Moroz , et al. October 10, 2	2017-10-10
Power Harvesting For Integrated Circuits App 20170287977 - Moroz; Victor ; et al.	2017-10-05
2D material super capacitors Grant 9,735,227 - Kawa , et al. August 15, 2	2017-08-15
Method and apparatus for floating or applying voltage to a well of an integrated circuit Grant 9,728,528 - Moroz , et al. August 8, 2	2017-08-08
Parameter extraction of DFT Grant 9,727,675 - Liu , et al. August 8, 2	2017-08-08
Nanowire or 2D material strips interconnects in an integrated circuit cell Grant 9,691,768 - Moroz , et al. June 27, 2	2017-06-27
FinFET cell architecture with power traces Grant 9,691,764 - Kawa , et al. June 27, 2	2017-06-27
N-channel and P-channel end-to-end finFET cell architecture Grant 9,646,966 - Moroz May 9, 2	2017-05-09
2d Material Super Capacitors App 20170040411 - Kawa; Jamil ; et al.	2017-02-09
Pre-Silicon Design Rule Evaluation App 20170039308 - Moroz; Victor ; et al.	2017-02-09
Methods for Manufacturing Integrated Circuit Devices Having Features With Reduced Edge Curvature App 20170025496 - Moroz; Victor ; et al.	2017-01-26
Methods for fabricating high-density integrated circuit devices Grant 9,547,740 - Moroz , et al. January 17, 2	2017-01-17
Integrated Circuit On Corrugated Substrate App 20160359006 - King Liu; Tsu-Jae ; et al.	2016-12-08
Design Tools For Converting a FinFet Circuit into a Circuit Including Nanowires and 2D Material Strips App 20160335387 - Moroz; Victor ; et al.	2016-11-17
Multi-scale Simulation Including First Principles Band Structure Extraction App 20160335381 - LIU; JIE ; et al.	2016-11-17
Cells Having Transistors And Interconnects Including Nanowires Or 2d Material Strips App 20160329313 - KAWA; JAMIL ; et al.	2016-11-10
Method for suppressing lattice defects in a semiconductor substrate Grant 9,472,423 - Moroz , et al. October 18, 2	2016-10-18
Analysis of stress impact on transistor performance Grant 9,465,897 - Moroz , et al. October 11, 2	2016-10-11
Nanowire Or 2d Material Strips Interconnects In An Integrated Circuit Cell App 20160284704 - Moroz; Victor ; et al.	2016-09-29
Estimation Of Effective Channel Length for Finfets and Nano-wires App 20160246915 - MOROZ; Victor ; et al.	2016-08-25
SRAM layouts Grant 9,418,189 - Lin , et al. August 16, 2	2016-08-16
First Principles Design Automation Tool App 20160232264 - OH; YONG-SEOG ; et al.	2016-08-11
Parameter Extraction Of Dft App 20160217234 - LIU; JIE ; et al.	2016-07-28
Cells having transistors and interconnects including nanowires or 2D material strips Grant 9,400,862 - Kawa , et al. July 26, 2	2016-07-26
Increasing Ion/Ioff ratio in FinFETs and nano-wires Grant 9,379,018 - Choi , et al. June 28, 2	2016-06-28
Methods for manufacturing integrated circuit devices having features with reduced edge curvature Grant 9,379,183 - Moroz , et al. June 28, 2	2016-06-28
Array with intercell conductors including nanowires or 2D material strips Grant 9,378,320 - Kawa , et al. June 28, 2	2016-06-28
Mapping Intermediate Material Properties To Target Properties To Screen Materials App 20160162625 - Moroz; Victor ; et al.	2016-06-09
Nanowire or 2D material strips interconnects in an integrated circuit cell Grant 9,361,418 - Moroz , et al. June 7, 2	2016-06-07
Finfet With Heterojunction And Improved Channel Control App 20160087099 - Moroz; Victor ; et al.	2016-03-24
Method and apparatus for floating or applying voltage to a well of an integrated circuit Grant 9,287,253 - Moroz , et al. March 15, 2	2016-03-15
Atomic Scale Grid For Modeling Semiconductor Structures And Fabrication Processes App 20160070830 - Moroz; Victor ; et al.	2016-03-10
Arrays With Compact Series Connection For Vertical Nanowires Realizations App 20160063163 - Moroz; Victor ; et al.	2016-03-03
Placing transistors in proximity to through-silicon vias Grant 9,275,182 - Sproch , et al. March 1, 2	2016-03-01
Finfet Cell Architecture With Power Traces App 20160043083 - KAWA; JAMIL ; et al.	2016-02-11
Methods For Manufacturing Integrated Circuit Devices Having Features With Reduced Edge Curvature App 20160043174 - Moroz; Victor ; et al.	2016-02-11
N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch Grant 9,257,429 - Moroz , et al. February 9, 2	2016-02-09
Latch-up Suppression And Substrate Noise Coupling Reduction Through A Substrate Back-tie For 3d Integrated Circuits App 20160034620 - KAWA; JAMIL ; et al.	2016-02-04
Cells Having Transistors And Interconnects Including Nanowires Or 2d Material Strips App 20150370951 - KAWA; JAMIL ; et al.	2015-12-24
Nanowire Or 2d Material Strips Interconnects In An Integrated Circuit Cell App 20150370949 - MOROZ; VICTOR ; et al.	2015-12-24
Memory Cells Having Transistors With Different Numbers Of Nanowires Or 2d Material Strips App 20150370948 - KAWA; JAMIL ; et al.	2015-12-24
Array With Intercell Conductors Including Nanowires Or 2d Material Strips App 20150370950 - KAWA; JAMIL ; et al.	2015-12-24
Design Tools For Integrated Circuit Components Including Nanowires And 2d Material Strips App 20150370947 - MOROZ; VICTOR ; et al.	2015-12-24
Self-aligned via interconnect using relaxed patterning exposure Grant 9,209,129 - Rieger , et al. December 8, 2	2015-12-08
Analysis of stress impact on transistor performance Grant 9,189,580 - Moroz , et al. November 17, 2	2015-11-17
Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits Grant 9,190,346 - Moroz , et al. November 17, 2	2015-11-17
Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits Grant 9,184,110 - Kawa , et al. November 10, 2	2015-11-10
Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits Grant 9,177,894 - Kawa , et al. November 3, 2	2015-11-03
Finfet Cell Architecture With Power Traces App 20150303196 - KAWA; JAMIL ; et al.	2015-10-22
Integrated Circuit Devices Having Features With Reduced Edge Curvature And Methods For Manufacturing The Same App 20150295021 - Moroz; Victor ; et al.	2015-10-15
Methods for manufacturing integrated circuit devices having features with reduced edge curvature Grant 9,152,750 - Moroz , et al. October 6, 2	2015-10-06
Analysis of stress impact on transistor performance Grant 9,141,737 - Moroz , et al. September 22, 2	2015-09-22
Finfet Cell Architecture With Insulator Structure App 20150261894 - KAWA; Jamil ; et al.	2015-09-17
Placing Transistors In Proximity To Through-silicon Vias App 20150205904 - Sproch; James David ; et al.	2015-07-23
N-channel And P-channel End-to-end Finfet Cell Architecture With Relaxed Gate Pitch App 20150194429 - Moroz; Victor ; et al.	2015-07-09
FinFET cell architecture with power traces Grant 9,076,673 - Kawa , et al. July 7, 2	2015-07-07
Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same Grant 9,064,808 - Moroz , et al. June 23, 2	2015-06-23
Method And Apparatus For Floating Or Applying Voltage To A Well Of An Integrated Circuit App 20150162320 - Moroz; Victor ; et al.	2015-06-11
FinFET cell architecture with insulator structure Grant 9,048,121 - Kawa , et al. June 2, 2	2015-06-02
Methods For Fabricating High-density Integrated Circuit Devices App 20150143306 - Moroz; Victor ; et al.	2015-05-21
Finfet Cell Architecture With Power Traces App 20150137256 - KAWA; JAMIL ; et al.	2015-05-21
Sram Layouts App 20150113492 - Lin; Xi-Wei ; et al.	2015-04-23
Placing transistors in proximity to through-silicon vias Grant 9,003,348 - Sproch , et al. April 7, 2	2015-04-07
Characterizing Target Material Properties Based On Properties Of Similar Materials App 20150088803 - Moroz; Victor ; et al.	2015-03-26
Adaptive Parallelization For Multi-scale Simulation App 20150089511 - Smith; Stephen Lee ; et al.	2015-03-26
Iterative Simulation With Dft And Non-dft App 20150088481 - LIU; JIE ; et al.	2015-03-26
Simulation Scaling With Dft And Non-dft App 20150088473 - LIU; JIE ; et al.	2015-03-26
N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch Grant 8,987,828 - Moroz , et al. March 24, 2	2015-03-24
SRAM layouts Grant 8,964,453 - Lin , et al. February 24, 2	2015-02-24
Increasing Ion/ioff Ratio In Finfets And Nano-wires App 20150041921 - Choi; Munkang ; et al.	2015-02-12
N-channel And P-channel End-to-end Finfet Cell Architecture App 20150041924 - MOROZ; VICTOR	2015-02-12
FinFET cell architecture with power traces Grant 08924908 -	2014-12-30
FinFET cell architecture with power traces Grant 8,924,908 - Kawa , et al. December 30, 2	2014-12-30
Self-Aligned Via Interconnect Using Relaxed Patterning Exposure App 20140367855 - Rieger; Michael L. ; et al.	2014-12-18
N-channel and P-channel end-to-end finfet cell architecture Grant 8,901,615 - Moroz December 2, 2	2014-12-02
Analysis of stress impact on transistor performance Grant 8,881,073 - Moroz , et al. November 4, 2	2014-11-04
Boosting transistor performance with non-rectangular channels Grant 8,869,078 - Moroz , et al. October 21, 2	2014-10-21
Increasing ION /IOFF ratio in FinFETs and nano-wires Grant 8,847,324 - Choi , et al. September 30, 2	2014-09-30
Integrated Circuit On Corrugated Substrate App 20140284727 - King Liu; Tsu-Jae ; et al.	2014-09-25
Self-aligned via interconnect using relaxed patterning exposure Grant 8,813,012 - Rieger , et al. August 19, 2	2014-08-19
Methods For Manufacturing Integrated Circuit Devices Having Features With Reduced Edge Curvature App 20140223394 - Moroz; Victor ; et al.	2014-08-07
Boosting Transistor Performance With Non-rectangular Channels App 20140223395 - Moroz; Victor ; et al.	2014-08-07
N-channel And P-channel End-to-end Finfet Cell Architecture With Relaxed Gate Pitch App 20140217514 - Moroz; Victor ; et al.	2014-08-07
Integrated circuit on corrugated substrate Grant 8,786,057 - King , et al. July 22, 2	2014-07-22
Analysis of stress impact on transistor performance Grant 8,762,924 - Moroz , et al. June 24, 2	2014-06-24
Placing Transistors In Proximity To Through-silicon Vias App 20140173545 - Sproch; James David ; et al.	2014-06-19
Increasing Ion/ioff Ratio In Finfets And Nano-wires App 20140167174 - Choi; Munkang ; et al.	2014-06-19
Method And Apparatus With Channel Stop Doped Devices App 20140154855 - Moroz; Victor	2014-06-05
N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch Grant 8,723,268 - Moroz , et al. May 13, 2	2014-05-13
Analysis of stress impact on transistor performance Grant 8,713,510 - Moroz , et al. April 29, 2	2014-04-29
Analysis Of Stress Impact On Transistor Performance App 20140115556 - Moroz; Victor ; et al.	2014-04-24
Boosting transistor performance with non-rectangular channels Grant 8,701,054 - Moroz , et al. April 15, 2	2014-04-15
Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance Grant 8,686,512 - Moroz , et al. April 1, 2	2014-04-01
Latch-up Suppression And Substrate Noise Coupling Reduction Through A Substrate Back-tie For 3d Integrated Circuits App 20140061936 - Moroz; Victor ; et al.	2014-03-06
Latch-up Suppression And Substrate Noise Coupling Reduction Through A Substrate Back-tie For 3d Integrated Circuits App 20140061943 - Kawa; Jamil ; et al.	2014-03-06
Latch-up Suppression And Substrate Noise Coupling Reduction Through A Substrate Back-tie For 3d Integrated Circuits App 20140065821 - Kawa; Jamil ; et al.	2014-03-06
Finfet Cell Architecture With Power Traces App 20140054722 - KAWA; JAMIL ; et al.	2014-02-27
Analysis of stress impact on transistor performance Grant 8,661,398 - Moroz , et al. February 25, 2	2014-02-25
Placing transistors in proximity to through-silicon vias Grant 8,661,387 - Sproch , et al. February 25, 2	2014-02-25
Finfet Cell Architecture With Insulator Structure App 20140035053 - KAWA; JAMIL ; et al.	2014-02-06
Self-aligned Via Interconnect Using Relaxed Patterning Exposure App 20140015135 - Rieger; Michael L. ; et al.	2014-01-16
Sram Layouts App 20140003133 - Lin; Xi-Wei ; et al.	2014-01-02
Analysis of stress impact on transistor performance Grant 8,615,728 - Moroz , et al. December 24, 2	2013-12-24
N-channel And P-channel End-to-end Finfet Cell Architecture With Relaxed Gate Pitch App 20130334610 - Moroz; Victor ; et al.	2013-12-19
N-channel And P-channel End-to-end Finfet Cell Architecture App 20130334613 - MOROZ; VICTOR	2013-12-19
Methods for manufacturing integrated circuit devices having features with reduced edge curvature Grant 8,609,550 - Moroz , et al. December 17, 2	2013-12-17
N-channel and p-channel finFET cell architecture Grant 8,595,661 - Kawa , et al. November 26, 2	2013-11-26
Analysis of stress impact on transistor performance Grant 8,560,995 - Moroz , et al. October 15, 2	2013-10-15
N-channel and P-channel finFET cell architecture with inter-block insulator Grant 8,561,003 - Kawa , et al. October 15, 2	2013-10-15
Method and Apparatus for Placing Transistors In Proximity to Through-Silicon Vias App 20130132914 - Sproch; James David ; et al.	2013-05-23
Method For Rapid Estimation Of Layout-dependent Threshold Voltage Variation In A Mosfet Array App 20130125075 - MOROZ; VICTOR ; et al.	2013-05-16
Method and apparatus for floating or applying voltage to a well of an integrated circuit App 20130113547 - Moroz; Victor ; et al.	2013-05-09
Analysis of stress impact on transistor performance Grant 8,413,096 - Moroz , et al. April 2, 2	2013-04-02
Analysis of stress impact on transistor performance Grant 8,407,634 - Moroz , et al. March 26, 2	2013-03-26
Methods For Manufacturing Integrated Circuit Devices Having Features With Reduced Edge Curvature App 20130065380 - Moroz; Victor ; et al.	2013-03-14
Integrated Circuit Devices Having Features With Reduced Edge Curvature And Methods For Manufacturing The Same App 20130026607 - Moroz; Victor ; et al.	2013-01-31
Threshold Adjustment Of Transistors By Controlled S/d Underlap App 20130026575 - Moroz; Victor ; et al.	2013-01-31
N-channel And P-channel Finfet Cell Architecture App 20130026572 - KAWA; JAMIL ; et al.	2013-01-31
N-channel And P-channel Finfet Cell Architecture With Inter-block Insulator App 20130026571 - KAWA; JAMIL ; et al.	2013-01-31
Method and apparatus for placing transistors in proximity to through-silicon vias Grant 8,362,622 - Sproch , et al. January 29, 2	2013-01-29
Reclaiming usable integrated circuit chip area near through-silicon vias Grant 8,354,736 - Moroz January 15, 2	2013-01-15
Stress-enhanced performance of a FinFET using surface/channel orientations and strained capping layers Grant 8,349,668 - Moroz , et al. January 8, 2	2013-01-08
Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array Grant 8,347,252 - Moroz , et al. January 1, 2	2013-01-01
Methods For Fabricating High-density Integrated Circuit Devices App 20120280354 - MOROZ; VICTOR ; et al.	2012-11-08
Method for compensation of process-induced performance variation in a MOSFET integrated circuit Grant 8,219,961 - Moroz , et al. July 10, 2	2012-07-10
Boosting Transistor Performance With Non-rectangular Channels App 20120011479 - Moroz; Victor ; et al.	2012-01-12
Method of correlating silicon stress to device instance parameters for circuit simulation Grant 8,086,990 - Lin , et al. December 27, 2	2011-12-27
Elevation Of Transistor Channels To Reduce Impact Of Shallow Trench Isolation On Transistor Performance App 20110309453 - Moroz; Victor ; et al.	2011-12-22
Stress-managed revision of integrated circuit layouts Grant 8,069,430 - Moroz , et al. November 29, 2	2011-11-29
Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance Grant 8,035,168 - Moroz , et al. October 11, 2	2011-10-11
Method for Compensation of Process-Induced Performance Variation in a Mosfet Integrated Circuit App 20110219351 - Moroz; Victor ; et al.	2011-09-08
Stress-Enhanced Performance Of A Finfet Using Surface/Channel Orientations And Strained Capping Layers App 20110212601 - Moroz; Victor ; et al.	2011-09-01
Method and apparatus for performing stress modeling of integrated circuit material undergoing material conversion Grant 7,996,795 - Moroz , et al. August 9, 2	2011-08-09
Reclaiming Usable Integrated Circuit Chip Area Near Through-silicon Vias App 20110169140 - MOROZ; VICTOR	2011-07-14
Methods for forming a transistor Grant 7,968,413 - Nouri , et al. June 28, 2	2011-06-28
Methods of designing an integrated circuit on corrugated substrate Grant 7,960,232 - King , et al. June 14, 2	2011-06-14
Method for compensation of process-induced performance variation in a MOSFET integrated circuit Grant 7,949,985 - Moroz , et al. May 24, 2	2011-05-24
Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers Grant 7,939,862 - Moroz , et al. May 10, 2	2011-05-10
Method and apparatus for generating a layout for a transistor Grant 7,926,018 - Moroz , et al. April 12, 2	2011-04-12
Managing integrated circuit stress using dummy diffusion regions Grant 7,897,479 - Lin , et al. March 1, 2	2011-03-01
Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance Grant 7,863,146 - Moroz , et al. January 4, 2	2011-01-04
Methods for forming a transistor Grant 7,833,869 - Nouri , et al. November 16, 2	2010-11-16
Method and Apparatus for Performing Stress Modeling of Integrated Circuit Material Undergoing Material Conversion App 20100274376 - Moroz; Victor ; et al.	2010-10-28
Method And Apparatus For Placing Transistors In Proximity To Through-silicon Vias App 20100270597 - SPROCH; JAMES DAVID ; et al.	2010-10-28
Managing integrated circuit stress using stress adjustment trenches Grant 7,767,515 - Moroz , et al. August 3, 2	2010-08-03
Boosting Transistor Performance With Non-rectangular Channels App 20100187609 - Moroz; Victor ; et al.	2010-07-29
Transistor array with selected subset having suppressed layout sensitivity of threshold voltage Grant 7,705,406 - Moroz , et al. April 27, 2	2010-04-27
Method for suppressing layout sensitivity of threshold voltage in a transistor array Grant 7,691,693 - Moroz , et al. April 6, 2	2010-04-06
Method and apparatus for placing an integrated circuit device within an integrated circuit layout Grant 7,681,164 - Lin , et al. March 16, 2	2010-03-16
Analysis Of Stress Impact On Transistor Performance App 20100042958 - Moroz; Victor ; et al.	2010-02-18
Stress Engineering For Cap Layer Induced Stress App 20100029050 - MOROZ; VICTOR ; et al.	2010-02-04
Method For Suppressing Lattice Defects In A Semiconductor Substrate App 20100025777 - Moroz; Victor ; et al.	2010-02-04
Stress Engineering For Cap Layer Induced Stress App 20100024978 - MOROZ; VICTOR ; et al.	2010-02-04
Analysis Of Stress Impact On Transistor Performance App 20100023902 - Moroz; Victor ; et al.	2010-01-28
Analysis Of Stress Impact On Transistor Performance App 20100023900 - Moroz; Victor ; et al.	2010-01-28
Managing Integrated Circuit Stress Using Stress Adjustment Trenches App 20100019317 - Moroz; Victor ; et al.	2010-01-28
Analysis Of Stress Impact On Transistor Performance App 20100023901 - Moroz; Victor ; et al.	2010-01-28
Analysis Of Stress Impact On Transistor Performance App 20100023899 - Moroz; Victor ; et al.	2010-01-28
Stress-managed Revision Of Integrated Circuit Layouts App 20090313595 - Moroz; Victor ; et al.	2009-12-17
Method for Rapid Estimation of Layout-Dependent Threshold Voltage Variation in a MOSFET Array App 20090288049 - MOROZ; VICTOR ; et al.	2009-11-19
Analysis Of Stress Impact On Transistor Performance App 20090288048 - Moroz; Victor ; et al.	2009-11-19
Stress-managed revision of integrated circuit layouts Grant 7,600,207 - Moroz , et al. October 6, 2	2009-10-06
Method For Suppressing Layout Sensitivity Of Threshold Voltage In A Transistor Array App 20090236673 - Moroz; Victor ; et al.	2009-09-24
Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array Grant 7,584,438 - Moroz , et al. September 1, 2	2009-09-01
Method Of Correlating Silicon Stress To Device Instance Parameters For Circuit Simulation App 20090217217 - Lin; Xi-Wei ; et al.	2009-08-27
Integrated Circuit On Corrugated Substrate App 20090181477 - King; Tsu-Jae ; et al.	2009-07-16
Method of correlating silicon stress to device instance parameters for circuit simulation Grant 7,542,891 - Lin , et al. June 2, 2	2009-06-02
Integrated circuit on corrugated substrate Grant 7,528,465 - King , et al. May 5, 2	2009-05-05
Method for Suppressing Lattice Defects in a Semiconductor Substrate App 20090108293 - Moroz; Victor ; et al.	2009-04-30
Method for Trapping Implant Damage in a Semiconductor Substrate App 20090108408 - Moroz; Victor ; et al.	2009-04-30
Method And Apparatus For Generating A Layout For A Transistor App 20090083688 - Moroz; Victor ; et al.	2009-03-26
Method And Apparatus For Placing An Integrated Circuit Device Within An Integrated Circuit Layout App 20090064072 - Lin; Xi-Wei ; et al.	2009-03-05
Managing integrated circuit stress using dummy diffusion regions Grant 7,484,198 - Lin , et al. January 27, 2	2009-01-27
Managing Integrated Circuit Stress Using Dummy Diffusion Regions App 20090007043 - Lin; Xi-Wei ; et al.	2009-01-01
Method For Compensation Of Process-induced Performance Variation In A Mosfet Integrated Circuit App 20080297237 - Moroz; Victor ; et al.	2008-12-04
Method For Suppressing Layout Sensitivity Of Threshold Voltage In A Transistor Array App 20080296698 - Moroz; Victor ; et al.	2008-12-04
Stress-Enhanced Performance Of A FinFet Using Surface/Channel Orientations And Strained Capping Layers App 20080296632 - Moroz; Victor ; et al.	2008-12-04
Methods For Forming A Transistor App 20080299735 - NOURI; FARAN ; et al.	2008-12-04
Method For Rapid Estimation Of Layout-dependent Threshold Voltage Variation In A Mosfet Array App 20080301599 - Moroz; Victor ; et al.	2008-12-04
Integrated Circuit On Corrugated Substrate App 20080290470 - King; Tsu-Jae ; et al.	2008-11-27
Methods For Forming A Transistor App 20080280413 - Nouri; Faran ; et al.	2008-11-13
Methods for forming a transistor Grant 7,413,957 - Nouri , et al. August 19, 2	2008-08-19
Method of Correlating Silicon Stress to Device Instance Parameters for Circuit Simulation App 20080127005 - Lin; Xi-Wei ; et al.	2008-05-29
Elevation Of Transistor Channels To Reduce Impact Of Shallow Trench Isolation On Transistor Performance App 20070298566 - MOROZ; VICTOR ; et al.	2007-12-27
Simulation of processes, devices and circuits by a modified newton method Grant 7,302,375 - Kucherov , et al. November 27, 2	2007-11-27
Stress Engineering For Cap Layer Induced Stress App 20070246776 - Moroz; Victor ; et al.	2007-10-25
Method of IC production using corrugated substrate Grant 7,265,008 - King , et al. September 4, 2	2007-09-04
Managing integrated circuit stress using stress adjustment trenches App 20070202663 - Moroz; Victor ; et al.	2007-08-30
Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance App 20070202652 - Moroz; Victor ; et al.	2007-08-30
Managing integrated circuit stress using dummy diffusion regions App 20070202662 - Lin; Xi-Wei ; et al.	2007-08-30
Stress-managed revision of integrated circuit layouts App 20070204250 - Moroz; Victor ; et al.	2007-08-30
Segmented channel MOS transistor Grant 7,247,887 - King , et al. July 24, 2	2007-07-24
Integrated Circuit On Corrugated Substrate App 20070132053 - King; Tsu-Jae ; et al.	2007-06-14
Integrated circuit on corrugated substrate Grant 7,190,050 - King , et al. March 13, 2	2007-03-13
Integrated circuit on corrugated substrate App 20070001232 - King; Tsu-Jae ; et al.	2007-01-04
Method of IC production using corrugated substrate App 20070004113 - King; Tsu-Jae ; et al.	2007-01-04
Segmented channel MOS transistor App 20070001237 - King; Tsu-Jae ; et al.	2007-01-04
Simulation of processes, devices and circuits by a modified newton method App 20060047737 - Kucherov; Andrey ; et al.	2006-03-02
Methods for forming a transistor App 20050287752 - Nouri, Faran ; et al.	2005-12-29