U.S. patent application number 12/400012 was filed with the patent office on 2009-07-16 for substrate treating system for depositing a metal gate on a high-k dielectric film and improving high-k dielectric film and metal gate interface.
This patent application is currently assigned to CANON ANELVA CORPORATION. Invention is credited to Naomu Kitano, Motomu Kosuda, Wickramanayaka Sunil, Naoki Yamada.
Application Number | 20090178621 12/400012 |
Document ID | / |
Family ID | 36932444 |
Filed Date | 2009-07-16 |
United States Patent
Application |
20090178621 |
Kind Code |
A1 |
Sunil; Wickramanayaka ; et
al. |
July 16, 2009 |
SUBSTRATE TREATING SYSTEM FOR DEPOSITING A METAL GATE ON A HIGH-K
DIELECTRIC FILM AND IMPROVING HIGH-K DIELECTRIC FILM AND METAL GATE
INTERFACE
Abstract
An apparatus to improve high-k dielectric film and metal gate
interface in the fabrication of MOSFET by depositing a metal gate
on a high-k dielectric comprising an annealing step annealing a
substrate with high-k dielectric film deposited thereon in a
thermal annealing module and a depositing step depositing a metal
gate material on said annealed substrate in a metal gate deposition
module, characterized that said annealing step and depositing step
are carried out consecutively without a vacuum break.
Inventors: |
Sunil; Wickramanayaka;
(Tokyo, JP) ; Kosuda; Motomu; (Tokyo, JP) ;
Yamada; Naoki; (Tokyo, JP) ; Kitano; Naomu;
(Tokyo, JP) |
Correspondence
Address: |
BUCHANAN, INGERSOLL & ROONEY PC
POST OFFICE BOX 1404
ALEXANDRIA
VA
22313-1404
US
|
Assignee: |
CANON ANELVA CORPORATION
Kawasaki-shi
JP
|
Family ID: |
36932444 |
Appl. No.: |
12/400012 |
Filed: |
March 9, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11347256 |
Feb 6, 2006 |
|
|
|
12400012 |
|
|
|
|
Current U.S.
Class: |
118/729 ;
204/298.15 |
Current CPC
Class: |
H01L 21/28185 20130101;
C23C 14/5806 20130101; H01L 21/31645 20130101; H01L 29/517
20130101; H01L 21/67207 20130101 |
Class at
Publication: |
118/729 ;
204/298.15 |
International
Class: |
C23C 16/54 20060101
C23C016/54 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 25, 2005 |
JP |
2005-51340 |
Claims
1. A substrate treating system comprising a wafer-handling platform
including a transfer device to transfer a substrate and a
processing module connected to said wafer-handling platform;
wherein said processing module includes at least a thermal
annealing module and a metal gate deposition module; and said
transfer device is adapted to transfer the substrate between said
wafer-handling platform and said processing module without a vacuum
break.
2. The substrate treating system according to claim 1, wherein said
processing module further includes a cooling module or a high-k
higher dielectric material deposition module.
3. The substrate treating system according to claim 1, wherein said
processing module further includes a cooling module and a high-k
higher dielectric material deposition module.
4. A substrate treating apparatus comprising: an angled-PVD module
configured and positioned to deposit a starting material on a
substrate; a thermal annealing module configured and positioned to
anneal a substrate on which the starting material is deposited; and
a transfer device configured and positioned to deliver the
substrate to the angled-PVD module and the thermal annealing
module.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority of Japanese Patent
Application No. 2005-051340, filed in Japan on Feb. 25, 2005, and
is a divisional application of U.S. patent application Ser. No.
11/347,256, filed Feb. 6, 2006, the entire contents of which are
hereby incorporated by reference.
FIELD OF THE INVENTION
[0002] The present invention relates to a method for depositing a
metal gate on a high-k dielectric film in the fabrication of
metal-oxide-semiconductor field effect transistors (MOSFET). And,
the present invention relates to a method for improving high-k
dielectric film and metal gate interface in the fabrication of
MOSFET. Also, the present invention relates to a substrate treating
system, which is suitable to be used in said methods.
BACKGROUND OF THE INVENTION
[0003] The elementary device of most of the complex integrated
circuits (IC) fabricated on semiconductor substrates is a
metal-oxide-semiconductor (MOS) transistor. These transistors are
generally called metal-oxide-semiconductor field effect transistors
(hereinafter referred to MOSFET).
[0004] FIG. 15 shows an example of a simple diagram of a MOSFET
denoted by numeral 100. In FIG. 15, MOSFET 100 is comprised of a
semiconductor 101, gate dielectric (gate oxide) 104, gate electrode
105, source region 102 and drain region 103. During its operation
an electric field is applied to the channel region 107 below the
gate dielectric 104 to switch the transistor on and off.
[0005] In order to increase the performance of integrated circuits
(IC), the design rule or the smallest feature size of ICs are
gradually reduced. With the shrink of design rule, new materials
and deposition techniques are of importance. For example, the
thickness of gate oxide (t.sub.ox) reduces with the reduction of
gate length (G.sub.L) (denoted by numeral 106) with the
relationship of t.sub.ox=0.018 G.sub.L. This is important to
maintain a higher capacitance between semiconductor 101 and the
gate electrode 105.
[0006] With respect to the thinning of gate oxide 104, conventional
dielectric materials (SiO.sub.2, SiON) are no longer applicable
since very thin films of these materials show different electrical
properties such as higher leakage current.
[0007] The gate dielectric (gate oxide) should be replaced with new
dielectric materials of which the dielectric constant is higher
than that of SiO.sub.2. This facilitates to use thicker film
without compensating the capacitance.
[0008] These higher dielectric constant materials are called high-k
dielectrics. For example, HfO.sub.2, HfSiO, HfAlO are considered as
high-k dielectrics.
[0009] With the use of high-k dielectrics, conventional gate
electrode material, such as poly-Si, also must be replaced with
different materials due to two reasons. First is that poly-Si is
not compatible with most high-k dielectrics. Second is that use of
poly-Si causes a generation of depletion region at the
poly-Si/high-k interface resulting in a higher equivalent oxide
thickness (EOT) and a lower capacitance.
[0010] Pure metals, metal alloys, metal nitride or metal alloy
nitrides are usually considered for a gate electrode to be used
with high-k dielectrics.
[0011] At present, high-k and metal gate are fabricated with the
procedure given in the following chart, for example.
[0012] 1. clean Si substrates with diluted HF solution
[0013] 2. dry the wafer in Nitrogen
[0014] 3. deposit thermal SiO.sub.2 (.about.1 nm)
[0015] 4. deposit Hf (or HfO.sub.2)
[0016] 5. thermal annealing
[0017] 6. deposit metal gate
[0018] 7. thermal annealing
[0019] One may eliminate step 3 described in the above procedure,
and instead, Hf or HfO.sub.2 is directly deposited on
surface-treated Si. Moreover, the above procedure is explained
using HfO.sub.2 as the high-k dielectric. However, one can select
any other high-k material as the dielectric, for example, HfSiO,
HfSiON, HfAlO etc.
[0020] FIG. 14 is a schematic diagram showing a CVD module 40
attached to a central wafer-handling platform 3 and wafer
loading/unloading equipment-front-end module 13. CVD module 40 may
be Metal Organic Chemical Vapor Deposition (MOCVD) module or Atomic
Layer Deposition (ALD) module.
[0021] In MOCVD processes, metal-organic gases are used. There are
two basic groups of metal-organic gases; for example, in depositing
Hf-base dielectrics one can use i) halide-based gases such as
HfCI.sub.4 or ii) carbon-based gases such as
C.sub.16H.sub.40N.sub.4Hf (Tetrakis-diethylamino hafnium).
[0022] In ALD depositions, two gases are alternatively introduced
into the CVD module 40. When the first gas, which is usually called
the precursor gas, is introduced into the CVD module 40, precursor
molecules stick on the substrate surface. When the second gas is
introduced into the CVD module 40, it reacts with surface-stick
precursor molecules and forms a dielectric film. This procedure
continues until a film with the desired thickness is formed.
[0023] Impurity contamination is the biggest problem in any CVD
(ALD or MOCVD) processes.
[0024] For example, firstly, in MOCVD, halides or carbon
contaminates the wafer. In ALD process also, carbon from precursor
gas contaminates the film. Higher impurity concentration in the
dielectric film causes higher leakage current, threshold voltage
shift and reduction of electron mobility in the channel region 107
in MOSFET devices (FIG. 15).
[0025] Secondly, for any CVD (MOCVD or ALD) processes, wafer must
be heated to a higher temperature, for example 400.degree. C. The
temperature uniformity on the substrate surface directly affects
the film uniformity. Any temperature non-uniformity results in
non-uniform dielectric film and thereby causes faulty MOSFET
devices or a lower yield (number of good MOSFETs) per wafer.
[0026] Thirdly, lower throughput, particularly with the ALD method,
limits the economic viability. In the ALD process, film grows with
the switching of two gases so the deposition rate is slow. The
required film thickness of high-k dielectric materials is usually
10-40 angstroms. When these deposition rate and film thickness are
considered, the throughput is less than 10 wafers per hour.
[0027] Fourth, owing to the expensive precursors and lower
utilization efficiency of precursors, CVD methods have a higher
running cost. This also limits the economic viability of CVD
methods.
OBJECTS AND SUMMARY
[0028] In the fabrication of high-k dielectric film and metal
gates, the qualities of lower interface between Si and high-k
dielectric film, and upper interface between high-k dielectric film
and metal gates are of importance.
[0029] The upper interface quality particularly affects the
electron mobility, threshold voltage (V.sub.th) shift due to
pinning effect.
[0030] To improve the electron mobility and minimize V.sub.th
shift, the interface trap density must be lowered.
[0031] The interface trap density depends on high-k dielectric and
metal gate material qualities as well as fabrication process.
[0032] Conventionally, after the thermal annealing of high-k
dielectric, which is usually done in a separate annealing system,
wafers are exposed to normal atmosphere until they are placed in
metal gate deposition system.
[0033] Usually, high-k dielectrics show a better thermal stability,
however, depending on the dielectric materials, they show different
chemical properties after being exposed to normal atmosphere.
[0034] For example, an SiO.sub.2 layer can be grown at the Si and
high-k interface when HfO.sub.2 is selected as the high-k, since
oxygen diffuses through HfO.sub.2 film. The thickness of this
interface SiO.sub.2 also varies depending on the time exposed to
the normal atmosphere causing reliability issues.
[0035] If LaO or its alloys are used as high-k, moisture absorbs
into the film when exposed to the atmosphere; this changes trap
density in the film and interface. All these changes after being
exposed to atmosphere cause a decrease of film quality and thereby
the performance of end-product semiconductor devices is
decreased.
[0036] Therefore, an object of the present invention is to provide
a method to deposit a metal gate on a high-k dielectric film in the
fabrication of metal-oxide-semiconductor field effect transistors
(MOSFET) by which the qualities of high-k dielectric film and metal
gate material are improved thereby electron mobility is improved
and V.sub.th shift is minimized.
[0037] Also, another object of the present invention is to provide
a method to improve high-k dielectric film and metal gate interface
in the fabrication of MOSFET by which the interface trap density
can be lowered thereby electron mobility is improved and Vth shift
is minimized.
[0038] A further object of the present invention is to provide a
substrate treating system, which is suitable to be used in said
methods.
[0039] In order to achieve the above-described objects, a first
aspect of the present invention provides a method for depositing a
metal gate on a high-k dielectric film in the fabrication of MOSFET
comprising an annealing step annealing a substrate with high-k
dielectric film deposited thereon in a thermal annealing module,
and a depositing step depositing a metal gate material on said
annealed substrate in a metal gate deposition module, wherein the
annealing step and depositing step are carried out consecutively
without a vacuum break.
[0040] This method is conducted by a substrate treating system
comprising a wafer-handling platform including transfer means to
transfer a substrate and a processing module connected to said
wafer-handling platform, wherein said processing module includes at
least a thermal annealing module and a metal gate deposition
module, and said transfer means transfer the substrate between said
wafer-handling platform and said processing module without a vacuum
break.
[0041] A second aspect of the present invention provides a method
to deposit a metal gate on a high-k dielectric film in the
fabrication of MOSFET comprising an annealing step annealing a
substrate with high-k dielectric film deposited thereon in a
thermal annealing module, a cooling step cooling said annealed
substrate in a cooling module, and a depositing step depositing a
metal gate material on said cooled substrate in a metal gate
deposition module, characterized that said annealing step, cooling
step and depositing step are carried out consecutively without a
vacuum break.
[0042] This method is conducted by a substrate treating system
comprising a wafer-handling platform including transfer means to
transfer a substrate and processing module connected to said
wafer-handling platform, wherein said processing module includes at
least a thermal annealing module, a cooling module and a metal gate
deposition module, and said transfer means transfer the substrate
between said wafer-handling platform and said processing module
without a vacuum break.
[0043] A third aspect of the present invention provides a method to
deposit a metal gate on a high-k dielectric film in the fabrication
of MOSFET comprising a first depositing step depositing a high-k
dielectric film on a substrate in a high-k deposition module, an
annealing step annealing said substrate on which high-k dielectric
film is deposited in a thermal annealing module, a cooling step
cooling said annealed substrate in a cooling module, and a second
depositing step depositing a metal gate material on said cooled
substrate in a metal gate deposition module characterized that said
first depositing step, annealing step, cooling step and second
depositing step are carried out consecutively without a vacuum
break.
[0044] This method is conducted by a substrate treating system
comprising a wafer-handling platform including transfer means to
transfer a substrate and processing module connected to said
wafer-handling platform, wherein said processing module includes at
least a thermal annealing module, a cooling module, a high-k
deposition module, and a metal gate deposition module, and said
transfer means transfer the substrate between said wafer-handling
platform and said processing module without a vacuum break.
[0045] A fourth aspect of the present invention provides a method
to deposit a metal gate on a high-k dielectric film in the
fabrication of MOSFET comprising a first depositing step depositing
a thin thermal SiO.sub.2 film on a substrate in a thermal annealing
module, a first cooling step cooling said substrate in a cooling
module, a second depositing step depositing a high-k dielectric
film on a substrate in a high-k deposition module, an annealing
step annealing said substrate in a thermal annealing module, a
second cooling step cooling said annealed substrate in a cooling
module, and a third depositing step depositing a metal gate
material on said cooled substrate in a metal gate deposition
module, wherein the first depositing step, first cooling step,
second depositing step, annealing step, second cooling step and
third depositing step are carried out consecutively without a
vacuum break.
[0046] This method is conducted by a substrate treating system
comprising a wafer-handling platform including transfer means to
transfer a substrate and processing module connected to said
wafer-handling platform, wherein said processing module includes at
least a thermal annealing module, a cooling module, a high-k
deposition module, and a metal gate deposition module, and said
transfer means transfer the substrate between said wafer-handling
platform and said processing module without a vacuum break.
[0047] A fifth aspect of the present invention provides a method to
deposit a metal gate on a high-k dielectric film in the fabrication
of MOSFET according to any one of the before described first to
fourth aspects of the present invention wherein a metal gate formed
by said depositing step depositing a metal gate material comprises
of a plural film stack, and after said metal gate is formed the
substrate is further annealed consecutively in the thermal
annealing module without a vacuum break.
[0048] In this depositing method, the before described plural film
stack including different films, for example, a plural film stack
including different films is laminated. And, by the annealing step,
which is consecutively conducted after said metal gate material
comprised of a plural film stack is formed, the metal stack
materials are intermixed.
[0049] A sixth aspect of the present invention provides a method to
improve high-k dielectric film and metal gate interface in the
fabrication of MOSFET by depositing a metal gate on a high-k
dielectric film according to any one method of the before described
first to fifth aspect of the present invention.
[0050] A seventh aspect of the present invention provides a
substrate treating system comprising a wafer-handling platform
including transfer means to transfer a substrate and processing
module connected to said wafer-handling platform; wherein said
processing module includes at least a thermal annealing module and
a metal gate deposition module, and said transfer means transfer
the substrate between said wafer-handling platform and said
processing module without a vacuum break.
[0051] An eighth aspect of the present invention provides a
substrate treating system according to the seventh aspect of the
present invention wherein said processing module further includes a
cooling module and/or a high-k dielectric deposition module.
[0052] According to an embodiment of the present invention, an
improved method of depositing a metal gate on a high-k dielectric
film in the fabrication of MOSFET is provided by which the
qualities of high-k dielectric film and metal gate material are
improved, thereby the electron mobility is improved and Vth shift
is minimized.
[0053] Also, an improved method improving high-k dielectric film
and metal gate interface in the fabrication of MOSFET is provided
by which the interface trap density can be lowered, thereby the
electron mobility is improved and Vth shift is minimized.
[0054] Further, a substrate treating system which is suitable to be
used in the before described methods is provided.
[0055] Integration of thermal annealing system and metal gate
deposition system to a one wafer-handling platform improves the
high-k dielectric film and metal gate interface properties and
thereby improves electrical characteristics and device
performance.
BRIEF DESCRIPTIONS OF THE DRAWINGS
[0056] FIG. 1 shows a schematic diagram of integrated system used
in working example one.
[0057] FIG. 2 shows another configuration for working example
one.
[0058] FIG. 3 shows a schematic diagram of working example two.
[0059] FIG. 4 shows a schematic diagram of another integrated
system.
[0060] FIG. 5 shows a cross sectional view of angled-PVD module
provided in the integrated system shown in FIG. 4.
[0061] FIG. 6 shows a cross sectional view of thermal annealing
module provided in the integrated system shown in FIG. 1.
[0062] FIGS. 7(a) to (d) show the procedure of film deposition and
thermal annealing process.
[0063] FIG. 8 shows a schematic diagram of another integrated
system.
[0064] FIG. 9 shows a schematic diagram of another integrated
system.
[0065] FIG. 10 (a) shows uniform-counter lines of Hf film deposited
on 300 mm wafer, FIG. 10(b) shows the cross sectional uniformity of
Hf film.
[0066] FIG. 11 shows a variation of HfSi film composition depending
on applied DC power.
[0067] FIG. 12(a) shows uniform-counter lines of TaN film deposited
on 200 mm wafer, FIG. 12(b) shows the cross sectional uniformity of
TaN film.
[0068] FIG. 13 shows RBS data obtained for HfSiON film.
[0069] FIG. 14 shows a schematic diagram of wafer treating system
in which CVD chamber for depositing high-k dielectrics using CVD
technique is connected to central wafer-handling platform.
[0070] FIG. 15 shows a schematic view of MOSFET
EXPLANATION OF REFERENCE SIGNS USED tO DESCRIBE THE PREFERRED
EMBODIMENTS
[0071] 1. thermal annealing module [0072] 2. metal gate deposition
module [0073] 3. central wafer-handling platform [0074] 4.
substrate [0075] 5. wafer alligner [0076] 6. wafer load port [0077]
7. wafer unload port [0078] 8. cooling module [0079] 9. robot arm
[0080] 10. high-k dielectric deposition module [0081] 11.
angled-PVD module [0082] 12. angled-PVD module [0083] 13. wafer
loading/unloading equipment-front-end module [0084] 14. target
[0085] 15. target angle .alpha. [0086] 16. cathode [0087] 16a, 16b,
16c, 16d and 16e. cathodes [0088] 17. substrate holder [0089] 18.
central axis of substrate holder [0090] 19. substrate holder [0091]
20. wafer heating mechanism [0092] 21. gas inlet [0093] 22. gas
outlet [0094] 23. initially deposited very thin SiO.sub.2 or SiON
layer [0095] 24. starting material (film) [0096] 25. high-k
dielectric [0097] 26. gate electrode [0098] 27. chamber wall [0099]
28. vacuuming port [0100] 29. wafer in/out port [0101] 30. backing
plate [0102] 31. insulator [0103] 32. magnets [0104] 33. substrate
in/out port.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0105] Preferred embodiments of the present invention are described
in the following examples in detail using the attached
drawings.
Example 1
[0106] In FIG. 1, a thermal annealing module 1 and metal gate
deposition module 2 are connected to a central wafer-handling
platform 3, that is to say, a thermal annealing module 1 and metal
gate deposition module 2 are integrated to a central wafer-handling
platform 3.
[0107] A cross sectional view of the thermal annealing module 1 is
shown in FIG. 6. Preferably, the thermal annealing module 1 is a
rapid thermal annealing module. The thermal annealing module 1 such
as RTP module, shown in FIG. 6, is comprised of a substrate holder
19, a wafer heating mechanism 20 heating a substrate 4 placed on
the substrate holder 19, gas inlet 21, a gas outlet 22 and
substrate in/out port 33 as shown in FIG. 6.
[0108] Typically, the heating mechanism 20 is an infrared (IR)
heating process assisted by IR lamps. Usually, the thermal
annealing module 1 such as RTP module can heat a substrate 4 to a
temperature around 1000.degree.C. within several seconds. During
the substrate heating, substrate holder 19 may or may not be
rotated. The thermal annealing module 1 such as RTP module heats a
substrate under a low-pressure with an inert gas or mixture of
inert gas and a reactive gas.
[0109] The thermal annealing module 1 may employ any suitable
technique to heat the substrate 4 to a higher temperature, for
example IR lamps, furnace annealing, or RF heating. The annealing
temperature may vary from 100.degree. C. to 1200.degree. C. . The
actual annealing temperature may change depending on the high-k
materials. The annealing pressure is also not critical. The
pressure may vary from 10.sup.-7 Pa to atmospheric pressure.
[0110] The metal gate deposition technique conducted in the metal
gate deposition module 2 is also not important. The technique may
be PVD, thermal CVD or plasma enhanced CVD, or atomic layer
deposition. The deposition pressure, precursor gas or gas mixtures
depend on the type of metal gate.
[0111] In addition to the thermal annealing and metal gate
deposition modules 1, 2, a wafer loading/unloading
equipment-front-end module 13 is attached to the central platform
3. Therefore, a thermal annealing module 1, metal gate deposition
module 2 and a wafer loading/unloading equipment-front-end module
13 are integrated to a central wafer-handling platform 3. The wafer
loading/unloading equipment-front-end module 13 comprises a wafer
aligner 5, wafer load port 6 and unload port 7.
[0112] The substrate 4 with high-k dielectric film deposition
thereon is placed in the thermal annealing module 1 in FIG. 1.
Substrate 4 is then subjected to thermal annealing process in the
thermal annealing module 1 at a desired temperature. The thermal
annealing may be a single step or a two-step process with different
gas atmospheres.
[0113] Then, substrate 4 is transferred into the metal gate
deposition module 2 via the central wafer-handling platform 3 by
the transfer means such as robot arm 9. And in the metal gate
deposition module 2, metal gate material is deposited. The metal
gate material may be any suitable material with appropriate
electrical properties. For example metal gate material may be TaN,
HfSi , RuTa, Ir, W, etc.
[0114] As described before, the annealing step annealing a
substrate with high-k dielectric film deposited thereon in a
thermal annealing module and depositing step depositing a metal
gate material on said annealed substrate in a metal gate deposition
module are carried out consecutively without a vacuum break.
[0115] FIG. 2 shows that a cooling module 8 is connected to the
central wafer-handling platform 3 in addition to the configuration
shown in FIG. 1. That is to say, in FIG. 2, a thermal annealing
module 1, metal gate deposition module 2, a cooling module 8 and a
wafer loading/unloading equipment-front-end module 13 are
integrated to a central wafer-handling platform 3.
[0116] Using the integrated system shown in FIG. 2, after the
thermal annealing of high-k dielectric mentioned above, one can
cool down the substrate 4 before placing it inside the metal gate
module 2.
[0117] That is to say, using the integrated system shown in FIG. 2,
firstly conducting an annealing step annealing a substrate with
high-k dielectric film deposited thereon in a thermal annealing
module, then cooling said annealed substrate in a cooling module,
and then depositing a metal gate material on said cooled substrate
in a metal gate deposition module, wherein said annealing step,
cooling step and depositing step can be carried out consecutively
without a vacuum break.
[0118] As described before, the thermal annealing module and metal
gate deposition module are integrated to a single central
wafer-handling platform, so that immediately after the high-k
annealing process, wafers can be transferred into metal gate
deposition module without a vacuum break and deposit metal
gate.
[0119] Also, the thermal annealing module, the cooling module, and
metal gate deposition module are integrated to a single central
wafer-handling platform, so that immediately after the high-k
annealing process and cooling process, wafers can be transferred
into the metal gate deposition module without a vacuum break and
deposit metal gate.
[0120] Integration of thermal annealing system and metal gate
deposition system to a one central wafer-handling platform, or
integration of thermal annealing system, cooling system and metal
gate deposition system to a one central wafer-handling platform can
improve the high-k dielectric film and metal gate interface
properties and thereby improve electrical characteristics and
device performance.
Example 2
[0121] FIG. 3 shows an example which is an extension of working
example 1, wherein there is an additional high-k dielectric
deposition module 10 attached to the central wafer handling
platform 3 described in working example 1.
[0122] In the example shown in FIG. 3, a high-k dielectric
deposition module 10 is connected to the central wafer-handling
platform 3 in addition to the configuration shown in FIG. 2. That
is to say, in FIG. 3, a thermal annealing module 1, metal gate
deposition module 2, a cooling module 8, a high-k dielectric
deposition module 10 and a wafer loading/unloading
equipment-front-end module 13 are integrated to a central
wafer-handling platform 3.
[0123] A cooling module 8 may be removed from the configuration
shown in FIG. 3.
[0124] The high-k dielectric deposition technique can be any
desired technique, for example PVD, CVD, MOCVD or ALD. The
parameters such as deposition pressure, precursor gases,
temperature etc., depend on the type of deposition technique and
high-k material.
[0125] First, high-k dielectric, for example HfO.sub.2, is
deposited on a substrate 4 by placing a wafer in high-k dielectric
deposition module 10. One can also deposit a metal or metal alloy
in the high-k deposition module 10, for example Hf, HfSi, HfAl
etc., to be oxidized in the thermal annealing module 1. The
substrate 4 is then transferred into the thermal annealing module 1
and performs the annealing process. The annealing is usually a
single step in oxygen or in an inert gas environment. One can
however, carry on a two-step annealing process where in the first
step annealing is done in an oxygen atmosphere at relatively a
lower temperature, while in the second step annealing is done in an
inert gas environment at relatively a higher temperature.
[0126] Then by using the cooling module 8, the wafer is cooled
down. Thereafter, the wafer is transferred into metal gate
deposition module 2, and deposits a metal.
[0127] When the configuration given in FIG. 3 is used, high-k
deposition, thermal annealing and metal gate deposition can be done
without a vacuum break. This results in further improvement of film
quality and thereby semiconductor device quality.
[0128] Using the integrated system shown in FIG. 3, the following
process can be conducted. Firstly, depositing a high-k dielectric
film on a substrate in a high-k deposition module, annealing said
substrate on which high-k dielectric film is deposited in a thermal
annealing module, cooling said annealed substrate in a cooling
module, and then depositing a metal gate material on said cooled
substrate in a metal gate deposition module wherein said first
depositing step, annealing step, cooling step and second depositing
step are carried out consecutively without a vacuum break.
[0129] Also, the following process can be conducted. After the
first depositing step depositing a thin thermal SiO.sub.2 film on a
substrate in a thermal annealing module, cooling said substrate in
a cooling module, depositing a high-k dielectric film on said
substrate in a high-k deposition module, annealing said substrate
in a thermal annealing module, cooling said annealed substrate in a
cooling module, and then depositing a metal gate material on said
cooled substrate in a metal gate deposition module wherein said
first depositing step, first cooling step, second depositing step,
annealing step, second cooling step and third depositing step are
carried out consecutively without a vacuum break.
[0130] As described before, the thermal annealing module, the
cooling module, the high-k deposition module, and the metal gate
deposition module are integrated to a single central wafer-handling
platform, so that immediately after the high-k annealing process
and cooling process, wafers can be transferred into metal gate
deposition module without a vacuum break and deposit metal
gate.
[0131] Integration of the thermal annealing system, the cooling
module, the high-k deposition module, and the metal gate deposition
module to a one central wafer-handling platform can improve the
high-k dielectric film and the metal gate interface properties and
thereby improves electrical characteristics and device
performance.
Example 3
[0132] FIG. 4 shows a schematic diagram of the integrated system
comprised of two angled-PVD modules 11 and 12, one thermal
annealing module 1, a cooling module 8, a central wafer-handling
platform 3, and a wafer loading/unloading equipment-front-end
module 13.
[0133] The hardware configuration of both angled-PVD systems 11 and
12 are the same except the target materials fixed to each cathode.
A cross sectional diagram of an example of an angled-PVD module
which can be adopted in the substrate treating system of the
present invention is shown in FIG. 5.
[0134] The angled-PVD module 11 and 12 is comprised of a chamber
having a chamber wall 27, a vacuuming port 28 and a wafer in/out
port 29. The substrate holder 17 is provided in the chamber as
shown in FIG. 5.
[0135] The angled-PVD modules 11 and 12 employ off-axis sputtering
technology where substrate 4 and target 14 surfaces are not
parallel as in conventional PVD systems. Instead these two surfaces
make an angle a (denoted by numeral 15) as shown in FIG. 5. This
angle .alpha.(15) is however, not critical and can lie in the range
of 10.degree. to 90.degree., but typically lies around 45.degree..
Each angled-PVD system may have one or more angled targets. For
example, as one cathode 16 is shown in FIG. 5, each PVD system
shown in FIG. 4 accommodates 5 cathodes (16a, 16b, 16c, 16d and
16e) and thereby 5 targets 14.
[0136] In each cathode, as shown in FIG. 5, backing plate 30 is
provided on the opening of cathode 16 by insulator 31. Target 14 is
supported by the front side of the backing plate 30, and magnets 32
are provided at the back side of backing plate 30. The magnets 32
are rotated during film deposition.
[0137] A target 14 made of a metal, metal nitride or metal oxide or
a semiconductor is fixed to each cathode 16a to 16e. Each cathode
is supplied with a DC, as shown in FIG. 5, or RF electrical power
to ignite and maintain a plasma. The ions in the plasma sputter the
target material and these sputtered atoms are deposited on the
substrate 4 placed on substrate holder 17.
[0138] The substrate holder 17 where a substrate 4 is placed for
the film deposition rotates around its central axis 18 during film
deposition. The rotation of substrate holder 17 is of importance to
obtain a uniform film thickness over the wafer surface since
sputtered atoms are coming with an angle.
[0139] The PVD module can accommodate 5 cathodes (16a, 16b, 16c,
16d, 16e) at the same time. These cathodes 16a to 16e are fixed to
the ceiling of the angled PVD modules 11 and 12 respectively with
an angle .alpha.(15) with respect to the surface of substrate 4.
This angle .alpha.(15) is not critical and can be varied in the
range of 0 to 90.degree., but typically lies around 45.degree.. In
each cathode 16, there is a metal or dielectric target 14 as an
integrated part of the cathode 16. Above the target 14, there is a
magnet 32, which is rotated during film deposition. The magnet 32
however, is not essential. Use of magnet 32 increases the plasma
density and confines the plasma to the region below the target
suppressing diffusion towards the wall 27 of the chamber of PVD
module. The diameter of a target 14 is also not critical and is
usually around 200 mm. The target 14 is simply a planar plate
firmly fixed to a backing plate 30. The backing plate 30 is usually
cooled using circulating water or any other suitable liquid. The
cooling mechanism of the backing plate 30 is not shown for the
clarity of the diagram.
[0140] In FIG. 5 numeral 35 indicates a shutter.
[0141] Each cathode 16 is electrically isolated from the rest of
the hardware and connected to a DC or RF electrical supply unit. In
FIG. 5 only a DC power source is shown. The DC or RF power applied
to a target 14 is not critical but typically lies lower than 500 W.
The reason is high-k materials that should be deposited on a
substrate 4 should be very thin. Therefore, in order to control the
film thickness to a greater accuracy, film deposition rate must be
lowered. So that, by measuring the depositing time, film thickness
can be controlled accurately.
[0142] The angled PVD modules 11 and 12 are vacuumed to a lower
pressure and maintained at a low-pressure before and after plasma
is ignited. The inside pressure in the chamber of angled PVD
modules 11 and 12 is not critical, however, deposition is usually
carried out at a pressure lower than 1 Pa.
[0143] It is possible to obtain extremely uniform depositing film,
by considering and comparing the mean-free-path of gas atoms in the
PVD modules 11 and 12 with respect to the substrate-to-target
distance.
[0144] The sputter deposition can be carried out with the use of an
inert gas plasma, such as Ar plasma or using a gas mixture such as
Ar+O.sub.2 or Ar+N.sub.2. When a reactive gas mixture is used,
sputtered atoms react with the gaseous species and form a different
product such as metal nitride or oxide and then are deposited on
the water surface. The film deposition is usually carried out at a
pressure lower than 1 Pa, however, as this is not critical, one can
use a different pressure for the film deposition.
[0145] The film deposition can be done using a single target 14 by
supplying DC or RF power to that appropriate target. Or, film
deposition can be done by a co-sputtering process where RF or DC
power is supplied to two or several targets 14, which are provided
at each cathode 16a to 16e, at the same time. In this case, the
atomic composition of alloy material is controlled by adjusting the
DC or RF electrical power applied to each target.
[0146] One of the angled-PVD systems may be used for high-k
dielectrics while the other may be used for gate electrode
deposition.
[0147] The thermal annealing module 1 used in the configuration of
FIG. 4 is the same as shown in FIG. 6 and described in Example
1.
[0148] When a substrate 4 with a film deposited in angled PVD
module 11 is placed in the thermal annealing module 1 such as RTP
module, it is heated to a higher temperature usually over
400.degree. C. under a reactive gas mixture, preferably with
Ar+O.sub.2 gas mixture. During this heating, the metal, metal-alloy
or metal nitride films get oxidized and become a dielectric.
[0149] The heating by the thermal annealing module 1, such as RTP
module, can be carried out in two or more steps under the same or
different gas environments. In the first step, for example heating
is carried out only to oxidize the film deposited on a wafer
surface, and in the second or later steps wafer is heated to even a
higher temperature to mix the oxidized film with underlying Si or
any other underlying film.
[0150] The cooling module 8 is comprised of at least a wafer stage
cooled to a lower temperature.
[0151] Again, there may be an electrostatic chuck mechanism
integrated to the wafer stage to clamp the wafer on to the wafer
stage. This is important if the wafer cooling must be done at a
higher rate. The pressure inside the cooling module 8 is not
important and can be in the range of atmospheric pressure to lower
pressures as low as 10.sup.-7 Pa.
[0152] The central wafer-handling platform 3 includes a transfer
means such as a robot arm 9 that delivers substrate 4 between
angled PVD module 11 and central wafer-handling platform 3, thermal
annealing module 1 and central wafer-handling platform 3, angled
PVD module 12 and central wafer-handling platform 3, cooling module
8 and central wafer-handling platform 3, and wafer
loading/unloading equipment-front-end module 13 and central
wafer-handling platform 3, respectively, without a vacuum
break.
[0153] The wafer loading/unloading equipment-front-end module 13 is
also comprised of at least a wafer handling robot arm and one or
several stages to place wafer cassettes. These are not shown in
figures for simplicity.
[0154] A method of high-k and metal gate preparation is as follows
and explained with reference to FIG. 7.
Step-1 Deposit preliminary film for high-k dielectric Step-2
Thermally anneal under oxygen atmosphere to form high-k dielectric
Step-3 Cool down the wafer Step-4 Deposit metal electrode material.
Detailed description of the deposition method:
Step-1
[0155] The starting wafer may or may not have an initially
deposited very thin SiO.sub.2 or SiON layer 23. This is shown in
FIG. 7(a).
[0156] A starting material 24 for high-k dielectric is deposited on
substrate 4 using one of the angled-PVD modules (FIG. 7(b)). The
starting material 24 may be a metal, preferably refractory metal
such as Hf, Ta, Zr etc., metal nitride such as HfN, TaN, TiN etc.,
metal alloy such as HfTa, HfTi, etc., metal-semiconductor alloy
such as HfSi etc. or metal alloy nitrides such as TaSiN etc.
[0157] Again, one can deposit two or several films mentioned above
as a stacked configuration. For example, Hf/SiN/Hf, HfN/AIN,
Hf.
[0158] Usually, Hf, Zr, Ti, or Ta is used as a metal target 14.
However, other metal targets can be used. In case a
metal-semiconductor alloy is deposited, preferably the
semi-conducting material is Si.
[0159] Though it is not critical, the film thickness of the above
starting materials is usually kept less than 5 nm, typically around
2 nm.
Step-2
[0160] After the deposition of starting film 24 as described above,
substrate 4 is transferred to thermal annealing module 1. The
substrate 4 is heated to a higher temperature usually over
400.quadrature., under an oxygen gas atmosphere, so that starting
material gets oxidized (FIG. 7(c)) forming a high-k dielectric 25.
The heating process can be carried out as a single step or several
steps. Usually, a heating procedure with two steps or several steps
is more suitable to control the chemical reaction during annealing
process. For example, first the film is heated to 400.quadrature.
to oxidize the metallic elements in the starting material. If the
film is heated to a very high temperature at once, for example to
800.quadrature., metallic elements in the film may form their
silicides, which are stable and show metallic features. Once the
film is properly oxidized at a relatively lower temperature such as
400.quadrature., temperature is raised to a higher value, for
example to 900.quadrature., preferably in an inert gas environment.
If metal stacks of different metals are used as the starting
material, high-temperature annealing is important for
inter-diffusion of each material and to form a uniform film
composition.
Step-3
[0161] After completion of thermal annealing process, substrate 4
is transferred to the cooling module 8 and cooled to a desired
temperature, preferably to the room temperature.
Step-4
[0162] The substrate 4 is transferred to the other angled-PVD
module and deposited a gate electrode 26 (FIG. 7(d)).
[0163] The gate material may be a metal such as Ta, Ru, Hf etc., a
metal nitride such as TiN, HfN, TaN etc., metal alloy such as RuTa,
HfTa, etc., metal semiconductor alloy such as HfSi, TaSi etc.,
metal semiconductor alloy nitrides such as TaSiN etc. or a stack of
above mentioned films such as Hf/TaN/TiN, Ru/Ta/TaN etc.
[0164] In depositing film stack one on each other, substrate does
not have to be removed from the angled-PVD module to deposit each
film. Since this PVD module has five cathodes 16a to 16e and
supports up to 5 different targets, by fixing appropriate targets
one can deposit any desired metal stacks in the same angled-PVD
module.
[0165] After the gate electrode deposition, the substrate may
subject to thermal annealing process, particularly if metal stacks
are deposited. During this thermal annealing process, metal stacks
inter-diffuse and form a new uniform composition. Otherwise, one
can take the wafer directly out from the integrated system shown in
FIG. 4 after the gate electrode deposition.
[0166] Preferably, before placing a wafer in the above integrated
system, the substrates are treated as follows to get improved
electrical properties.
[0167] 1. The substrate is cleaned with diluted HF solution to
remove native oxide on the surface
[0168] 2. Dry the substrate
[0169] 3. Deposit very thin layer of thermal SiO.sub.2 (eg. 1 nm)
(eg. Initially deposited film 23 shown in FIG. 7(a)). This process
can be conducted in the thermal annealing module 1.
[0170] The reason for the use of thin SiO.sub.2 layer 23 on Si
substrate 4 is that after the preparation of overall film
deposition process as described-above, a fraction of originally
deposited SiO.sub.2 layer 23 remains at interface between Si
substrate 4 and high-k dielectric 25 as shown in FIG. 7(c) and
7(d). This results in a lower leakage current, lower voltage
hysterias, and improved electron mobility in the channel region in
a MOSFET.
[0171] These angled PVD modules give 11, 12 shown in FIG. 5 and
used in the configuration of FIG. 4 can achieve higher deposition
rate. As a result of higher deposition rate, an economically viable
throughput can be obtained by the present invention.
Example 4
[0172] In FIG. 8, there are two angled PVD modules 11 ad 12, two
thermal annealing modules 1a and 1b, one cooling module 8 and wafer
loading/unloading equipment front-end module 13 attached to a
central wafer-handling platform 3.
[0173] Compared to the integrated system explained in working
example 3, there is an additional thermal annealing module in this
working example 4. Except for this addition, all the other hardware
are the same as that explained in working example 3. This
additional thermal annealing module is used for high-temperature
annealing of gate electrode material. Use of separate thermal
annealing modules to anneal starting material to form high-k
dielectric and gate electrode, increases the throughput and
minimize cross contamination. Except for the above-mentioned
difference, all the other processing steps and procedures are the
same as that explained in working example 3.
Example 5
[0174] FIG. 9 shows a schematic diagram of the integrated system
for the deposition of high-k dielectric, which is comprised of
angled PVD module 11, thermal annealing module 1 such as RTP
module, central wafer-handling platform 3 and a wafer
loading/unloading equipment-front-end module (EFEM) 13.
[0175] The construction and mechanism of the angled PVD module 11
is described in Example 3 and shown in FIG. 5. So that, they are
omitted from this example.
[0176] FIG. 10(a) shows a Hf film uniformity deposited on a 300 mm
wafer at a pressure of 0.015 Pa using the angled PVD module 11. The
other parameters used for that deposition are as follows.
Target-to-substrate vertical distance=250 mm, DC power applied to
Hf target=300 W, substrate holder rotation speed=240 rpm, Plasma
gas=Ar. The standard deviation (.sigma.) of larger number of film
thickness measurements is usually given as the film non-uniformity.
The standard deviation (.sigma.) of 49-points measurement on Hf
film given in FIG. 10(a) is 0.16%. The lines shown in FIG. 10(a)
are the constant-uniform contours 36. The numeral 37 given at each
contours is the normalized uniformity. FIG. 10(b) shows the
normalized uniformity across a diameter line.
[0177] In case of bi-metal or metal alloy depositions, two or many
targets (16a, 16b,) are given DC or RF power simultaneously. By
adjusting the DC or RF power applied to each cathode, the
composition of metal alloy can be varied. For example FIG. 11 shows
controllability of HfSi composition. The deposition condition for
FIG. 11 is as follows.
[0178] Process gas=Ar, Pressure=0.015 Pa, Hf target DC power=70 W,
Si target DC power=30 W to 130 W, Substrate-to-target distance=250
mm. The Hf fraction of HfSi film can be controlled from 55% to 82%
(or Si fraction from 45% to 18%) by controlling the DC power
applied to Si target. In FIG. 11, variation of Hf fraction in HfSi
film is denoted numeral 38 and variation of Si fraction in HfSi
film is denoted numeral 39.
[0179] In case of reactive sputter depositions, a reactive gas, for
example oxygen or nitrogen is added to the PVD module in addition
to an inert gas, for example Ar. The reactive gas decomposes in the
plasma and reacts with the sputtered atom and then deposits on the
wafer surface. For example, FIG. 12(a) shows film uniformity of TaN
film deposited by reactive sputtering method using Ar+N.sub.2 gas
mixture with the following condition.
[0180] Ta target DC power=300 W, Plasma gas=Ar, Pressure=0.015 Pa,
Ar flow rate=30 sccm, N.sub.2 flow rate=10 sccm,
substrate-to-target distance=250 mm.
[0181] FIG. 12(a) shows the constant uniform contours 36 while FIG.
12(b) shows the normalized uniformity across a diameter line. The
standard deviation of 49-thickness measurement on TaN film shown in
FIG. 12 is 0.13%.
[0182] After a film is deposited in PVD module 11, substrate 4 is
transferred to the thermal annealing module 1 without a vacuum
break.
[0183] The thermal annealing module 1 is an RTP module shown in
FIG. 6 and described in the before described example 1.
[0184] The heating by the thermal annealing module 1 such as RTP
module can be carried out in two or more steps under the same or
different gas environments. In the first step, for example, heating
is carried out only to oxidize the film deposited on a wafer
surface, and in the second or later steps wafer is heated to an
even higher temperature to mix the oxidized film with underlying Si
or any other underlying film.
[0185] For example, HfSiON film is fabricated with the following
procedure.
[0186] Started with p-type Si wafer
[0187] Cleaned with HF to remove native oxide
[0188] Deposited 1 nm thermal SiO.sub.2
[0189] Deposited 1 nm HfN by placing in the PVD module (11)
[0190] Placed wafer in RTP module (1)
[0191] Annealed at 400 for 30 sec. in an oxygen ambient
[0192] Annealed at 800 for 30 sec. in an inert gas ambient
[0193] Wafer is taken out and film is evaluated.
[0194] During the first annealing step HfN film gets oxidized and
form HfON. During the second annealing step, HfON and underlying
SiO.sub.2 film gets intermixed and form HfSiON. RBS spectra
obtained for the above film is shown in FIG. 13, which clearly
shows the film is HfSiON.
[0195] It should be noted that after the RTP process, a Ti film is
deposited as a capping layer to prevent further oxidation of
prepared high-k film.
[0196] During the second RTP process only a fraction of initially
deposited thermal SiO.sub.2 film is consumed to form HfSiON.
Therefore, a thin SiO.sub.2 layer remains below the HfSiON film
just above the semiconductor.
[0197] It is important to have a very thin layer of thermal
SiO.sub.2 remaining below the HfSiON film to improve the electron
mobility in the channel region 107 (FIG. 15). So that one has to
control the RTP temperature and time to consume only a fraction of
thermal SiO.sub.2. By this method, one can therefore, have very
thin thermal SiO.sub.2 layer, for example 5 angstrom, under HfSiON
layer. The importance of this process is that there is no reliable
technique in directly depositing such a thin SiO.sub.2 layer.
[0198] HfSiON is considered as a high-k material with a relative
dielectric constant between 15-24 depending on film
composition.
[0199] Similar to the method explained above, one can deposit many
other different high-k materials using PVD module and RTP module
without having a vacuum-break.
[0200] Since this process does not involve vacuum-break, the
overall process is very reliable and repeatable, so that this
process can be confidently apply in actual device fabrications.
[0201] As described before, a PVD (physical vapor deposition)
module and RTP (rapid thermal processing) module are integrated
together with the use of wafer transfer module and EFEM (equipment
front-end module), wherein first a metal, metal nitride or metal
oxide film is deposited on a substrate by placing in PVD module and
secondly the wafer is subjected to RTP process to convert metal
film into dielectric and/or improve dielectric properties. The film
deposition step and RTP process is carried out without a vacuum
break so that film deposited by this procedure gives repeatable and
reliable properties.
[0202] The present invention is not limited to the preferable
examples described above, and may be modified to various
embodiments within the technological scope defined by the
accompanying claims and equivalents thereof.
* * * * *