U.S. patent application number 12/288944 was filed with the patent office on 2009-03-05 for angled implantation for removal of thin film layers.
Invention is credited to Justin K. Brask, Michael L. Hattendorf, Jack Kavalieros, Matthew V. Metz, Justin S. Sandford.
Application Number | 20090057788 12/288944 |
Document ID | / |
Family ID | 37875684 |
Filed Date | 2009-03-05 |
United States Patent
Application |
20090057788 |
Kind Code |
A1 |
Hattendorf; Michael L. ; et
al. |
March 5, 2009 |
Angled implantation for removal of thin film layers
Abstract
Embodiments of the invention provide a device with a
reverse-tapered gate electrode and a gate dielectric layer with a
length close to that of the gate length. In an embodiment, this may
be done by altering portions of a blanket dielectric layer with one
or more angled ion implants, then removing the altered portions of
the blanket dielectric layer.
Inventors: |
Hattendorf; Michael L.;
(Beaverton, OR) ; Brask; Justin K.; (Portland,
OR) ; Sandford; Justin S.; (Tigard, OR) ;
Kavalieros; Jack; (Portland, OR) ; Metz; Matthew
V.; (Hillsboro, OR) |
Correspondence
Address: |
INTEL CORPORATION;c/o INTELLEVATE, LLC
P.O. BOX 52050
MINNEAPOLIS
MN
55402
US
|
Family ID: |
37875684 |
Appl. No.: |
12/288944 |
Filed: |
October 24, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11293753 |
Dec 1, 2005 |
|
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12288944 |
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Current U.S.
Class: |
257/412 ;
257/E29.255 |
Current CPC
Class: |
H01L 21/31111 20130101;
H01L 21/28114 20130101; H01L 29/517 20130101; H01L 21/26586
20130101; H01L 21/32137 20130101; H01L 29/4958 20130101; H01L
21/31155 20130101; H01L 29/495 20130101; H01L 21/32136 20130101;
H01L 29/42376 20130101; H01L 29/66545 20130101; H01L 29/4966
20130101 |
Class at
Publication: |
257/412 ;
257/E29.255 |
International
Class: |
H01L 29/78 20060101
H01L029/78 |
Claims
1. A semiconductor device, comprising: a substrate; a gate
dielectric layer on the substrate, the gate dielectric layer having
a length; a gate electrode on the gate dielectric layer, the gate
electrode having a gate length adjacent the gate dielectric layer,
the gate electrode having reverse-tapered sidewalls so the gate
electrode has an intermediate length further from the gate
dielectric layer than the gate length, the intermediate length
being greater than the gate length; and wherein the length of the
gate dielectric layer is between about 120% and about 85% of the
gate length.
2. The device of claim 1, wherein at least a portion of the gate
electrode sidewalls has a sidewall angle between the gate electrode
sidewalls and a top surface of the substrate, the sidewall angle
being between about eighty-five degrees and about seventy-five
degrees.
3. The device of claim 1, wherein the gate electrode includes a
work function metal gate layer comprising a first metal and a
second metal gate layer comprising a second metal different than
the first metal on the work function metal gate layer.
4. The device of claim 3, wherein the work function metal gate
layer is conformal to the bottom and sidewalls and has a thickness
between about 50 angstroms and about 100 angstroms.
5. The device of claim 1, wherein the length of the gate dielectric
layer is between about 105% and about 97% of the gate length.
6. The device of claim 1, wherein the gate length is between about
18 nanometers and about 22 nanometers and the length of the gate
dielectric layer is between about 23.2 nanometers and about 17.4
nanometers.
7. The device of claim 1, wherein the gate dielectric layer has a
footing less than or equal to about six angstroms on each side.
8. The device of claim 1, wherein the gate dielectric layer has an
undercut less than or equal to about three angstroms on each side.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional application of Ser. No.
11/293,753 filed Dec. 1, 2005, entitled "ANGLED IMPLANTATION FOR
REMOVAL OF THIN FILM LAYERS".
BACKGROUND OF THE INVENTION
[0002] Dry etching using tools such as plasma provide directional
etching. However, such etching methods lack selectivity and may
etch into materials below those desired to be etched, or the
materials desired to be etched may be blocked from the plasma by
structures above. Certain wet etchants have high selectivity as
paired with substrates and target materials. However, many of these
wet etchants etch at the same rate in all directions of material
exposure (i.e. are isotropic), and may leave excessively large
footings or undercuttings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] FIGS. 1a through 1e are cross sectional side views that
illustrate the semiconductor device of one embodiment of the
present invention.
[0004] FIG. 2 is a cross sectional side view that illustrates a
substrate from which the device may be formed.
[0005] FIG. 3 is a cross sectional side view that illustrates a
blanket dielectric layer formed on the substrate.
[0006] FIG. 4 is a cross-sectional side view that illustrates a
blanket gate electrode layer 206 formed on the blanket dielectric
layer.
[0007] FIG. 5 is a cross-sectional side view that illustrates a
first gate that may be formed by patterning the blanket gate
electrode layer.
[0008] FIG. 6 is a cross-sectional side view that illustrates ions
being implanted into portions of the blanket dielectric layer.
[0009] FIG. 7 is a cross-sectional side view that illustrates
altered regions of the blanket dielectric layer after ion
implantation.
[0010] FIG. 8 is a cross-sectional side view that illustrates a
second set of ions being implanted into portions of the blanket
dielectric layer in a second ion implantation process.
[0011] FIG. 9 is a cross-sectional side view that illustrates
altered regions of the blanket dielectric layer after the second
ion implantation.
[0012] FIG. 10 is a cross-sectional side view that illustrates the
formation of the gate dielectric layer by removal of the damaged
region of the blanket dielectric layer.
[0013] FIG. 11 is a cross-sectional side view that illustrates
spacers formed adjacent the sidewalls of the gate electrode and
source and drain regions formed in the substrate.
[0014] FIG. 12 is a cross-sectional side view that illustrates a
first interlayer dielectric layer (ILD layer).
[0015] FIG. 13 is a cross-sectional side view that illustrates a
trench formed by removal of the first gate electrode.
[0016] FIG. 14 is a cross-sectional side view that illustrates a
first metal gate electrode layer formed in the trench.
[0017] FIG. 15 is a cross-sectional side view that illustrates the
second gate electrode layer formed on the first metal gate
layer.
[0018] FIG. 16 is a block diagram that illustrates a system in
accordance with one embodiment of the present invention.
DETAILED DESCRIPTION
[0019] In various embodiments, an apparatus and method relating to
the formation of a semiconductor device are described. In the
following description, various embodiments will be described.
However, one skilled in the relevant art will recognize that the
various embodiments may be practiced without one or more of the
specific details, or with other replacement and/or additional
methods, materials, or components. In other instances, well-known
structures, materials, or operations are not shown or described in
detail to avoid obscuring aspects of various embodiments of the
invention. Similarly, for purposes of explanation, specific
numbers, materials, and configurations are set forth in order to
provide a thorough understanding of the invention. Nevertheless,
the invention may be practiced without specific details.
Furthermore, it is understood that the various embodiments shown in
the figures are illustrative representations and are not
necessarily drawn to scale.
[0020] Reference throughout this specification to "one embodiment"
or "an embodiment" means that a particular feature, structure,
material, or characteristic described in connection with the
embodiment is included in at least one embodiment of the invention,
but do not denote that they are present in every embodiment. Thus,
the appearances of the phrases "in one embodiment" or "in an
embodiment" in various places throughout this specification are not
necessarily referring to the same embodiment of the invention.
Furthermore, the particular features, structures, materials, or
characteristics may be combined in any suitable manner in one or
more embodiments. Various additional layers and/or structures may
be included and/or described features may be omitted in other
embodiments.
[0021] Various operations will be described as multiple discrete
operations in turn, in a manner that is most helpful in
understanding the invention. However, the order of description
should not be construed as to imply that these operations are
necessarily order dependent. In particular, these operations need
not be performed in the order of presentation. Operations described
may be performed in a different order than the described
embodiment. Various additional operations may be performed and/or
described operations may be omitted in additional embodiments.
[0022] A device with a reverse-tapered (i.e. wider toward the top
than toward the bottom) gate electrode and its method of
fabrication is disclosed herein. The device may be a transistor.
There is a gate dielectric under the gate electrode. The gate
dielectric has a length close to a gate length measured adjacent
the gate dielectric. The gate dielectric layer may lack a large
footing beyond the gate length and a large undercut beneath the
gate electrode. Such large footings and undercuts may decrease
transistor performance. The dielectric layer without large footing
or undercut may be fabricated by using angled ion implants to alter
a blanket dielectric layer, then removing the altered portions.
[0023] FIG. 1a is a cross sectional side view that illustrates the
semiconductor device 100 of one embodiment of the present
invention. In the cross-sectional side view of FIG. 1a, a Z-axis is
perpendicular to a top surface of a substrate 102 and an X-Y plane
(X is not shown as it extends into the plane of the Figure)
substantially coincides with a top surface of the substrate 102. As
used herein, the "length" of portions of the device 100 is measured
in the Y direction and the height in the Z direction. As used
herein, angles are measured from the X-Y plane, with an angle
perpendicular to the X-Y plane (in the Z-direction) being the
maximum possible angle, of ninety degrees. Thus two angles referred
to here may be the same number of degrees from the X-Y plane, but
may be oriented in a different direction so that they point away
from each other.
[0024] The device 100 may be a transistor formed on the substrate
102 in some embodiments. Substrate 102 may comprise any material
that may serve as a foundation upon which a semiconductor device
may be built. The substrate 102 may be a silicon containing
substrate 102. In an embodiment, the substrate 102 may comprise a
semiconductor material such as single crystal silicon, gallium
arsenide or another suitable material. In some embodiments, the
substrate 102 may be a bulk semiconductor substrate 102, while in
other embodiments, the substrate 102 may be a
semiconductor-on-insulator ("SOI") substrate. The substrate 102 may
include multiple different layers and structures in some
embodiments, while in other embodiments the substrate 102 may just
be one layer of material.
[0025] There may be a gate dielectric layer 104 on the substrate
102 in some embodiments. The gate dielectric layer 104 may comprise
a material with a high dielectric constant value. Such materials
are referred to as high-k materials. The gate dielectric layer 104
may comprise, for example, hafnium oxide, hafnium silicon oxide,
lanthanum oxide, lanthanum aluminum oxide, zirconium oxide,
zirconium silicon oxide, titanium oxide, tantalum oxide, barium
strontium titanium oxide, barium titanium oxide, strontium titanium
oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide,
and lead zinc niobate. Although a few examples of materials that
may be used to form a high-k gate dielectric layer 104 are
described here, the gate dielectric layer 104 may be made from
other materials that serve to reduce gate leakage in other
embodiments.
[0026] In embodiments where the gate dielectric layer 104 comprises
a high-k material, the gate dielectric layer 104 may have a k-value
higher than about 7.5. In other embodiments, the high-k gate
dielectric layer 104 may have a k-value higher than about 10. In
other embodiments, the high-k gate dielectric layer 104 may
comprise a material with a k-value of about 12, or may comprise a
material with a higher k-value than that. In other embodiments, the
high-k gate dielectric layer 104 may have a k-value between about
15 and about 25, e.g. HfO.sub.2. In yet other embodiments, the
high-k gate dielectric layer 104 may have a k-value even
higher.
[0027] There may be a gate electrode 106 on the gate dielectric
layer 104 in some embodiments. Only one layer is shown in the gate
electrode 106 illustrated in FIG. 1a. However, in other
embodiments, the gate electrode 106 may comprise multiple layers of
materials. The gate electrode 106 may comprise a metal gate
electrode layer or another material, such as polysilicon. In some
embodiments, the gate electrode 106 may comprise a metal gate
electrode layer as the only layer of the gate electrode 106 or as
one of multiple layers in the gate electrode 106. Such a metal gate
electrode layer may be a work function metal layer, which may set a
work function of the device 100.
[0028] The gate electrode 106 may have reverse-tapered sidewalls in
some embodiments. "Reverse-tapered" means the sidewalls generally
get further apart toward the top, with each sidewall generally
trending wider. The sidewalls may have an angle 114 with respect to
the top of the substrate 102. In an embodiment, the sidewall of the
gate electrode 114 may have an angle 114 between about eighty-five
degrees and about seventy-five degrees, although the angle 114 may
be different in other embodiments. FIG. 1a illustrates the gate
electrode 106 as having idealized sidewalls, with the angle 114
consistent all the way along the sidewall. In reality, the
sidewalls of the gate electrode may not be so consistent. The angle
114 may be measured by imagining a line through a point at the
bottom of the gate electrode 106 sidewall, adjacent to the gate
dielectric layer 104, and through a point on the sidewall about
two-thirds of the way up the height of the gate electrode 106; the
angle 114 of this line is considered the angle 114 of the sidewall.
As all angles herein are measured from the X-Y plane and none are
greater than ninety degrees, both sidewalls may have an angle 114
that is substantially the same, even though they point in different
directions. However, as the gate electrode 106 is reverse-tapered
rather than tapered, it is clear that the sidewalls generally
extend away from each other and each is angled in substantially
opposite directions away from the Z-axis.
[0029] The gate dielectric layer 104 may have a length 117 and the
gate electrode 104 may have a gate length 116. As illustrated in
FIG. 1a, the length 117 of the gate dielectric layer 104 may be
measured adjacent the gate electrode 106. In some embodiments, the
gate length 116 may be substantially the same as the length 117 of
the gate dielectric 104, although in other embodiments these
lengths 116, 117 may differ.
[0030] In an embodiment, the gate length 116 may be between about
18 nanometers and about 22 nanometers. In another embodiment, the
gate length 116 may be about twenty-five nanometers or less. In
another embodiment, the gate length 116 may be about thirty
nanometers or less. In yet other embodiments, the gate length 116
may be greater than thirty nanometers.
[0031] The gate electrode 106 may also have an intermediate length
115 greater than the gate length 116. The intermediate length 115
may be at a height further from the substrate 102 than the gate
length 116, such as about two-thirds of the way up the gate
electrode 106. As the sidewalls of the gate electrode 106 may be
reverse-tapered, in such embodiments, the intermediate length 115
is greater than the gate length 116. In an embodiment, the
intermediate length 115 may be between about 15% and about 50%
greater than the gate length 116. In an embodiment, the
intermediate length 115 may be between about 5 nanometers and about
15 nanometers greater than the gate length 116.
[0032] There may be spacers 108 on either side of the gate
electrode 106. The spacers 108 may comprise any suitable material,
such as silicon nitride, aluminum nitride, or another material.
[0033] There may be a source region 110 to one side of the gate
electrode 106 and a drain region 112 to the other side of the gate
electrode 106 in some embodiments. The source and drain regions
110, 112 may be doped regions of the substrate 102 in an
embodiment. In another embodiment, the source and drain regions
110, 112 may comprise a source/drain material formed in recesses in
the substrate 102.
[0034] FIGS. 1b and 1c are cross-sectional side views that
illustrate embodiments where the dielectric layer length 117 is
less than the gate length 116 (FIG. 1b) and greater than the gate
length 116 (FIG. 1c).
[0035] FIG. 1b is a cross sectional side view that illustrates an
embodiment with a dielectric layer 104 with an undercut 118. As
illustrated, both sides of the dielectric layer 104 have an
undercut 118, although in other embodiments, only one side may have
an undercut 118, or one side may have an undercut 118 larger than
the other side. In an embodiment, the undercuts 118 of the
dielectric layer 104 may be less than about ten angstroms. In an
embodiment, the undercuts 118 of the dielectric layer 104 may be
less than about three angstroms. In an embodiment, each undercut
118 of the dielectric layer 104 may have a size smaller than about
8% of the gate length 116. In an embodiment, each undercut 118 of
the dielectric layer 104 may have a size smaller than about 4% of
the gate length 116. In an embodiment, each undercut 118 of the
dielectric layer 104 may have a size about 1% of the gate length
116 or smaller. In an embodiment, the combined sizes of undercuts
118 of the dielectric layer 104 may result in the dielectric layer
104 having a length 117 between about 100% the gate length 116 and
about 85% the gate length 116. In an embodiment, the combined sizes
of undercuts 118 of the dielectric layer 104 may result in the
dielectric layer 104 having a length 117 between about 100% the
gate length 116 and about 95% the gate length 116. In an
embodiment, the combined sizes of undercuts 118 of the dielectric
layer 104 may result in the dielectric layer 104 having a length
117 between about 100% the gate length 116 and about 97% the gate
length 116. In an embodiment, the combined sizes of undercuts 118
of the dielectric layer 104 may result in the dielectric layer 104
having a length 117 between about 100% the gate length 116 and
about 98% the gate length 116. Some embodiments may lack undercuts
118 altogether.
[0036] FIG. 1c is a cross sectional side view that illustrates an
embodiment with a dielectric layer 104 with a footing 120. As
illustrated, both sides of the dielectric layer 104 have footings
120, although in other embodiments, only one side may have a
footing 120, or one side may have a footing 120 larger than the
other side. In an embodiment, the footings 120 of the dielectric
layer 104 may be less than about twenty angstroms. In an
embodiment, the footings 120 of the dielectric layer 104 may be
less than about six angstroms. In an embodiment, each footing 120
of the dielectric layer 104 may have a size smaller than about 10%
of the gate length 116. In an embodiment, each footing 120 of the
dielectric layer 104 may have a size smaller than about 5% of the
gate length 116. In an embodiment, each footing 120 of the
dielectric layer 104 may have a size about 2% of the gate length
116 or smaller. In an embodiment, the combined sizes of footings
120 of the dielectric layer 104 may result in the dielectric layer
104 having a length 117 between about 100% the gate length 116 and
about 120% the gate length 116. In an embodiment, the combined
sizes of footings 120 of the dielectric layer 104 may result in the
dielectric layer 104 having a length 117 between about 100% the
gate length 116 and about 110% the gate length 116. In an
embodiment, the combined sizes of footings 120 of the dielectric
layer 104 may result in the dielectric layer 104 having a length
117 between about 100% the gate length 116 and about 105% the gate
length 116. In an embodiment, the combined sizes of footings 120 of
the dielectric layer 104 may result in the dielectric layer 104
having a length 117 between about 100% the gate length 116 and
about 104% the gate length 116. Some embodiments may lack footings
120 altogether.
[0037] FIGS. 1d and 1e are cross-sectional side views that
illustrate two embodiments where the gate electrode 106 comprises
multiple layers.
[0038] There may be a first gate electrode layer 122 on the
dielectric layer 104. The first gate electrode layer 122 may be a
metal gate electrode layer 122, although other suitable materials
may be used as the first gate electrode layer 122 in other
embodiments. The first gate electrode layer 122 may be a work
function metal gate layer 122.
[0039] The metal work function layer 122 may be an n-type metal
gate electrode. Materials that may be used to form n-type metal
gate electrodes include: hafnium, zirconium, titanium, tantalum,
aluminum, their alloys (e.g., metal carbides that include these
elements, i.e., hafnium carbide, zirconium carbide, titanium
carbide, tantalum carbide, and aluminum carbide), and aluminides
(e.g., an aluminide that comprises hafnium, zirconium, titanium,
tantalum, or tungsten).
[0040] The metal work function layer 122 may be a p-type metal gate
electrode. Materials for forming p-type metal gate electrodes
include: ruthenium, palladium, platinum, cobalt, nickel, and
conductive metal oxides, e.g., ruthenium oxide.
[0041] Rather than n- or p-type, the metal work function layer 122
may be a mid-gap metal gate electrode. In such embodiments, the
work function layer 122 may comprise stoichiometric titanium
nitride, tantalum nitride, or another mid-gap material.
[0042] The device 100 may be a transistor, such as an NMOS, PMOS,
or mid-gap transistor. In some embodiments, metal work function
layers 122 for NMOS transistor devices 100 may have a workfunction
that is between about 3.9 eV and about 4.2 eV. In some embodiments,
metal work function layers 122 for PMOS devices 100 may have a
workfunction that is between about 4.9 eV and about 5.2 eV. In some
embodiments, metal work function layers 122 for semiconductor on
insulator (SOI) mid-gap transistor devices 100 may have a
workfunction that is between the workfunctions of NMOS and PMOS
gate electrode materials. Although a few examples of materials for
forming a metal work function layer 122 are identified here, such a
component may be made from many other materials, as will be
apparent to those skilled in the art.
[0043] The work function layer 122 may have a thickness. The
thickness of the work function layer 122 may be chosen to provide a
desired work function and threshold voltage (V.sub.Th) of the gate
of the device 100. In an embodiment, the thickness may between
about 50 angstroms and about 200 angstroms. In an embodiment, the
thickness may between about 50 angstroms and about 100 angstroms.
In other embodiments, the thickness may be greater than about 75
angstroms. In yet other embodiments, the thickness may be
different.
[0044] There may be a second gate electrode layer 124 on the first
gate electrode layer 122. This second gate electrode layer 124 may
comprise another metal or metals, e.g., a metal that may be easily
polished like tungsten, aluminum, titanium, or titanium nitride, or
a metal with a low resistance. The second gate electrode layer 124
may comprise polysilicon, which may be doped, in other embodiments.
The second gate electrode layer 124 may comprise a fill material in
some embodiments, to fill some or all of the rest of the volume of
the gate electrode 106. Such a material may make up the remainder
of the gate electrode 106, or additional layers may be part of the
gate electrode 106 as well, below the first gate electrode layer
122, between the first and second gate electrode layers 122, 124,
or on the second gate electrode layer 124.
[0045] In the embodiment of FIG. 1d, the first gate electrode layer
122 is present only up to a certain height of the gate electrode
106. The second gate electrode layer 124 is on top of the first
gate electrode layer 122 and is adjacent the sidewalls. Such a gate
electrode 106 may be formed by forming blanket layers of electrode
layer 122, 124 material, then removing portions of the blanket
layers, leaving gate electrode layers 122, 124, and forming spacers
adjacent to the gate electrode 106.
[0046] In the embodiment of FIG. 1e, the first gate electrode layer
122 is conformal to the dielectric layer 104 and spacers 108, and
extends up substantially to the top of the gate electrode 106. The
second gate electrode layer 124 is within the first gate electrode
layer 122. However, as used here, the second gate electrode layer
124 is still "on" the first gate electrode layer 122.
[0047] FIGS. 2 through 15 illustrate stages in the formation of the
device 100 of FIG. 1, according to one embodiment.
[0048] FIG. 2 is a cross sectional side view that illustrates a
substrate 102 from which the device 100 may be formed according to
one embodiment. The substrate 102 may comprise any suitable
material from which devices 100 may be formed. In an embodiment,
the substrate 102 may be a bulk single crystal silicon material. In
other embodiments, other semiconductor materials, such as gallium
arsenide, or other materials, may be used for the substrate 102.
The substrate 102 may also be a semiconductor-on-insulator ("SOI")
substrate 102, with a buried insulator layer. In some embodiments,
the substrate 102 may comprise additional layers and/or structures
that are not shown in the Figures.
[0049] FIG. 3 is a cross-sectional side view that illustrates a
blanket dielectric layer 204 formed on the substrate, according to
one embodiment. The blanket dielectric layer 204 may comprise a
high-k material in some embodiments. The blanket dielectric layer
204 may comprise, for example, hafnium oxide, hafnium silicon
oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide,
zirconium silicon oxide, titanium oxide, tantalum oxide, barium
strontium titanium oxide, barium titanium oxide, strontium titanium
oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide,
and lead zinc niobate. In other embodiments, the blanket dielectric
layer 204 (and the dielectric layer 104) may comprise a non-high-k
material, such as silicon dioxide. Although a few examples of
materials that may be used to form a blanket dielectric layer 204
are described here, the blanket dielectric layer 204 may comprise
any suitable material.
[0050] FIG. 4 is a cross-sectional side view that illustrates a
blanket gate electrode layer 206 formed on the blanket dielectric
layer 204, according to one embodiment. The blanket gate electrode
layer 206 may be a sacrificial blanket gate electrode layer 206 in
some embodiments, although in other embodiments it may not be. The
blanket gate electrode layer 206 may comprise more than one layer
in some embodiments, even though only one layer is illustrated in
FIG. 4. For example, the blanket gate electrode layer 206 may
include a first layer that comprises a metal, such as Ti or TaN,
and a second polysilicon layer on the first layer. The first layer
may be about twenty to fifty angstroms thick in some embodiments,
although it may have a different thickness. The first layer may
keep the polysilicon from contacting the dielectric layer 204 in
such embodiments. Other materials may also be used.
[0051] FIG. 5 is a cross-sectional side view that illustrates a
first gate 208 that may be formed by patterning the blanket gate
electrode layer 206. In an embodiment, a hard mask layer 210 may be
formed on the blanket gate electrode layer 206. The hard mask layer
210 may be patterned, and used to pattern the blanket gate
electrode layer 206. The first gate 208 may have reverse-tapered
sidewalls with a sidewall angle 114 and a gate length 116 as
described above with respect to the gate electrode 106. In an
embodiment, the reverse-tapered sidewalls may be formed by using a
dry etch process to remove portions of the blanket gate electrode
layer 206, increasing the bias during the etch to remove more of
the blanket gate electrode layer 206 closer to the substrate 102
than further from the substrate 102. Blanket dielectric layer 204
may be electrically charged, which may promote a slightly faster
etch rate at the lower part of blanket gate electrode layer 206
than occurs at the upper part of blanket gate electrode layer 206.
In other embodiments, other suitable processes may be used. In some
embodiments, the first gate electrode 208 may be sacrificial, and
removed and replaced with gate electrode 106. In other embodiments,
the first gate electrode 208 may remain in place and also be the
gate electrode 106. Other embodiments may be a hybrid between these
two processes, with part of the first gate electrode 208 being
removed and part of the first gate electrode 208 remaining in place
to become part of gate electrode 106.
[0052] FIG. 6 is a cross-sectional side view that illustrates ions
302 being implanted into portions of the blanket dielectric layer
204 to alter those portions of the blanket dielectric layer 204 and
make them more susceptible to removal, according to one embodiment.
The hard mask layer 210 and first gate electrode 208 protect other
portions of the blanket dielectric layer 204 from being altered by
the ion 302 implantation. Any suitable method may be used to
implant ions 302 into portions of the blanket dielectric layer 204.
In an embodiment, the blanket dielectric layer 204 may comprise
HfO.sub.2 with a thickness between about 0.5 nanometers and about 2
nanometers. In an embodiment, the substrate 102 comprises silicon,
and silicon ions 302 are selected for implantation to facilitate a
subsequent annealing and recrystallization of the substrate 102, to
mitigate structural alteration of the substrate 102 resulting from
ion 302 bombardment. The silicon ions may be supplied to an ion
implanter by a silicon source, such as silicon fluoride
(SiF.sub.4). The implantation energy may be between about 200 eV
and about 35 keV and the dosage may be between about
2.times.10.sup.14 cm.sup.-2 and about 5.times.10.sup.15 cm.sup.-2
to implant silicon ions into and through the HfO.sub.2 blanket
dielectric layer 204. In other embodiments, silicon, germanium,
arsenic or other ions may be used. In an embodiment, germanium ions
may be implanted at a dosage of about 2.times.10.sup.15 cm.sup.-2
and an implantation energy of about 2 keV. In an embodiment,
silicon ions may be implanted at a dosage of about
3.times.10.sup.15 cm.sup.-2 and an implantation energy of about 2
keV. Rather than a single ion 302 implantation, a series of
multiple relatively small implantations may be substituted. In
other embodiments, other suitable non-silicon ions 302 may be
implanted, ions 302 of multiple elements may be implanted, and
different implantation energies may be used.
[0053] The ions 302 may be implanted at an angle 304 of ion
implantation similar to the angle of one of the sidewalls of the
gate electrode 208. For example, in FIG. 6, the ions 302 are
implanted at an angle 304 similar to the angle 114 of the
right-hand sidewall of the gate electrode 208 and angle 304 may be
oriented in substantially the same direction as angle 114. In an
embodiment, the angle 304 of ion implantation is within about five
degrees of the sidewall angle 114. In an embodiment, the angle 304
of ion implantation is within about two degrees of the sidewall
angle 114. In an embodiment, the angle 304 of ion implantation is
between about equal to the sidewall angle 114 and about five
degrees less than the sidewall angle 114 (e.g., if there is 85
degrees between the sidewall and the X-Y plane, the angle 304 is
between about 85 degrees and about 80 degrees in such an
embodiment). In an embodiment, the angle 304 of ion implantation is
between about equal to the sidewall angle 114 and about two degrees
less than the sidewall angle 114. In some embodiments, by having
the angle 304 of the ion 302 implantation similar to that of the
side wall angle 114, the portion 306 of the blanket dielectric
layer 204 adjacent where the sidewall of the first gate electrode
208 may be altered by the ions 302. Were the ions 302 implanted
perpendicular to the substrate 102, the larger width toward the top
of the first gate electrode 208 would shadow portion 306 and
prevent it from being altered by the ions 302. Such a scheme may
result in portions of the blanket dielectric layer 204 adjacent the
sidewalls of first gate electrode 208 remaining in place so the
footings 118 of the dielectric layer 104 are large, thereby
reducing the performance of the device 100, or causing other
problems with device 100 operation.
[0054] FIG. 7 is a cross-sectional side view that illustrates
altered regions 212 of the blanket dielectric layer 204 after ion
302 implantation, according to one embodiment. The altered regions
212 may also be referred to as damaged regions 212. The ions 302
may have structurally altered or damaged the portions of the
blanket dielectric layer 204 to result in the altered regions 212.
These altered regions 212 may be amorphized or modified by the ions
302, resulting in structural disruption or alteration of the
blanket dielectric layer 204, such as bond breakage and/or
chemically or physically induced crystal disorganization, which is
associated with decreased resistance to outside chemistry. In other
words, the implantation causes "structural alteration" of exposed
portions of the blanket dielectric layer 204, which makes the
altered portion 212 more susceptible to a selected wet etchant than
unaltered (also referred to as undamaged) regions 214 of the
blanket dielectric layer 204, which may have been protected from
the ions 302 by the first gate electrode 208 and hard mask 210.
[0055] FIG. 8 is a cross-sectional side view that illustrates a
second set of ions 312 being implanted into portions of the blanket
dielectric layer 204 in a second ion implantation process. The
second set of ions 312 may alter some of the blanket dielectric
layer 204 that remained unaltered 214 after the first ion
implantation 302. The ions 312 of the second ion implantation may
be implanted similarly to the first ions 302 of the first ion
implantation.
[0056] The ions 304 may be implanted at an angle 314 of ion
implantation similar to the angle of the other sidewall of the gate
electrode 208. For example, in FIG. 6, the ions 302 are implanted
at an angle 304 similar to the angle 114 of the right-hand sidewall
of the gate electrode 208. In FIG. 8, the ions 312 are therefore
implanted at an angle 314 similar to the angle 114 of the left-hand
sidewall, and angle 314 is oriented in substantially the same
direction as angle 114 of the left-hand sidewall. In other words,
if both sidewalls of the gate electrode 208 are at an angle of
eighty five degrees from the plane of the top surface of the
substrate 102, ions 302, 312 of both ion implantations may be
implanted at angles 304, 314 similar to eighty five degrees; if
both implantations are at eighty-five degrees, there is a ten
degree difference between the two implantation angles 304, 314. In
an embodiment, the angle 314 of ion implantation is within about
five degrees of the left sidewall angle 114. In an embodiment, the
angle 314 of ion implantation is within about two degrees of the
sidewall angle 114. In an embodiment, the angle 314 of ion
implantation is between about equal to the sidewall angle 114 and
about five degrees less than the sidewall angle 114 (e.g., if there
is 85 degrees between the sidewall and the X-Y plane, the angle 314
is between about 85 degrees and about 80 degrees in such an
embodiment). In an embodiment, the angle 314 of ion implantation is
between about equal to the sidewall angle 114 and about two degrees
less than the sidewall angle 114. This second ion 312 implantation
may occur after the first ion 302 implantation, or may occur
substantially simultaneously.
[0057] FIG. 9 is a cross-sectional side view that illustrates
altered regions 212 of the blanket dielectric layer 204 after the
second ion 312 implantation, according to one embodiment. As seen
in FIG. 9, much or all of the exposed portion of the blanket
dielectric layer 204 (the portion not covered by the gate electrode
208) has been converted to an altered region 212. The second ion
312 implantation has altered much or all of the blanket dielectric
layer 204 that had been shadowed by the gate electrode 208 during
the first ion 302 implantation. Thus, after the second ion 312
implantation, much or all of the exposed portion of the blanket
dielectric layer 204 has been altered or damaged by ion
implantation, making the damaged region 212 more susceptible to a
selected wet etchant.
[0058] FIG. 10 is a cross-sectional side view that illustrates the
formation of the gate dielectric layer 104 by removal of the
damaged region 212 of the blanket dielectric layer 204, according
to one embodiment. Because the angled ion implantations may provide
a highly anisotropic alteration of the blanket dielectric layer
204, and the etchant may be highly selective to the altered
portions 212 of the blanket dielectric layer 204, the gate
dielectric layer 104 may be formed that has little or no footings
120 or undercuts 118, as described above with respect to FIGS. 1b
and 1c, which may result in a device 100 that performs better than
it would with a gate dielectric layer 104 with large footings 120
or undercuts 118. Suitable etchants that may be used to remove the
altered regions 212 of the blanket dielectric layer 204 include but
are not limited to phosphoric acid (H.sub.3PO.sub.4), hydrofluoric
acid (HF), buffered HF, hydrochloric acid (HCl), sulfuric acid
(H.sub.2SO.sub.4), nitric acid (HNO.sub.3), acetic acid
(CH.sub.3COOH), sodium hydroxide (NaOH), potassium hydroxide (KOH),
ammonium hydroxide (NH.sub.4OH), alcohols, potassium permanganate
(KMnO.sub.4), ammonium fluoride (NH.sub.4F), tetramethyl ammonium
hydroxide (TMAH), and others. In an embodiment, a buffered
hydrofluoric acid with a pH of about 4 may be used.
[0059] FIG. 11 is a cross-sectional side view that illustrates
spacers 108 formed adjacent the sidewalls of the gate electrode 208
and source and drain regions 110, 112 formed in the substrate,
according to an embodiment. The source and drain regions 110, 112
may be formed by doping regions of the substrate 102 in an
embodiment. In another embodiment, the source and drain regions
110, 112 may be formed be removing portions of the substrate 102 to
form recesses 130, 132, then filling the recesses 130, 132 with a
source/drain material. Such a material may extend beyond the top
surface of the substrate 102, and may be doped during formation or
after formation. Other suitable methods to make source and drain
regions 110, 112 may also be used. Any suitable method may be used
to make the spacers 108.
[0060] FIG. 12 is a cross-sectional side view that illustrates a
first interlayer dielectric layer (ILD layer) 140, according to an
embodiment. Note that the first ILD layer 140 may be present in the
device 100 shown in FIG. 1a; it was left out of the Figure for
simplicity. Any suitable material may be used as the ILD layer 140.
Excess material of the ILD layer 140 may have been placed on the
substrate 102 and gate electrode 208. The excess material above the
top surface of the gate electrode 208 may be removed to expose the
top surface of the first gate electrode 208, as is illustrated in
FIG. 12.
[0061] FIG. 13 is a cross-sectional side view that illustrates a
trench 220 formed by removal of the first gate electrode 208,
according to one embodiment. The first gate electrode 208 may be
removed by any suitable method. Note that while FIG. 13 shows the
first gate electrode 208 completely removed, in some embodiments, a
portion of the first gate electrode 208 may remain in place. For
example, if the first gate electrode 208 comprises a polysilicon
layer and an intermediate layer between the polysilicon layer and
the gate dielectric 104, the intermediate layer may be left behind
in some embodiments. Further, FIGS. 13 through 15 only illustrate
embodiments where all or part of the first gate electrode 208 is
removed and replaced with a replacement gate electrode comprising
one or more gate electrode layers, which may also be referred to as
"replacement gate electrode layers." In other embodiments, the
first gate electrode 208 may be left in place and used as the gate
electrode 106 of the device 100 after fabrication.
[0062] FIG. 14 is a cross-sectional side view that illustrates a
first metal gate electrode layer 122 formed in the trench 220,
according to one embodiment. As illustrated in FIG. 14, the first
metal gate layer 122 is conformal to the trench bottom and
sidewalls, similar to the embodiment discussed with respect to FIG.
1e. Any suitable method may be used to form the first metal gate
layer 122. The first gate electrode layer 122 may comprise other
suitable materials besides metal.
[0063] FIG. 15 is a cross-sectional side view that illustrates the
second gate electrode layer 124 formed on the first metal gate
layer 122, according to one embodiment. In an embodiment, the
second gate electrode layer 124 may fill remaining portions of the
trench 220 not filled by the first gate electrode layer 122 and
other layers, to result in the gate electrode 106. The second gate
electrode layer 124 may comprise a metal, polysilicon, or another
material.
[0064] Additional gate electrode layers beyond the first and second
gate electrode layers 122, 124 may also be formed in the trench 220
and form part of the final gate electrode 106. Alternatively, only
one layer may be formed in the trench 220, and that one layer may
make up the gate electrode 106.
[0065] While FIGS. 14 and 15 illustrate the first gate electrode
layer 122 being conformal to the trench 220 and the second gate
electrode layer 124 being on the first gate electrode layer 122,
the first gate electrode layer 122 may be formed within the trench
220 in a less or non-conformal manner and the second gate electrode
layer 124 formed on the first gate electrode layer 122 and adjacent
the trench 220 sidewalls, to result in the gate electrode 106
illustrated in FIG. 1d.
[0066] As the trench 220 is wider towards the top than at the
bottom because of the reverse-tapered shape of gate electrode 208,
it is easier to form the layer or layers that form the gate
electrode 106 than if the trench had straight walls or was tapered.
Such a reverse-tapered shape helps avoid the formation of voids,
such as when a material being deposited bridges the gap at the top
of the trench 220 prior to lower volumes of the trench 220 being
filled.
[0067] Additional process steps may be performed to complete the
device 100, as will be appreciated by those of skill in the
art.
[0068] FIG. 16 is a block diagram that illustrates a system 1600 in
accordance with one embodiment of the present invention. One or
more devices 100 with reverse-tapered gate electrodes 106 and
dielectric layers 104 with little to no footings 120 or undercuts
118 as described above may be included in the system 1600 of FIG.
16. As illustrated, for the embodiment, system 1600 includes a
computing device 1602 for processing data. Computing device 1602
may include a motherboard 1604. Coupled to or part of the
motherboard 1604 may be in particular a processor 1606, and a
networking interface 1608 coupled to a bus 1610. A chipset may form
part or all of the bus 1610. The processor 1606, chipset, and/or
other parts of the system 1606 may include one or more devices 100
as described above.
[0069] Depending on the applications, system 1600 may include other
components, including but are not limited to volatile and
non-volatile memory 1612, a graphics processor (integrated with the
motherboard 1604 or connected to the motherboard as a separate
removable component such as an AGP or PCI-E graphics processor), a
digital signal processor, a crypto processor, mass storage 1614
(such as hard disk, compact disk (CD), digital versatile disk (DVD)
and so forth), input and/or output devices 1616, and so forth.
[0070] In various embodiments, system 1600 may be a personal
digital assistant (PDA), a mobile phone, a tablet computing device,
a laptop computing device, a desktop computing device, a set-top
box, an entertainment control unit, a digital camera, a digital
video recorder, a CD player, a DVD player, or other digital device
of the like.
[0071] Any of one or more of the components 1606, 1614, etc. in
FIG. 16 may include one or more device 100 as described herein. For
example, a transistor 100 may be part of the CPU 1606, motherboard
1604, graphics processor, digital signal processor, or other
devices.
[0072] The foregoing description of the embodiments of the
invention has been presented for the purposes of illustration and
description. It is not intended to be exhaustive or to limit the
invention to the precise forms disclosed. This description and the
claims following include terms, such as left, right, top, bottom,
over, under, upper, lower, first, second, etc. that are used for
descriptive purposes only and are not to be construed as limiting.
For example, terms designating relative vertical position refer to
a situation where a device side (or active surface) of a substrate
or integrated circuit is the "top" surface of that substrate; the
substrate may actually be in any orientation so that a "top" side
of a substrate may be lower than the "bottom" side in a standard
terrestrial frame of reference and still fall within the meaning of
the term "top." The term "on" as used herein (including in the
claims) does not indicate that a first layer "on" a second layer is
directly on and in immediate contact with the second layer unless
such is specifically stated; there may be a third layer or other
structure between the first layer and the second layer on the first
layer. The embodiments of a device or article described herein can
be manufactured, used, or shipped in a number of positions and
orientations. Persons skilled in the relevant art can appreciate
that many modifications and variations are possible in light of the
above teaching. Persons skilled in the art will recognize various
equivalent combinations and substitutions for various components
shown in the Figures. It is therefore intended that the scope of
the invention be limited not by this detailed description, but
rather by the claims appended hereto.
* * * * *