U.S. patent application number 12/176624 was filed with the patent office on 2008-11-13 for strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Thomas N. Adam, Stephen W. Bedell, Joel P. de Souza, Keith E. Fogel, Alexander Reznicek, Devendra K. Sadana, Ghavam Shahidi.
Application Number | 20080277690 12/176624 |
Document ID | / |
Family ID | 34969794 |
Filed Date | 2008-11-13 |
United States Patent
Application |
20080277690 |
Kind Code |
A1 |
Adam; Thomas N. ; et
al. |
November 13, 2008 |
STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON
GERMANIUM LAYER
Abstract
A cost efficient and manufacturable method of fabricating
strained semiconductor-on-insulator (SSOI) substrates is provided
that avoids wafer bonding. The method includes growing various
epitaxial semiconductor layers on a substrate, wherein at least one
of the semiconductor layers is a doped and relaxed semiconductor
layer underneath a strained semiconductor layer; converting the
doped and relaxed semiconductor layer into a porous semiconductor
via an electrolytic anodization process, and oxidizing to convert
the porous semiconductor layer into a buried oxide layer. The
method provides a SSOI substrate that includes a relaxed
semiconductor layer on a substrate; a high-quality buried oxide
layer on the relaxed semiconductor layer; and a strained
semiconductor layer on the high-quality buried oxide layer. In
accordance with the present invention, the relaxed semiconductor
layer and the strained semiconductor layer have identical
crystallographic orientations.
Inventors: |
Adam; Thomas N.;
(Poughkeepsie, NY) ; Bedell; Stephen W.;
(Wappingers Falls, NY) ; de Souza; Joel P.;
(Putnam Valley, NY) ; Fogel; Keith E.; (Mohegan
Lake, NY) ; Reznicek; Alexander; (Mount Kisco,
NY) ; Sadana; Devendra K.; (Pleasantville, NY)
; Shahidi; Ghavam; (Pound Ridge, NY) |
Correspondence
Address: |
SCULLY, SCOTT, MURPHY & PRESSER, P.C.
400 GARDEN CITY PLAZA, SUITE 300
GARDEN CITY
NY
11530
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
Armonk
NY
|
Family ID: |
34969794 |
Appl. No.: |
12/176624 |
Filed: |
July 21, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11620663 |
Jan 6, 2007 |
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12176624 |
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10883887 |
Jul 2, 2004 |
7172930 |
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11620663 |
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Current U.S.
Class: |
257/190 ;
257/E21.57; 257/E27.112 |
Current CPC
Class: |
H01L 21/76259 20130101;
Y10S 438/967 20130101 |
Class at
Publication: |
257/190 ;
257/E27.112 |
International
Class: |
H01L 27/12 20060101
H01L027/12 |
Claims
1. A semiconductor structure comprising: a substrate; a relaxed
semiconductor layer on the substrate; a high-quality buried oxide
layer on the relaxed semiconductor layer; and a strained
semiconductor layer on the high-quality buried oxide layers wherein
the relaxed semiconductor layer and the strained semiconductor
layer have identical crystallographic orientations.
2. The semiconductor structure of claim 1 wherein said substrate is
a crystalline semiconductor substrate.
3. The semiconductor structure of claim 2 wherein said crystalline
semiconductor substrate is doped.
4. The semiconductor structure of claim 2 wherein said crystalline
semiconductor substrate is a Si-containing substrate.
5. The semiconductor structure of claim 1 wherein said relaxed
semiconductor layer comprises a SiGe alloy layer having up to 99
atomic percent Ge.
6. The semiconductor structure of claim 1 wherein said relaxed
semiconductor layer has a measured degree of relaxation of about
10% or greater.
7. The semiconductor structure of claim 1 wherein said relaxed
semiconductor layer has a surface region that is metastable and has
a defect density of about 1E5 defects/cm.sup.3 or greater.
8. The semiconductor structure of claim 1 wherein said relaxed
semiconductor layer is a graded SiGe layer having a varying content
of Ge.
9. The semiconductor structure of claim 1 wherein said relaxed
semiconductor layer is doped.
10. The semiconductor structure of claim 1 wherein said strained
semiconductor layer is under a compressive or tensile strain.
11. The semiconductor structure of claim 1 wherein said strained
semiconductor layer comprises a Si-containing semiconductor.
12. The semiconductor structure of claim 11 wherein said
Si-containing semiconductor comprises Si or SiGe.
13. The semiconductor structure of claim 1 wherein said strained
semiconductor is a doped layer having a dopant concentration of
about 1E15 atoms/cm.sup.3 or greater.
14. The semiconductor structure of claim 1 wherein said relaxed
semiconductor layer and said strained semiconductor layer have a
(100), (110) or (111) crystal orientation.
15. The semiconductor structure of claim 1 wherein said
high-quality buried oxide layer has a leakage current of about 1
microAmp or less.
16. The semiconductor structure of claim 1 wherein said
high-quality buried oxide layer has a breakdown field of about 2
Megavolts or greater.
17. The semiconductor structure of claim 1 wherein said strained
semiconductor layer is patterned.
18. The semiconductor structure of claim 17 wherein said
high-quality buried oxide layer is patterned.
19. The semiconductor structure of claim 1 further comprising at
least one complementary metal oxide semiconductor device located on
a surface of said strained semiconductor layer.
Description
RELATED APPLICATION
[0001] This application is a continuation of U.S. application Ser.
No. 11/620,663, filed on Jan. 6, 2007, which is a divisional of
U.S. application Ser. No. 10/883,887 filed Jul. 2, 2004, now U.S.
Pat. No. 7,172,930, issued on Feb. 6, 2007.
FIELD OF THE INVENTION
[0002] The present invention relates to a semiconductor substrate
material and to a method of fabricating the same. More
specifically, the present invention relates to a strained
semiconductor, e.g., Si-on-insulator (SSOI) substrate material and
a robust method of fabricating the same that avoids wafer
bonding.
BACKGROUND OF THE INVENTION
[0003] In the semiconductor industry, there has been an increasing
interest in enhancing performance of complementary metal oxide
semiconductor (CMOS) devices by replacing conventional
silicon-on-insulator (SOI) substrates with strained
semiconductor-on-insulator (SSOI) substrates. The reason behind
this interest is that SSOI substrates provide higher carrier
(electrons/holes) mobility than a conventional SOI substrate. The
strain in the SSOI substrates can either be compressive or
tensile.
[0004] Conventional methods to fabricate SSOI substrates typically
require a layer transfer process wherein a strained Si-containing
layer located on a relaxed SiGe layer is transferred onto a handle
wafer. In particular, the conventional process includes first
creating a relaxed SiGe layer of a few microns in thickness on a
surface of a Si-containing substrate. The relaxed SiGe layer
typically has an in-plane lattice parameter that is larger than
that of Si. Next, a Si-containing layer is grown on the relaxed
SiGe layer. Because the SiGe layer has a larger in-plane lattice
parameter as compared to Si, the Si-containing layer is under
strain.
[0005] The structure, including the strained Si-containing layer
located on a relaxed SiGe layer, is then bonded to a handle wafer,
which includes an insulating layer, such as an oxide layer. The
bonding occurs between the strained Si-containing layer and the
insulator layer. The Si-containing substrate and the relaxed SiGe
layer are then typically removed from the bonded structure to
provide a strained Si-on-insulator substrate.
[0006] The conventional SSOI substrate preparation method described
above is quite expensive and low-yielding because it combines two
rather advanced substrate technologies, i.e., high-quality, thick
SiGe/strain Si growth, and wafer bonding. Moreover, the
conventional preparation method is unattractive for manufacturing a
large volume of substrates.
[0007] In view of the above, a cost effective and manufacturable
solution to fabricate SSOI substrates is required for future
high-performance Si-containing CMOS products.
SUMMARY OF THE INVENTION
[0008] The present invention provides a cost-effective and
manufacturable solution to produce SSOI substrates that avoids
wafer bonding which is typically required in conventional
technologies to produce SSOI substrate materials. In particular,
the method of the present invention, which fabricates SSOI
substrates, includes creating a buried porous layer underneath a
strained semiconductor layer. The porous layer is then converted
into a buried oxide layer by employing a high temperature
oxidation/anneal step such that only a part of the strained
semiconductor layer is consumed during processing.
[0009] The method provides a SSOI substrate that includes a
strained semiconductor layer atop an oxide layer, the oxide layer
is located on a relaxed semiconductor template. Unlike the
conventional process described above, the strained semiconductor
layer and the relaxed semiconductor layer have a commensurate,
i.e., identical, crystal orientation. Moreover, the oxide layer
that is formed by the inventive method is of `high-quality` meaning
that the oxide layer has a leakage of about 1 microAmp or less and
a breakdown field of about 2 Megavolts/cm or greater.
[0010] In broad terms, the method of the present invention
comprises the steps of:
providing a structure that comprises a substrate, a relaxed
semiconductor layer on the substrate, a doped and relaxed
semiconductor layer on the relaxed semiconductor layer, and a
strained semiconductor layer on the doped and relaxed semiconductor
layer, said relaxed semiconductor layer, said doped and relaxed
semiconductor layer and said strained semiconductor layer have
identical crystallographic orientations; converting the doped and
relaxed semiconductor layer underneath the strained semiconductor
layer into a buried porous layer; and annealing the structure
including the buried porous layer to provide a strained
semiconductor-on-insulator substrate, wherein during said annealing
the buried porous layer is converted into a buried oxide layer.
[0011] In addition to the method described above the present
invention also relates to the SSOI substrate that is formed.
Specifically, the SSOI substrate of the instant invention
comprises:
a substrate; a relaxed semiconductor layer on the substrate; a
high-quality buried oxide layer on the relaxed semiconductor layer;
and a strained semiconductor layer on the high-quality buried oxide
layer, wherein the relaxed semiconductor layer and the strained
semiconductor layer have identical crystallographic
orientations.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIGS. 1A-1D are pictorial representations (through cross
sectional views) illustrating the basic processing steps employed
in fabricating the inventive SSOI substrate. The inventive SSOI
substrate shown in FIG. 1D contains a strained semiconductor layer
and a buried oxide that are both unpatterned.
[0013] FIGS. 2A-2B are pictorial representations (through
cross-sectional views) illustrating patterned SSOI substrates that
are fabricated using the method of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0014] The present invention, which provides a method of
fabricating a SSOI substrate and the SSOI substrate produced by the
method, will now be described in greater detail by referring to the
drawings that accompany the present application. The drawings are
provided for illustrative purposes only and are thus not drawn to
scale. In the drawings, like and corresponding elements are
referred to by like reference numerals.
[0015] The method of the present invention begins with first
providing the structure 10 shown, for example, in FIG. 1A.
Structure 10 includes a substrate 12, a relaxed semiconductor,
e.g., SiGe alloy, layer 14 located on a surface of substrate 12, a
doped and relaxed semiconductor layer 16 located on the relaxed
semiconductor layer 14, and a strained semiconductor layer 18
located on a surface of the doped and relaxed semiconductor layer
16. In accordance with the present invention, layers 14, 16 and 18
have the same crystallographic orientation since those layers are
each formed by epitaxial growth.
[0016] Examples of various epitaxial growth processes that can be
employed in the present invention in fabricating layers 14, 16 and
18 on substrate 12 include, for example, rapid thermal chemical
vapor deposition (RTCVD), low-energy plasma deposition (LEPD),
ultra-high vacuum chemical vapor deposition (UHVCVD)), atmospheric
pressure chemical vapor deposition (APCVD) and molecular beam
epitaxy (MBE).
[0017] The substrate 12 employed in the present invention may be
comprised of any material or material layers including, for
example, crystalline glass or metal, but preferably the substrate
12 is a crystalline semiconductor substrate. Examples of
semiconductor substrates that can be employed as substrate 12
include, but are not limited to: Si, SiGe, SiC, SiGeC, GaAs, InAs,
InP, and other III/IV or II/VI compound semiconductors. The term
"semiconductor substrate" also includes preformed
silicon-on-insulator (SOI) or SiGe-on-insulator (SGOI) substrates
which may include any number of buried insulating (continuous,
non-continuous or a combination of continuous and non-continuous)
regions therein. In one preferred embodiment, the substrate 12 is a
Si-containing substrate. The substrate 12 may be undoped or it may
be an electron rich or hole-rich substrate, i.e., doped
substrates.
[0018] The relaxed semiconductor layer 14 is then epitaxially grown
on a surface of the substrate 12 using one of the above mentioned
processes. In the following description the relaxed semiconductor
layer 14 is referred to a relaxed SiGe layer 14 since that
semiconductor material represents a preferred material for layer
14. The term "SiGe alloy layer" denotes a SiGe layer that comprises
up to 99 atomic percent Ge. More typically, the SiGe alloy layer
comprises from about 1 to about 99 atomic percent Ge, with a Ge
atomic percent from about 10 to about 50 atomic percent being more
highly preferred.
[0019] The relaxed SiGe alloy layer 14 may be a single layer having
a continuous distribution of Ge, or it may be a graded layer having
a varying content of Ge included within different regions of the
layer. As stated above, layer 14 is a relaxed layer having a
measured degree of relaxation from about 10% or greater. Typically,
the surface region of the relaxed semiconductor layer 14 is
metastable having a defect (stacking faults, pile-up and threading)
density that is typically about 1E5 defects/cm.sup.3 or
greater.
[0020] The relaxed semiconductor layer 14 may be doped or undoped.
The type of dopant and concentration of dopant within the layer 14
is arbitrary and can be predetermined by a skilled artisan. When
doped, relaxed layer 14 typically has a dopant concentration that
is greater than 1E17 atoms/cm.sup.3. Doped layer 14 is formed by
providing a dopant source with the Si source, or the Ge source, or
both sources used during the epitaxial growth process.
[0021] The thickness of the relaxed semiconductor layer 14 may vary
so long as a relaxed layer can be formed. The thickness of the
relaxed semiconductor layer 14 is dependent on the Ge content of
the layer. Typically, and for a relaxed semiconductor layer 14
having a Ge content of less than about 50 atomic %, layer 14 has a
thickness from about 1 to about 5000 nm, with a thickness from
about 1000 to about 3000 nm being more typical.
[0022] Although relaxed SiGe alloy templates are preferred, the
present invention also contemplates the use of other semiconductor
materials that can be formed in relaxed state.
[0023] Next, a doped and relaxed semiconductor layer 16 is formed
on the relaxed semiconductor layer 14. The doped and relaxed
semiconductor layer 16 may include p- or n-type dopants, with
p-type dopants being highly preferred. P-type dopants include Ga,
Al, B and BF.sub.2. The doped and relaxed semiconductor layer 16
may be a separate layer, as shown in FIG. 1A, or it can be an upper
portion of the previously formed relaxed semiconductor layer 14.
The term "semiconductor" when used in content with layer 16 denotes
any semiconductor material including, for example, Si, SiGe, SiC,
and SiGeC. Preferably, the doped and relaxed semiconductor layer 16
is a Si-containing semiconductor, with Si and SiGe being most
preferred.
[0024] In accordance with the present invention, the doped and
relaxed semiconductor layer 16 is a layer that is more heavily
doped than the surrounding layers, i.e., layers 14 and 18.
Typically, the doped and relaxed semiconductor layer 16 contains a
p-type dopant concentration of about 1E19 atoms/cm.sup.3or greater,
with a p-type dopant concentration from about 1E20 to about 5E20
atoms/cm.sup.3 being more typical. The doped and relaxed
semiconductor layer 16 is formed using one of the above mentioned
epitaxial growth processes in which the dopant source is included
with the semiconductor source. The doped and relaxed semiconductor
material 16 may have an in-plane lattice parameter that is either
larger or smaller than that of virgin Si.
[0025] The doped and relaxed semiconductor layer 16 is a thin layer
whose thickness will define the thickness of the buried oxide layer
to be subsequently formed. Typically, the doped and relaxed
semiconductor layer 16 has a thickness from about 1 to about 1000
nm, with a thickness from about 10 to about 200 nm being more
typical.
[0026] After forming the doped and relaxed semiconductor layer 16,
a strained semiconductor layer 18 is formed on top of the doped and
relaxed semiconductor layer 16 using one of the above-mentioned
epitaxial growth processes. The strained semiconductor layer 18 may
be comprised of one of the semiconductor materials mentioned above
in connection with layer 16. The strained semiconductor layer 18
and the doped and relaxed semiconductor 16 can thus be comprised of
the same or different semiconductor material. The strained
semiconductor 18 can have a tensile or compressive stress.
[0027] It is noted that the growth of layers 14, 16 and 18 may
occur using the same or different epitaxial growth process.
Moreover, it is also contemplated to form layers 14, 16 and 18 in
the same reactor chamber without breaking vacuum.
[0028] The strained semiconductor layer 18 may be doped or undoped.
When doped, the strained semiconductor layer 18 typically has a
dopant concentration of about 1E15 atoms/cm.sup.3 or greater. The
thickness of layer 18 is typically from about 5 to about 2000 nm,
with a thickness from about 10 to about 500 nm being more
typical.
[0029] In one embodiment of the present invention, the strained
semiconductor layer 18 and the doped and relaxed semiconductor
layer 16 are comprised of the same or different Si-containing
semiconductor, with Si or SiGe being highly preferred.
[0030] In a highly preferred embodiment of the present invention,
the strained semiconductor layer 18 and the relaxed semiconductor
layer 14 are both doped layers having a dopant concentration of
about 1E15 atoms/cm.sup.3 or greater, while the doped and relaxed
semiconductor layer 16 is a p-doped layer having a dopant
concentration of about 1E20 atoms/cm.sup.3 or greater.
[0031] In accordance with the present invention, layers 14, 16 and
18 have the same crystallographic orientation as substrate 12 since
the various layers are formed by epitaxial growth. Hence, layers
14, 16 and 18 can have a (100), (110), (111) or any other
crystallographic orientation.
[0032] Next, the structure shown in FIG. 1A is subjected to an
electrolytic anodization process that is capable of converting the
doped and relaxed semiconductor layer 16 into a porous region. The
structure, after the electrolytic anodization process has been
performed, is shown, for example in FIG. 1B. In the drawing,
reference numeral 20 denotes the porous region or layer.
[0033] The anodization process is performed by immersing the
structure shown in FIG. 1A into an HF-containing solution while an
electrical bias is applied to the structure with respect to an
electrode also placed in the HF-containing solution. In such a
process, the structure typically serves as the positive electrode
of the electrochemical cell, while another semiconducting material
such as Si, or a metal is employed as the negative electrode.
[0034] In general, the HF anodization converts the doped and
relaxed semiconductor layer 16 into a porous semiconductor layer
20. The rate of formation and the nature of the porous
semiconductor layer 20 so-formed (porosity and microstructure) is
determined by both the material properties, i.e., doping type and
concentration, as well as the reaction conditions of the
anodization process itself (current density, bias, illumination and
additives in the HF-containing solution). Generally, the porous
semiconductor layer 20 formed in the present invention has a
porosity of about 0.1% or higher.
[0035] The term "HF-containing solution" includes concentrated HF
(49%), a mixture of HF and water, a mixture of HF and a monohydric
alcohol such as methanol, ethanol, propanol, etc, or HF mixed with
at least one surfactant. The amount of surfactant that is present
in the HF solution is typically from about 1 to about 50%, based on
49% HF.
[0036] The anodization process, which converts the doped and
relaxed semiconductor layer 16 into a porous semiconductor layer
20, is performed using a constant current source that operates at a
current density from about 0.05 to about 50 milliAmps/cm.sup.2. A
light source may be optionally used to illuminate the sample. More
preferably, the anodization process of the present invention is
employed using a constant current source operating at a current
density from about 0.1 to about 5 milliAmps/cm.sup.2.
[0037] The anodization process is typically performed at room
temperature or, a temperature that is elevated from room
temperature may be used. Following the anodization process, the
structure is typically rinsed with deionized water and dried.
Anozidation typically occurs for a time period of less than about
10 minutes, with a time period of less than 1 minute being more
typical.
[0038] The structure shown in FIG. 1B including the porous
semiconductor layer 20 is then heated, i.e., annealed, at a
temperature which converts the porous semiconductor layer 20 into a
buried oxide region 22. The resultant structure is shown, for
example, in FIG. 1C. As shown, the structure includes a strained
semiconductor layer 18 atop a buried oxide layer 22. The buried
oxide layer 22 is located atop the relaxed semiconductor layer 14,
which is, in turn, atop of the substrate 12.
[0039] Note that an oxide layer 24 is formed atop layer 18 during
the heating step. This surface oxide layer, i.e., oxide layer 24,
is typically, but not always, removed from the structure after the
heating step using a conventional wet etch process wherein a
chemical etchant such as HF that has a high selectivity for
removing oxide as compared to semiconductor is employed. The
structure, without the surface oxide layer 24, is shown in FIG.
1D.
[0040] Note that when the oxide layer 24 is removed, the above
processing steps can be repeated any number of times to provide a
multilayered structure containing, from bottom to top,
substrate/(relaxed semiconductor/buried oxide/strained
semiconductor), wherein x is greater than 1. When x is 1, the
structure shown in FIG. 1D is formed.
[0041] In some embodiments of the present invention, multiple
buried oxide layers can be obtained by forming continuous layers of
materials 14, 16 and 18 on substrate 12 and then performing the
electrolytic anodization process and annealing process of the
present invention.
[0042] The surface oxide layer 24 formed after the heating step of
the present invention has a variable thickness which may range from
about 10 to about 1000 nm, with a thickness of from about 20 to
about 500 nm being more highly preferred. Buried oxide layer 22
typically has the same thickness as previously described for the
doped and relaxed semiconductor layer 16.
[0043] Specifically, the heating step of the present invention is
an annealing step which is performed at a temperature that is
greater than 400.degree. C., preferably greater than 1100.degree.
C. A typical temperature range for the heating step of the present
invention is from about 1200.degree. to about 1320.degree. C.
[0044] Moreover, the heating step of the present invention is
carried out in an oxidizing ambient which includes at least one
oxygen-containing gas such as O.sub.2, NO, N.sub.2O, ozone, air and
other like oxygen-containing gases. The oxygen-containing gas may
be admixed with each other (such as an admixture of O.sub.2 and
NO), or the gas may be diluted with an inert gas such as He, Ar,
N.sub.2, Xe, Kr, or Ne. When a diluted ambient is employed, the
diluted ambient contains from about 0.1 to about 100% of
oxygen-containing gas, the remainder, up to 100%, being inert
gas.
[0045] The heating step may be carried out for a variable period of
time that typically ranges from greater than 0 minutes to about
1800 minutes, with a time period from about 60 to about 600 minutes
being more highly preferred. The heating step may be carried out at
a single targeted temperature, or various ramp and soak cycles
using various ramp rates and soak times can be employed.
[0046] The heating step is performed under an oxidizing ambient to
achieve the presence of oxide layers, i.e., layers 22 and 24. Note
that the porous semiconductor region reacts with diffused oxygen at
an enhanced rate.
[0047] After heating, and subsequent removal of surface oxide layer
24, the structure can be subjected to a thermal process (i.e.,
baking step) that is capable of reducing the content of dopants
present in the final structure. The baking step is typically
performed in the presence of a hydrogen-containing ambient such as
H.sub.2. Leaching of dopants from the structure typically occurs
when this step is performed at a temperature that is greater than
800.degree. C., with a temperature of greater than 1000.degree. C.
being more typical. This thermal step is optional and does not need
to be performed in all instances. Leaching of dopants using the
thermal treatment process can be performed for any desired period
of time.
[0048] Typically, the thermal process, which leaches dopants from
the structure, is performed for a time period from about 1 to about
60 minutes. As stated above, this baking step reduces the amount of
dopant within the SSOI substrate. Although it can be used to reduce
any dopant within the SSOI substrate, it is particularly employed
to remove boron from the structure.
[0049] After performing the above processing steps, conventional
CMOS process can be carried out to form one or more CMOS devices
such as field effect transistors (FETs) atop the strained
semiconductor layer. The CMOS processing is well known to those
skilled in the art; therefore details concerning that processing
are not needed herein.
[0050] The method of the present invention described above provides
a SSOI substrate including a strained semiconductor layer 18 atop
an oxide layer 22, the oxide layer 22 is located atop a relaxed
semiconductor layer 14 which is located on a substrate 12. Unlike
the conventional process described above, the strained
semiconductor layer 18 and the relaxed semiconductor layer 14 have
a commensurate, i.e., identical, crystal orientation. Moreover, the
oxide layer 22 that is formed by the inventive method is of
`high-quality` meaning that the buried oxide layer 22 has a leakage
of about 1 microAmp or less and a breakdown field of about 2
Megavolts or greater.
[0051] The embodiment depicted in FIGS. 1A-1D illustrates the case
wherein no layers are patterned. In another embodiment, it is also
contemplated to form a structure that includes a patterned strained
semiconductor layer 18 on a buried oxide layer 22. One such
patterned SSOI structure is shown, for example, in FIG. 2A. The
patterned structure is formed using the same basic processing steps
as described above except that prior to anodization the strained
semiconductor layer 18, shown, for example, in FIG. 1A, is
patterned by lithography and etching. The lithography step includes
applying a photoresist on the strained semiconductor layer 18,
exposing the photoresist to a pattern of radiation and developing
the patterned into the exposed photoresist by utilizing a
conventional resist developer. The etching step can include a wet
etch process or a dry etching process that selectively removes the
exposed strained semiconductor layer 18. After stripping the
patterned photoresist from the structure, anodization and
oxidation, as described above are performed. In some embodiments,
the oxide layer 22 not underneath the strained semiconductor layer
can be removed exposing the relaxed semiconductor layer 14.
[0052] In yet another embodiment of the present invention, a
patterned SSOI substrate, such as illustrated in FIG. 2B, can be
formed. This patterned SSOI substrate is formed by first conducting
the processing steps of epitaxial growth, anodization and
oxidation, and then patterning the structure by lithography and
etching. The etching step may be stopped atop a surface of oxide
layer 22 providing the structure shown in FIG. 2A, or it can be
stopped when a surface of the relaxed semiconductor layer 14 is
reached, See FIG. 2B. The etch used in removing the exposed
portions of both layer 18 and 22 can include a single etch step, or
multiple etching steps may be employed.
[0053] CMOS processing can also be performed on the patterned SSOI
substrates as well.
[0054] While the present invention has been particularly shown and
described with respect to preferred embodiments thereof, it will be
understood by those skilled in the art that the foregoing and other
changes in forms and details may be made without departing from the
scope and the spirit of the present invention. It is therefore
intended that the present invention not be limited to the exact
forms and details described and illustrated, but fall within the
scope of the appended claims.
* * * * *