Shahidi; Ghavam

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shahidi; Ghavam.The latest application filed is for "cmos-compatible high-speed and low-power random number generator".

Company Profile

5.39.45

Shahidi; Ghavam - Pound Ridge NY
Shahidi; Ghavam - Yorktown Heights NY
Shahidi; Ghavam - Round Ridge NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
CMOS-compatible high-speed and low-power random number generator Grant 11,132,177 - Hekmatshoartabari , et al. September 28, 2	2021-09-28
System implementation of one-time programmable memories Grant 10,884,918 - Subramanian , et al. January 5, 2	2021-01-05
CMOS-Compatible High-Speed and Low-Power Random Number Generator App 20200364032 - Hekmatshoartabari; Bahman ; et al.	2020-11-19
Monolithic Photovoltaics in Series on Insulating Substrate App 20200350449 - Li; Ning ; et al.	2020-11-05
System Implementation Of One-time Programmable Memories App 20200242022 - Subramanian; Chitra ; et al.	2020-07-30
Thin film interconnects with large grains Grant 10,727,121 - Bruce , et al.	2020-07-28
Thin film transistors with epitaxial source/drain contact regions Grant 10,700,211 - Hekmatshoartabari , et al.	2020-06-30
Low-power random number generator Grant 10,671,351 - Hekmatshoartabari , et al.	2020-06-02
Low-power Random Number Generator App 20200065068 - Hekmatshoartabari; Bahman ; et al.	2020-02-27
Thin Film Transistors With Epitaxial Source/drain Contact Regions App 20190165181 - Hekmatshoartabari; Bahman ; et al.	2019-05-30
Thin Film Interconnects With Large Grains App 20190096757 - Bruce; Robert L. ; et al.	2019-03-28
Thin film transistors with epitaxial source/drain contact regions Grant 10,090,415 - Hekmatshoartabari , et al. October 2, 2	2018-10-02
Hybrid Ion-sensitive Field-effect Transistor App 20170059513 - AFZALI-ARDAKANI; ALI ; et al.	2017-03-02
Heterojunction III-V photovoltaic cell fabrication Grant 9,018,675 - Bedell , et al. April 28, 2	2015-04-28
Autonomous integrated circuits Grant 8,969,992 - Bedell , et al. March 3, 2	2015-03-03
Method and structure for forming on-chip high quality capacitors with ETSOI transistors Grant 8,969,938 - Cheng , et al. March 3, 2	2015-03-03
FinFET device having reduce capacitance, access resistance, and contact resistance Grant 8,900,936 - Kulkarni , et al. December 2, 2	2014-12-02
Raised source/drain structure for enhanced strain coupling from stress liner Grant 8,890,245 - Cheng , et al. November 18, 2	2014-11-18
Heterojunction III-V Photovoltaic Cell Fabrication App 20140299181 - Bedell; Stephen W. ; et al.	2014-10-09
Raised source/drain structure for enhanced strain coupling from stress liner Grant 8,853,038 - Cheng , et al. October 7, 2	2014-10-07
Heterojunction III-V photovoltaic cell fabrication Grant 8,802,477 - Bedell , et al. August 12, 2	2014-08-12
Autonomous Integrated Circuits App 20140183686 - Bedell; Stephen W. ; et al.	2014-07-03
Method and structure for forming on-chip high quality capacitors with ETSOI transistors Grant 8,748,258 - Cheng , et al. June 10, 2	2014-06-10
Method and Structure for Forming On-Chip High Quality Capacitors With ETSOI Transistors App 20140124845 - Cheng; Kangguo ; et al.	2014-05-08
Compressively Strained Soi Substrate App 20140099776 - Cheng; Kangguo ; et al.	2014-04-10
Compressively Strained Soi Substrate App 20140097467 - Cheng; Kangguo ; et al.	2014-04-10
Forming narrow fins for finFET devices using asymmetrically spaced mandrels Grant 8,617,937 - Cheng , et al. December 31, 2	2013-12-31
Method and Structure For Forming On-Chip High Quality Capacitors With ETSOI Transistors App 20130146959 - Cheng; Kangguo ; et al.	2013-06-13
Fully-depleted SON Grant 8,455,308 - Cheng , et al. June 4, 2	2013-06-04
Raised Source/drain Structure For Enhanced Strain Coupling From Stress Liner App 20130011975 - CHENG; Kangguo ; et al.	2013-01-10
Raised source/drain structure for enhanced strain coupling from stress liner Grant 8,338,260 - Cheng , et al. December 25, 2	2012-12-25
Raised Source/drain Structure For Enhanced Strain Coupling From Stress Liner App 20120299103 - CHENG; Kangguo ; et al.	2012-11-29
Schottky Barrier Solar Cells With High And Low Work Function Metal Contacts App 20120285517 - Souza; Joel P. de ; et al.	2012-11-15
Fully-depleted Son App 20120235238 - Cheng; Kangguo ; et al.	2012-09-20
FinFET device having reduce capacitance, access resistance, and contact resistance App 20120193713 - Kulkarni; Pranita ; et al.	2012-08-02
Autonomous Integrated Circuit App 20120118383 - Bedell; Stephen W. ; et al.	2012-05-17
Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation Grant 8,169,024 - Cheng , et al. May 1, 2	2012-05-01
Forming Narrow Fins For Finfet Devices Using Asymmetrically Spaced Mandrels App 20120068264 - CHENG; KANGGUO ; et al.	2012-03-22
Extremely Thin Semiconductor-on-Insulator (ETSOI) FET Having a Stair-Shape Raised Source/Drain and a Method of Forming the Same App 20120061759 - Cheng; Kangguo ; et al.	2012-03-15
Contact scheme for FINFET structures with multiple FINs Grant 8,080,838 - Chang , et al. December 20, 2	2011-12-20
Raised Source/drain Structure For Enhanced Strain Coupling From Stress Liner App 20110254090 - Cheng; Kangguo ; et al.	2011-10-20
Ultrathin SOI CMOS devices employing differential STI liners Grant 8,021,956 - Ren , et al. September 20, 2	2011-09-20
Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors Grant 7,968,459 - Bedell , et al. June 28, 2	2011-06-28
Buried channel MOSFET using III-V compound semiconductors and high k gate dielectrics Grant 7,964,896 - Kiewra , et al. June 21, 2	2011-06-21
Strained semiconductor-on-insulator (sSOI) by a simox method Grant 7,897,444 - Adam , et al. March 1, 2	2011-03-01
Method Of Forming Extremely Thin Semiconductor On Insulator (etsoi) Device Without Ion Implantation App 20110042744 - Cheng; Kangguo ; et al.	2011-02-24
Heterojunction III-V Photovoltaic Cell Fabrication App 20100307572 - Bedell; Stephen W. ; et al.	2010-12-09
Method to form Si-containing SOI and underlying substrate with different orientations Grant 7,759,772 - Ieong , et al. July 20, 2	2010-07-20
Ultrathin Soi Cmos Devices Employing Differential Sti Liners App 20100105187 - Ren; Zhibin ; et al.	2010-04-29
Disposable metallic or semiconductor gate spacer Grant 7,682,917 - Bedell , et al. March 23, 2	2010-03-23
Ultrathin SOI CMOS devices employing differential STI liners Grant 7,659,583 - Ren , et al. February 9, 2	2010-02-09
Thin Silicon Single Diffusion Field Effect Transistor For Enhanced Drive Performance With Stress Film Liners App 20090305471 - Chang; Leland ; et al.	2009-12-10
Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer Grant 7,592,671 - Adam , et al. September 22, 2	2009-09-22
CONTACT SCHEME FOR FINFET STRUCTURES WITH MULTIPLE FINs App 20090212366 - Chang; Leland ; et al.	2009-08-27
Disposable Metallic Or Semiconductor Gate Spacer App 20090186455 - Bedell; Stephen W. ; et al.	2009-07-23
STRAINED SEMICONDUCTOR-ON-INSULATOR (sSOI) BY A SIMOX METHOD App 20090134460 - Adam; Thomas N. ; et al.	2009-05-28
Ultrathin Soi Cmos Devices Employing Differential Sti Liners App 20090045462 - Ren; Zhibin ; et al.	2009-02-19
Strained semiconductor-on-insulator (sSOI) by a simox method Grant 7,485,539 - Adam , et al. February 3, 2	2009-02-03
Fully silicided metal gate semiconductor device structure Grant 7,473,975 - Biery , et al. January 6, 2	2009-01-06
STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON GERMANIUM LAYER App 20080277690 - Adam; Thomas N. ; et al.	2008-11-13
Ion Implantation Combined With In Situ Or Ex Situ Heat Treatment For Improved Field Effect Transistors App 20080258220 - Bedell; Stephen W. ; et al.	2008-10-23
METHOD TO FORM Si-CONTAINING SOI AND UNDERLYING SUBSTRATE WITH DIFFERENT ORIENTATIONS App 20080128866 - Ieong; Meikei ; et al.	2008-06-05
BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS App 20080001173 - Kiewra; Edward W. ; et al.	2008-01-03
Contact scheme for FINFET structures with multiple FINs App 20070287256 - Chang; Leland ; et al.	2007-12-13
Formation Of Fully Silicided (fusi) Gate Using A Dual Silicide Process App 20070281431 - Biery; Glenn A. ; et al.	2007-12-06
Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors App 20070257315 - Bedell; Stephen W. ; et al.	2007-11-08
Formation of fully silicided (FUSI) gate using a dual silicide process Grant 7,273,777 - Biery , et al. September 25, 2	2007-09-25
Strained semiconductor-on-insulator (sSOI) by a simox method App 20070164356 - Adam; Thomas N. ; et al.	2007-07-19
Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners App 20070158743 - Chang; Leland ; et al.	2007-07-12
STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON GERMANIUM LAYER App 20070111463 - Adam; Thomas N. ; et al.	2007-05-17
Formation of fully silicided (FUSI) gate using a dual silicide process App 20070032010 - Biery; Glenn A. ; et al.	2007-02-08
Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer Grant 7,172,930 - Adam , et al. February 6, 2	2007-02-06
Method to form Si-containing SOI and underlying substrate with different orientations Grant 7,141,457 - Ieong , et al. November 28, 2	2006-11-28
Method to form Si-containing SOI and underlying substrate with different orientations App 20060105507 - Ieong; Meikei ; et al.	2006-05-18
Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer App 20060003555 - Adam; Thomas N. ; et al.	2006-01-05
Method Of Forming Silicon-on-insulator Wafers Having Process Resistant Applications App 20040266129 - DeSouza, Joel P. ; et al.	2004-12-30

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