U.S. patent application number 11/565299 was filed with the patent office on 2008-06-05 for chip package and fabricating process thereof.
This patent application is currently assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC.. Invention is credited to JAE-SUN AN, SANG-JIN CHA, SOO-MIN CHOI, HYEONG-NO KIM, YOUNG-GUE LEE.
Application Number | 20080128890 11/565299 |
Document ID | / |
Family ID | 39474765 |
Filed Date | 2008-06-05 |
United States Patent
Application |
20080128890 |
Kind Code |
A1 |
CHOI; SOO-MIN ; et
al. |
June 5, 2008 |
CHIP PACKAGE AND FABRICATING PROCESS THEREOF
Abstract
A chip package comprising a carrier, a chip, a plurality of
first conductive elements, an encapsulation, and a conductive film
is provided. The carrier has a carrying surface and a back surface
opposite to the carrying surface. Furthermore, the carrier has a
plurality of common contacts in the periphery of the carrying
surface. The chip is disposed on the carrying surface and
electrically connected to the carrier. In addition, the first
conductive elements are disposed on the common contacts
respectively. The encapsulation is disposed on the carrying surface
and encapsulating the chip. Moreover, the conductive film is
disposed over the encapsulation and the first conductive elements,
so as to electrically connect with the common contacts via the
first conductive elements. A process for fabricating the chip
package is further provided. The chip package is capable of
preventing the EMI problem and thus provides superior electrical
performance.
Inventors: |
CHOI; SOO-MIN; (KYUNGGI-DO,
KR) ; KIM; HYEONG-NO; (KYUNGGI-DO, KR) ; AN;
JAE-SUN; (KYUNGGI-DO, KR) ; LEE; YOUNG-GUE;
(KYUNGGI-DO, KR) ; CHA; SANG-JIN; (KYUNGGI-DO,
KR) |
Correspondence
Address: |
J C PATENTS, INC.
4 VENTURE, SUITE 250
IRVINE
CA
92618
US
|
Assignee: |
ADVANCED SEMICONDUCTOR ENGINEERING,
INC.
KAOHSIUNG
TW
|
Family ID: |
39474765 |
Appl. No.: |
11/565299 |
Filed: |
November 30, 2006 |
Current U.S.
Class: |
257/693 ;
257/E21.502; 257/E23.023; 438/127 |
Current CPC
Class: |
H01L 23/3128 20130101;
H01L 23/552 20130101; H01L 2924/00014 20130101; H01L 2224/4911
20130101; H01L 2924/3025 20130101; H01L 21/56 20130101; H01L
2224/48091 20130101; H01L 2224/48227 20130101; H01L 2224/48091
20130101; H01L 2224/4911 20130101; H01L 2924/045 20130101; H01L
2924/15331 20130101; H01L 2924/181 20130101; H01L 23/34 20130101;
H01L 24/48 20130101; H01L 2924/181 20130101; H01L 2224/48091
20130101; H01L 2924/014 20130101; H01L 2924/00014 20130101; H01L
2924/00014 20130101; H01L 2924/0105 20130101; H01L 2924/15311
20130101; H01L 2924/19107 20130101; H01L 2924/00014 20130101; H01L
2924/01082 20130101; H01L 2224/48227 20130101; H01L 2924/01033
20130101; H01L 2224/48227 20130101; H01L 2924/00012 20130101; H01L
2924/19107 20130101; H01L 2224/05599 20130101; H01L 2924/01047
20130101; H01L 2924/00014 20130101; H01L 2224/05599 20130101; H01L
2224/45099 20130101; H01L 2224/45099 20130101; H01L 2924/00014
20130101; H01L 2924/00012 20130101; H01L 24/49 20130101; H01L
2224/4911 20130101; H01L 2924/19041 20130101; H01L 23/28 20130101;
H01L 2924/181 20130101; H01L 2924/19107 20130101; H01L 2924/19105
20130101; H01L 2924/14 20130101 |
Class at
Publication: |
257/693 ;
438/127; 257/E23.023; 257/E21.502 |
International
Class: |
H01L 23/488 20060101
H01L023/488; H01L 21/56 20060101 H01L021/56 |
Claims
1. A chip package, comprising: a carrier, having a carrying surface
and a back surface opposite to the carrying surface, the carrier
further having a plurality of common contacts in the periphery of
the carrying surface; a chip, disposed on the carrying surface and
electrically connected to the carrier; a plurality of first
conductive elements, disposed on the common contacts respectively;
an encapsulation, disposed on the carrying surface and
encapsulating the chip; and a conductive film, disposed over the
encapsulation and the first conductive elements, so as to connected
to the common contacts via the first conductive elements.
2. The chip package according to claim 1, wherein the first
conductive elements comprise a plurality of first solder balls.
3. The chip package according to claim 1, wherein the first
conductive elements surround the encapsulation.
4. The chip package according to claim 3, further comprising a
conductive bonding layer disposed between the conductive film and
the first conductive elements.
5. The chip package according to claim 4, wherein the conductive
bonding layer is a solder layer.
6. The chip package according to claim 1, wherein the encapsulation
covers the carrying surface and encapsulates the chip and the first
conductive elements, and the encapsulation exposes a top portion of
each first conductive element.
7. The chip package according to claim 6, wherein the conductive
film is directly attached on a top surface of the encapsulation so
as to connect with the first conductive elements.
8. The chip package according to claim 6, further comprising a
plurality of second conductive elements disposed between the
conductive film and the corresponding first conductive elements
respectively.
9. The chip package according to claim 8, wherein the second
conductive elements comprise a plurality of second solder
balls.
10. The chip package according to claim 1, wherein the conductive
film is a metal film.
11. The chip package according to claim 1, wherein the carrier is a
circuit substrate.
12. The chip package according to claim 1, further comprising a
plurality of conductive bumps, the chip being electrically
connected with the carrier by a flip chip manner.
13. The chip package according to claim 1, further comprising a
plurality of wires connected between the chip and the carrier and
encapsulated by the encapsulation.
14. The chip package according to claim 1, further comprising a
plurality of third solder balls disposed on the back surface of the
carrier, the third solder balls being electrically connected with
the chip and/or the first conductive elements via the carrier
respectively.
15. A chip packaging process, comprising: providing a carrier which
has a carrying surface and a back surface opposite to the carrying
surface, the carrier further having a plurality of common contacts
in the periphery of the carrying surface; disposing a chip on the
carrying surface and electrically connecting the chip to the
carrier; forming an encapsulation on the carrying surface, wherein
the encapsulation encapsulates the chip; forming a plurality of
first conductive elements on the corresponding common contacts; and
providing a conductive film on the encapsulation and electrically
connecting the conductive film to the common contacts via the first
conductive elements.
16. The chip packaging process according to claim 15, wherein the
first conductive elements are fabricated by forming a first solder
ball on each common contact respectively.
17. The chip packaging process according to claim 15, further
comprising forming a conductive bonding layer between the
conductive film and the first conductive elements so as to connect
the conductive film to the first conductive elements via the
conductive bonding layer.
18. The chip packaging process according to claim 17, wherein the
conductive bonding layer is fabricated by coating a solder layer on
the conductive film.
19. The chip packaging process according to claim 15, wherein the
chip is bonded to the carrier by flip chip bonding technology.
20. The chip packaging process according to claim 15, wherein the
chip is bonded to the carrier by wire bonding technology.
21. The chip packaging process according to claim 15, further
comprising forming a plurality of second solder balls on the back
surface of the carrier, the second solder balls being electrically
connected with the chip and/or the first conductive elements via
the carrier respectively.
22. A chip packaging process, comprising: providing a carrier which
has a carrying surface and a back surface opposite to the carrying
surface, the carrier further having a plurality of common contacts
in the periphery of the carrying surface; disposing a chip on the
carrying surface and electrically connecting the chip to the
carrier; forming a plurality of first conductive elements on the
corresponding common contacts; forming an encapsulation for
covering the carrying surface and encapsulating the chip and the
first conductive elements, the encapsulation exposing a top portion
of each first conductive element; providing a conductive film and
forming a plurality of second conductive elements on a surface of
the conductive film; and disposing the conductive film over the
encapsulation and connecting the second conductive elements to the
corresponding first conductive elements, wherein the conductive
film is electrically connected to the common contacts via the first
conductive elements and the second conductive elements.
23. The chip packaging process according to claim 22, wherein the
first conductive elements are fabricated by forming a first solder
ball on each common contact respectively.
24. The chip packaging process according to claim 22, wherein the
second conductive elements are fabricated by forming a plurality of
second solder balls on the conductive film.
25. The chip packaging process according to claim 22, wherein the
chip is bonded to the carrier by flip chip bonding technology.
26. The chip packaging process according to claim 22, wherein the
chip is bonded to the carrier by wire bonding technology.
27. The chip packaging process according to claim 22, further
comprising forming a plurality of third solder balls on the back
surface of the carrier, the third solder balls being electrically
connected with the chip and/or the first conductive elements via
the carrier respectively.
28. A chip packaging process, comprising: providing a carrier which
has a carrying surface and a back surface opposite to the carrying
surface, the carrier further having a plurality of common contacts
in the periphery of the carrying surface; disposing a chip on the
carrying surface and electrically connecting the chip to the
carrier; forming a plurality of first conductive elements on the
corresponding common contacts; forming an encapsulation for
covering the carrying surface and encapsulating the chip and the
first conductive elements, the encapsulation exposing a top portion
of each first conductive element; and forming a conductive film on
a top surface of the encapsulation so as to electrically connect
the conductive film to the common contacts via the first conductive
elements.
29. The chip packaging process according to claim 28, wherein the
first conductive elements are fabricated by forming a first solder
ball on each common contact respectively.
30. The chip packaging process according to claim 28, wherein the
conductive film is fabricated by spraying a conductive material on
the top surface of the encapsulation.
31. The chip packaging process according to claim 28, wherein the
chip is bonded to the carrier by flip chip bonding technology.
32. The chip packaging process according to claim 28, wherein the
chip is bonded to the carrier by wire bonding technology.
33. The chip packaging process according to claim 28, further
comprising forming a plurality of second solder balls on the back
surface of the carrier, the second solder balls being electrically
connected with the chip and/or the first conductive elements via
the carrier respectively.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention generally relates to a chip package.
More particularly, the present invention relates to a chip package
having electromagnetic interference (EMI) shielding function.
[0003] 2. Description of Related Art
[0004] In the manufacturing of integrated circuits, ultimate size
of the package is an important issue. As the level of integration
and functions of integrated circuits increase, the number of
conductive leads required for connections with external circuitry
is also increased. Furthermore, as the operating speed of chip goes
higher, the amount of heat generated by the chip and electrical
interference caused by external electromagnetic fields during
operation can no longer be ignored. A typical high-density area
array package is the ball grid array (BGA) type package.
Nonetheless, the thermal dissipation and the EMI problems of the
BGA type package or even other types of chip package are still
unresolved, and need to be carefully considered in the design of a
high-density area array package.
SUMMARY OF THE INVENTION
[0005] Accordingly, the present invention is directed to a chip
package which is capable of eliminating the EMI problem and
provides superior electrical performance.
[0006] The present invention is also directed to a fabricating
process of the chip package having EMI shielding ability.
[0007] As embodied and broadly described herein, the present
invention provides a chip package comprising a carrier, a chip, a
plurality of first conductive elements, an encapsulation, and a
conductive film. The carrier has a carrying surface and a back
surface opposite to the carrying surface. Furthermore, the carrier
has a plurality of common contacts in the periphery of the carrying
surface. The chip is disposed on the carrying surface and
electrically connected to the carrier. In addition, the first
conductive elements are disposed on the common contacts
respectively. The encapsulation is disposed on the carrying surface
and encapsulating the chip. Moreover, the conductive film is
disposed over the encapsulation and the first conductive elements,
so as to electrically connect with the common contacts via the
first conductive elements.
[0008] The present invention also provides a chip packaging
process, comprising: providing a carrier which has a carrying
surface and a back surface opposite to the carrying surface, the
carrier further having a plurality of common contacts in the
periphery of the carrying surface; disposing a chip on the carrying
surface and electrically connecting the chip to the carrier;
forming an encapsulation on the carrying surface, wherein the
encapsulation encapsulates the chip; forming a plurality of first
conductive elements on the corresponding common contacts; and
providing a conductive film on the encapsulation and electrically
connecting the conductive film to the common contacts via the first
conductive elements.
[0009] The present invention further provides a chip packaging
process, comprising: providing a carrier which has a carrying
surface and a back surface opposite to the carrying surface, the
carrier further having a plurality of common contacts in the
periphery of the carrying surface; disposing a chip on the carrying
surface and electrically connecting the chip to the carrier;
forming a plurality of first conductive elements on the
corresponding common contacts; forming an encapsulation for
covering the carrying surface and encapsulating the chip and the
first conductive elements, wherein the encapsulation exposes a top
portion of each first conductive element; providing a conductive
film and forming a plurality of second conductive elements on a
surface of the conductive film; and disposing the conductive film
over the encapsulation and connecting the second conductive
elements to the corresponding first conductive elements, wherein
the conductive film is electrically connected to the common
contacts via the first conductive elements and the second
conductive elements.
[0010] Moreover, the present invention provides a chip packaging
process, comprising: providing a carrier which has a carrying
surface and a back surface opposite to the carrying surface, the
carrier further having a plurality of common contacts in the
periphery of the carrying surface; disposing a chip on the carrying
surface and electrically connecting the chip to the carrier;
forming a plurality of first conductive elements on the
corresponding common contacts; forming an encapsulation for
covering the carrying surface and encapsulating the chip and the
first conductive elements, the encapsulation exposing a top portion
of each first conductive element; and forming a conductive film on
a top surface of the encapsulation so as to electrically connect
the conductive film to the common contacts via the first conductive
elements.
[0011] To sum up, the present invention disposes the conductive
film over the encapsulation to form a common plane in the chip
package, so as to solve the problem of EMI for the chip package.
Therefore, products utilizing the chip package and the chip
packaging process can achieve superior electrical performance and
higher reliability.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The accompanying drawings are included to provide a further
understanding of the invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the invention and, together with the description,
serve to explain the principles of the invention.
[0013] FIG. 1A illustrates a chip package according to an
embodiment of the present invention.
[0014] FIG. 1B and FIG. 1C show other chip packages utilizing
different types of circuit substrate as carriers in comparison with
that in FIG. 1A.
[0015] FIGS. 2A.about.2E show a chip package process of the chip
packages in FIGS. 1A.about.1C according to an embodiment of the
present.
[0016] FIG. 3A illustrates a chip package according to another
embodiment of the present invention.
[0017] FIG. 3B and FIG. 3C respectively show other chip packages
utilizing different types of circuit substrate as carriers in
comparison with that in FIG. 3A.
[0018] FIGS. 4A.about.4F show a chip package process of the chip
packages in FIGS. 3A.about.3C according to an embodiment of the
present.
[0019] FIG. 5A illustrates a chip package according to further
another embodiment of the present invention.
[0020] FIG. 5B and FIG. 5C respectively show other chip packages
utilizing different types of circuit substrate as carriers in
comparison with that in FIG. 5A.
[0021] FIGS. 6A.about.6E show a chip package process of the chip
packages in FIGS. 5A.about.5C according to an embodiment of the
present.
DESCRIPTION OF THE EMBODIMENTS
[0022] The present invention proposes a chip package with EMI
shielding to improve the electrical performance and the reliability
thereof. Embodiments are now given in the following to illustrate
various arrangements of the chip package of the present invention.
Furthermore, the accompanying fabricating processes of the chip
package are also illustrated in the corresponding embodiments.
[0023] Reference will now be made in detail to the present
embodiments of the invention, examples of which are illustrated in
the accompanying drawings. Wherever possible, the same reference
numbers are used in the drawings and the description to refer to
the same or like parts.
[0024] FIG. 1A illustrates a chip package according to an
embodiment of the present invention. Referring to FIG. 1A, the chip
package 100 includes a carrier 110, a chip 120, first conductive
elements 132, an encapsulation 140, and a conductive film 150. The
carrier 110 has a carrying surface 110a and a back surface 110b
opposite to the carrying surface 110a, wherein a plurality of
common contacts 112 and bonding pads 114 is disposed in the
periphery of the carrying surface 110a. It is noted that the
embodiment shows a BGA type chip package 100 which utilize a
circuit substrate as the carrier 110, however, there is no set
limit on the type of carrier, while other known appropriate chip
package type, such as Pin Grid Array (PGA) type, Quad Flat Package
(QFP) type and so on, can also be carried out in the present
invention.
[0025] In addition, the chip 120 is disposed on the carrying
surface 110a of the carrier 110 and is electrically connected with
the carrier 110 by performing, for example, a wire bonding process,
wherein the chip 120 is connected to the bonding pads 114 of the
carrier 110 via plural wires 160. It is noted that there is no
limit on the manners for bonding the chip 120 and the carrier 110
in the present invention. For example, a flip chip bonding process
may be carried out in another embodiment of the present invention
to connect the chip 120: with the carrier 110 via a plurality of
conductive bumps (not shown).
[0026] The first conductive elements 132 are disposed on the common
contacts 112 respectively. For example, the first conductive
elements 132 can be solder balls or other appropriate conductive
objects, such as solder bumps. In the embodiment, there may also be
some peripheral devices 102 disposed on the carrying surface 110a
of the carrier 110, wherein the peripheral devices 102 may be
passive devices, such as capacitors, resistors, or inductors, which
are electrically connected with the chip 120 via the carrier
110.
[0027] The encapsulation 140 is disposed on the carrying surface
110a of the carrier 110 to encapsulate the chip 120, the bonding
pads 114, the wires 160 and the peripheral devices 102. Besides,
the encapsulation 140 exposes the common contacts 112 and the first
conductive elements 132 thereon. In other words, the first
conductive elements 132 are arranged around the encapsulation 140.
Moreover, the conductive film 150 is disposed over the
encapsulation 140 and the first conductive elements 132, so as to
be electrically connected with the common contacts 112 via the
first conductive elements 132. By applying a common voltage on the
conductive film 150 through the common contacts 112, the conductive
film 150 can serve as a common plane in the chip package 100 to
provide an EMI shielding effect. Specifically, the conductive film
150 of the embodiment can be manufactured by providing a metal
sheet. Furthermore, the periphery surface of the conductive film
150 is coated with a conductive bonding layer 152, such as a solder
layer. The conductive film 150 is connected with the first
conductive elements 132 via the conductive bonding layer 152.
[0028] The chip package 100 further comprise a plurality of solder
balls 172 and 174 arranged in array on the back surface 110b of the
carrier 110. The solder balls 172 are distributed in the periphery
of the back surface 110b and connected with the common contacts
112. Thus, the conductive film 150 can be electrically connected
with an external circuitry for the common voltage via the solder
balls 172. Besides, the solder balls 174 are distributed in the
center region of the back surface 110b and electrically connected
with the bonding pads 114 via the carrier 110. The chip 120 and the
peripheral devices 102 can be connected with another external
circuitry for driving signals via the solder balls 174.
[0029] It should be noted that, in the present invention, the chip
and the peripheral devices may further be electrically connected
with the common contacts to share the common voltage with the
conductive film by rearranging the wires and the interconnections
of the carrier.
[0030] Accordingly, FIG. 1B and FIG. 1C show other chip packages
utilizing different types of circuit substrate as carriers
respectively according to other embodiments of the present
invention. Since most of the elements in the chip packages of FIG.
1B and FIG. 1C have been described in the aforementioned
embodiment, details are not repeated herein.
[0031] Referring to FIG. 1B, expect the common contacts 112, the
carrier 100 further has at least one extending contact 116 on the
carrying surface 110a, wherein the extending contact is
electrically connected with the common contacts 112 via the
interconnections 190 in the carrier 110. In addition, the chip 120
and the bonding pads 114 may be electrically connected with the
extending contact 116 via a part of the wires 160. Thus, the chip
120 and the peripheral devices 102 can take the common voltage from
the common contacts 112 as, for example, a ground voltage.
[0032] FIG. 1C shows another chip package 100 with different
arrangement of solder balls, wherein the solder balls 172 for
providing the common voltage is disposed in the center region of
the back surface 110b and electrically connected with the common
contacts 112 via the interconnections 190 in the carrier 110. In
addition, the solder balls 174 for providing the driving signals
are distributed in the periphery of the back surface 110b and
electrically connected with the bonding pads 114 via the carrier
110.
[0033] For providing a more detailed and clear disclosure of the
present invention, a chip package process for fabricating the
aforementioned chip packages 100 is illustrated in the following.
Since most of the elements of the chip packages 100 have been
mentioned in the aforementioned embodiments, detailed descriptions
are not repeated in the following.
[0034] FIGS. 2A.about.2E show the chip package process according to
an embodiment of the present. First, as shown in FIG. 2A, the
carrier 110 having the carrying surface 110a and the back surface
110b is provided. Then, as shown in FIG. 2B, the chip 120 and the
peripheral devices 102 are disposed on the carrying surface 110a of
the carrier 110. The chip is bonded to the carrier 110 by wire
bonding, flip chip bonding or other appropriate bonding manners. In
addition, the peripheral devices 102 may be mounted on the carrier
110 by surface mount technology (SMT).
[0035] Next, as shown in FIG. 2C, the encapsulation 140 is formed
on the carrying surface 110a of the carrier to encapsulate the chip
120, the bonding pads 114, the wires 160 and the peripheral devices
102. Thereafter, as shown in FIG. 2D, the first conductive elements
132 are formed on the corresponding common contacts 112, wherein
the first conductive elements 132 surround the encapsulation 140.
In the embodiment, the first conductive elements 132 are fabricated
by forming a solder ball on each common contact 112
respectively.
[0036] Then, as shown in FIG. 2E, the conductive film 150 is
provided on the encapsulation 140 and electrically connected with
the common contacts 112 via the first conductive elements 132.
Herein, the conductive bonding layer 152 is formed between the
conductive film 150 and the first conductive elements 132 before
providing the conductive film 150 on the encapsulation 140, so as
to connect the conductive film 150 to the first conductive elements
132 via the conductive bonding layer 152. After that, the solder
balls 172 and 174 can be selectively formed on the back surface
110b of the carrier 110, wherein the solder balls 172 and 174 are
electrically connected with the chip 120, the peripheral devices
102 and/or the first conductive elements 132 via the carrier 110
respectively.
[0037] It is noted that the above fabricating process as shown in
FIGS. 2A.about.2E focuses on a single chip package. Practically,
the above fabricating process is applied on an array type carrier
and then forms a plurality of chip packages at the same time. Thus,
a singulation process may further be carried out after the steps
mentioned above to achieve a single chip package.
[0038] In addition to the above embodiments, other types of chip
packages and the corresponding fabricating processes thereof are
illustrated in the following.
[0039] FIG. 3A illustrates a chip package according to another
embodiment of the present invention. Referring to FIG. 3A, the chip
package 300 includes a carrier 310, a chip 320, first conductive
elements 332, second conductive elements 334, an encapsulation 340,
and a conductive film 350. The carrier 310 has a carrying surface
310a and a back surface 310b opposite to the carrying surface 310a.
A plurality of common contacts 312 and bonding pads 314 is disposed
in the periphery of the carrying surface 310a. It is noted that the
embodiment shows a BGA type chip package 300 which utilize a
circuit substrate as the carrier 310, however, there is no set
limit on the type of carrier, while other known appropriate chip
package type, such as PGA type, QFP type and so on, can also be
carried out in the present invention.
[0040] The chip 320 is disposed on the carrying surface 310a of the
carrier 310 and is electrically connected with the carrier 310 by
performing, for example, a wire bonding process, wherein the chip
320 is connected to the bonding pads 314 of the carrier 310 via
plural wires 360. It is noted that there is no limit on the manners
for bonding the chip 320 and the carrier 310 in the present
invention. For example, a flip chip bonding process may be carried
out in another embodiment of the present invention to connect the
chip 320 with the carrier 310 via a plurality of conductive bumps
(not shown).
[0041] The first conductive elements 332 are disposed on the common
contacts 312 respectively. For example, the first conductive
elements 332 can be solder balls or other appropriate conductive
objects, such as solder bumps. In the embodiment, there may also be
some peripheral devices 302 disposed on the carrying surface 310a
of the carrier 310, wherein the peripheral devices 302 may be
passive devices, such as capacitors, resistors, or inductors, which
are electrically connected with the chip 320 via the carrier
310.
[0042] The encapsulation 340 is disposed on the whole carrying
surface 310a of the carrier 310 to encapsulate the chip 320, the
first conductive elements 332, the common contacts 312, the bonding
pads 314, the wires 360 and the peripheral devices 302.
Particularly, the encapsulation 340 exposes a top portion of each
first conductive element 332. In addition, the conductive film 350
is disposed over the encapsulation 340 and the first conductive
elements 332. The second conductive elements 334 are disposed
between the conductive film 350 and the corresponding first
conductive elements 332 respectively, so as to electrically connect
the conductive film 350 with the common contacts 312. In the
embodiment, the second conductive elements 334 may be solder balls
or other appropriate conductive elements such as solder bumps, or
silver paste.
[0043] By applying a common voltage on the conductive film 350
through the common contacts 312, the conductive film 350 can serve
as a common plane in the chip package 300 to provide an EMI
shielding effect. Specifically, the conductive film 350 of the
embodiment can be manufactured by providing a metal sheet. Then,
the second conductive elements 334 are disposed in the periphery
surface of the conductive film 350. Therefore, the conductive film
350 can be electrically connected with the first conductive
elements 332 via the second conductive elements 334.
[0044] The chip package 300 further comprise a plurality of solder
balls 372 and 374 arranged in array on the back surface 310b of the
carrier 310. The solder balls 372 are distributed in the periphery
of the back surface 310b and connected with the common contacts
312. Thus, the conductive film 350 can be electrically connected
with an external circuitry for the common voltage via the solder
balls 372. Besides, the solder balls 374 are distributed in the
center region of the back surface 310b and electrically connected
with the bonding pads 314 via the carrier 310. The chip 320 and the
peripheral devices 302 can be connected with another external
circuitry for driving signals via the solder balls 374.
[0045] Similar to the above illustrations of FIG. 1B and FIG. 1C,
the chip 320 and the peripheral devices 302 of the aforementioned
embodiment may further be electrically connected with the common
contacts 312 to share the common voltage with the conductive film
350 by rearranging the wires 360 and the interconnections of the
carrier 310. Referring to FIG. 3B and FIG. 3C, which respectively
show other chip packages utilizing different types of circuit
substrate as carriers according to other embodiments of the present
invention. Since most of the elements in the chip packages of FIG.
3B and FIG. 3C have been described in the aforementioned
embodiment, details are not repeated herein.
[0046] As shown in FIG. 3B, expect the common contacts 312, the
carrier 300 further has at least one extending contact 316 on the
carrying surface 310a, wherein the extending contact is
electrically connected with the common contacts 312 via the
interconnections 390 in the carrier 310. In addition, the chip 320
and the bonding pads 314 may be electrically connected with the
extending contact 316 via a part of the wires 360. Thus, the chip
320 and the peripheral devices 302 can take the common voltage from
the common contacts 312 as, for example, a ground voltage.
[0047] FIG. 3C shows another chip package 300 with different
arrangement of solder balls, wherein the solder balls 372 for
providing the common voltage is disposed in the center region of
the back surface 310b and electrically connected with the common
contacts 312 via the interconnections 390 in the carrier 310. In
addition, the solder balls 374 for providing the driving signals
are distributed in the periphery of the back surface 310b and
electrically connected with the bonding pads 314 via the carrier
310.
[0048] In order to provide a more detailed and clear disclosure of
the present invention, a chip package process for fabricating the
aforementioned chip packages 300 is illustrated in the following.
Since most of the elements of the chip packages 300 have been
mentioned in the aforementioned embodiments, detailed descriptions
are not repeated in the following.
[0049] FIGS. 4A.about.4F show the chip package process according to
an embodiment of the present. First, as shown in FIG. 4A, the
carrier 310 having the carrying surface 310a and the back surface
310b is provided. Then, as shown in FIG. 4B, the chip 320 and the
peripheral devices 302 are disposed on the carrying surface 310a of
the carrier 310. The chip is bonded to the carrier 310 by wire
bonding, flip chip bonding or other appropriate bonding manners. In
addition, the peripheral devices 302 may be mounted on the carrier
310 by SMT.
[0050] Next, as shown in FIG. 4C, the first conductive elements 332
are formed on the corresponding common contacts 312. In the
embodiment, the first conductive elements 332 are fabricated by
forming a solder ball on each common contact 312 respectively.
Then, as shown in FIG. 4D, the encapsulation 340 is formed on the
whole carrying surface 310a of the carrier to encapsulate the chip
320, the peripheral devices 302, the common contacts 312, the
bonding pads 314, the wires 360 and the first conductive elements
332. It is noted that the encapsulation 340 shall expose a top
portion of each first conductive element 332.
[0051] Thereafter, as shown in FIG. 4E, the conductive film 350 is
provided and the second conductive elements 334 are formed on a
surface of the conductive film 350. In the embodiment, the second
conductive elements 334 are fabricated by forming a plurality of
solder balls on the conductive film 350.
[0052] Then, as shown in FIG. 4F, the conductive film 350 is
disposed on the encapsulation 340 and the second conductive
elements 334 on the conductive film 350 are connected to the
corresponding first conductive elements 332, wherein the conductive
film 350 is electrically connected to the common contacts 312 via
the first conductive elements 332 and the second conductive
elements 334. After that, the solder balls 372 and 374 can be
selectively formed on the back surface 310b of the carrier 310,
wherein the solder balls 372 and 374 are electrically connected
with the chip 320, the peripheral devices 302, and/or the first
conductive elements 332 via the carrier 310 respectively.
[0053] It is noted that the above fabricating process as shown in
FIGS. 4A.about.4F focuses on a single chip package. Practically,
the above fabricating process is applied on an array type carrier
and then forms a plurality of chip packages at the same time. Thus,
a singulation process may further be carried out after the steps
mentioned above to achieve a single chip package.
[0054] FIG. 5A illustrates a chip package according to further
another embodiment of the present invention. Referring to FIG. 5A,
the chip package 500 includes a carrier 510, a chip 520, first
conductive elements 532, an encapsulation 540, and a conductive
film 550. The carrier 510 has a carrying surface 510a and a back
surface 510b opposite to the carrying surface 510a. A plurality of
common contacts 512 and bonding pads 514 is disposed in the
periphery of the carrying surface 510a. It is noted that the
embodiment shows a BGA type chip package 500 which utilize a
circuit substrate as the carrier 510, however, there is no set
limit on the type of carrier, while other known appropriate chip
package type, such as PGA type, QFP type and so on, can also be
carried out in the present invention.
[0055] The chip 520 is disposed on the carrying surface 510a of the
carrier 510 and is electrically connected with the carrier 510 by
performing, for example, a wire bonding process, wherein the chip
520 is connected to the bonding pads 514 of the carrier 510; via
plural wires 560. It is noted that there is no limit on the manners
for bonding the chip 520 and the carrier 510 in the present
invention. For example, a flip chip bonding process may be carried
out in another embodiment of the present invention to connect the
chip 520 with the carrier 510 via a plurality of conductive bumps
(not shown).
[0056] The first conductive elements 532 are disposed on the common
contacts 512, respectively. For example, the first conductive
elements 532 can be solder balls or other appropriate conductive
objects, such as solder bumps. In the embodiment, there may also be
some peripheral devices 502 disposed on the carrying surface 510a
of the carrier 510, wherein the peripheral devices 502 may be
passive devices, such as capacitors, resistors, or inductors, which
are electrically connected with the chip 520 via the carrier
510.
[0057] The encapsulation 540 is disposed on the whole carrying
surface 510a of the carrier 510 to encapsulate the chip 520, the
first conductive elements 532, the common contacts 512, the bonding
pads 514, the wires 560 and the peripheral devices 502.
Particularly, the encapsulation 540 exposes a top portion of each
first conductive element 532. In addition, the conductive film 550
is directly attached on a top surface of the encapsulation 540 so
as to connect with the first conductive elements 532.
[0058] By applying a common voltage on the conductive film 550
through the common contacts 512, the conductive film 550 can serve
as a common plane in the chip package 500 to provide an EMI
shielding effect. Specifically, the conductive film 550 of the
embodiment can be manufactured by spraying a conductive material on
the top surface of the encapsulation 540. Therefore, the conductive
film 550 can be electrically connected with the common contacts 512
via the first conductive elements 532.
[0059] The chip package 500 further comprise a plurality of solder
balls 572 and 574 arranged in array on the back surface 510b of the
carrier 510. The solder balls 572 are distributed in the periphery
of the back surface 510b and connected with the common contacts
512. Thus, the conductive film 550 can be electrically connected
with an external circuitry for the common voltage via the solder
balls 572. Besides, the solder balls 574 are distributed in the
center region of the back surface 510b and electrically connected
with the bonding pads 514 via the carrier 510. The chip 520 and the
peripheral devices 502 can be connected with another external
circuitry for driving signals via the solder balls 574.
[0060] Similar to the above illustrations of FIGS. 1B, 1C and FIGS.
3B, 3C, the chip 520 and the peripheral devices 502 of the
aforementioned embodiment may further be electrically connected
with the common contacts 512 to share the common voltage with the
conductive film 550 by rearranging the wires 560 and the
interconnections of the carrier 510. Referring to FIG. 5B and FIG.
5C, which respectively show other chip packages utilizing different
types of circuit substrate as carriers in comparison with that in
FIG. 5A. Since most of the elements in the chip packages of FIG. 5B
and FIG. 5C have been described in the aforementioned embodiment,
details are not repeated herein.
[0061] As shown in FIG. 5B, expect the common contacts 512, the
carrier 500 further has at least one extending contact 516 on the
carrying surface 510a, wherein the extending contact is
electrically connected with the common contacts 512 via the
interconnections 590 in the carrier 510. In addition, the chip 520
and the bonding pads 514 may be electrically connected with the
extending contact 516 via a part of the wires 560. Thus, the chip
520 and the peripheral devices 502 can take the common voltage from
the common contacts 512 as, for example, a ground voltage.
[0062] FIG. 5C shows another chip package 500 with different
arrangement of solder balls, wherein the solder balls 572 for
providing the common voltage is disposed in the center region of
the back surface 510b and electrically connected with the common
contacts 512 via the interconnections 590 in the carrier 510. In
addition, the solder balls 574 for providing the driving signals
are distributed in the periphery of the back surface 510b and
electrically connected with the bonding pads 514 via the carrier
510.
[0063] In order to provide a more detailed and clear disclosure of
the present invention, a chip package process for fabricating the
aforementioned chip packages 500 is illustrated in the following.
Since most of the elements of the chip packages 500 have been
mentioned in the aforementioned embodiments, detailed descriptions
are not repeated in the following.
[0064] FIGS. 6A.about.6E show the chip package process according to
an embodiment of the present. First, as shown in FIG. 6A, the
carrier 510 having the carrying surface 510a and the back surface
510b is provided. Then, as shown in FIG. 6B, the chip 520 and the
peripheral devices 502 are disposed on the carrying surface 510a of
the carrier 510. The chip is bonded to the carrier 510 by wire
bonding, flip chip bonding or other appropriate bonding manners. In
addition, the peripheral devices 502 may be mounted on the carrier
510 by SMT.
[0065] Next, as shown in FIG. 6C, the first conductive elements 532
are formed on the corresponding common contacts 512. In the
embodiment, the first conductive elements 532 are fabricated by
forming a solder ball on each common contact 512 respectively.
Then, as shown in FIG. 6D, the encapsulation 540 is formed on the
whole carrying surface 510a of the carrier to encapsulate the chip
520, the peripheral devices 502, the common contacts 512, the
bonding pads 514, the wires 560 and the first conductive elements
532. It is noted that the encapsulation 540 shall expose a top
portion of each first conductive element 532.
[0066] Thereafter, as shown in FIG. 6E, the conductive film 550 is
formed by spraying a conductive material on the top surface of the
encapsulation 540. Therefore, the conductive film 550 can be
electrically connected to the common contacts 512 via the first
conductive elements 532. After that, the solder balls 572 and 574
can be selectively formed on the back surface 510b of the carrier
510, wherein the solder balls 572 and 574 are electrically
connected with the chip 520, the peripheral devices 502 and/or the
first conductive elements 532 via the carrier 510 respectively.
[0067] It is noted that the above fabricating process as shown in
FIGS. 6A.about.6E focuses on a single chip package. Practically,
the above fabricating process is applied on an array type carrier
and then forms a plurality of chip packages at the same time. Thus,
a singulation process may further be carried out after the steps
mentioned above to achieve a single chip package.
[0068] In summary, the present invention provides structures and
the fabricating method thereof to integrate a conductive film into
a chip package, wherein the conductive film can be taken as a
common plane, so as to solve the problem of EMI for the chip
package. Therefore, products utilizing the chip package and the
chip packaging process can achieve superior electrical performance
and higher reliability.
[0069] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
present invention without departing from the scope or spirit of the
invention. In view of the foregoing, it is intended that the
present invention cover modifications and variations of this
invention provided they fall within the scope of the following
claims and their equivalents.
* * * * *