U.S. patent application number 11/941793 was filed with the patent office on 2008-05-22 for gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials.
This patent application is currently assigned to Applied Materials, Inc.. Invention is credited to Won B. Bang, Vikash Banthia, Nitin K. Ingle, Yen-Kun V. Wang, Shan Wong, Xinyun Xia.
Application Number | 20080115726 11/941793 |
Document ID | / |
Family ID | 35943864 |
Filed Date | 2008-05-22 |
United States Patent
Application |
20080115726 |
Kind Code |
A1 |
Ingle; Nitin K. ; et
al. |
May 22, 2008 |
GAP-FILL DEPOSITIONS INTRODUCING HYDROXYL-CONTAINING PRECURSORS IN
THE FORMATION OF SILICON CONTAINING DIELECTRIC MATERIALS
Abstract
A chemical vapor deposition method for forming a dielectric
material in a trench formed on a substrate. The method includes
flowing a silicon-containing precursor into a process chamber
housing the substrate, flowing an oxidizing gas into the chamber,
and providing a hydroxyl-containing precursor in the process
chamber. The method also includes reacting the silicon-containing
precursor, oxidizing gas and hydroxyl-containing precursor to form
the dielectric material in the trench. The ratio of the
silicon-containing precursor to the oxidizing gas flowed into the
chamber is increased over time to alter a rate of deposition of the
dielectric material.
Inventors: |
Ingle; Nitin K.; (Santa
Clara, CA) ; Wong; Shan; (San Jose, CA) ; Xia;
Xinyun; (Sunnyvale, CA) ; Banthia; Vikash;
(Mountain View, CA) ; Bang; Won B.; (Gilroy,
CA) ; Wang; Yen-Kun V.; (Union City, CA) |
Correspondence
Address: |
TOWNSEND AND TOWNSEND AND CREW LLP / AMAT
TWO EMBARCADERO CENTER, EIGHTH FLOOR
SAN FRANCISCO
CA
94111-3834
US
|
Assignee: |
Applied Materials, Inc.
Santa Clara
CA
|
Family ID: |
35943864 |
Appl. No.: |
11/941793 |
Filed: |
November 16, 2007 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11213612 |
Aug 26, 2005 |
7335609 |
|
|
11941793 |
|
|
|
|
60605116 |
Aug 27, 2004 |
|
|
|
Current U.S.
Class: |
118/696 ;
257/E21.275; 257/E21.279; 257/E21.546 |
Current CPC
Class: |
C23C 16/401 20130101;
H01L 21/31612 20130101; H01L 21/76837 20130101; H01L 21/02271
20130101; H01L 21/02129 20130101; H01L 21/02126 20130101; H01L
21/31625 20130101; C23C 16/045 20130101; H01L 21/02274 20130101;
H01L 21/02164 20130101; H01L 21/76224 20130101 |
Class at
Publication: |
118/696 |
International
Class: |
B05C 11/00 20060101
B05C011/00 |
Claims
1. A substrate processing apparatus comprising: a substrate support
configured to support a substrate within a processing chamber; a
gas delivery system configured to receive a silicon-containing
precursor, a hydroxyl-containing precursor and an oxidizing
processing gas and deliver them to the processing chamber; and a
controller configured to control the gas delivery system and the
substrate support, wherein the controller introduces the
silicon-containing precursor, the hydroxyl-containing precursor and
oxidizing processing gas into the processor chamber to form a
dielectric layer on the substrate, and alter the position of the
substrate support relative to the gas delivery system during the
deposition of the dielectric layer.
2. The substrate processing chamber of claim 1, wherein the
controller varies the concentration of the silicon-containing
precursor to the oxidizing processing gas over time during the
deposition of the dielectric layer on the substrate, as the
silicon-containing precursor gas is continuously flowed into the
chamber.
3. The substrate processing chamber of claim 1, wherein the
controller moves the substrate support closer to the gas delivery
system during the deposition of the dielectric layer to increase a
deposition rate for the dielectric layer.
4. The substrate processing chamber of claim 1, wherein the gas
delivery system comprises separate channels to deliver the
silicon-containing precursor and the hydroxyl-containing precursor
to the processing chamber.
5. The substrate processing chamber of claim 1, wherein the
silicon-containing precursor comprises tetraethylorthosilicate
(TEOS), the hydroxyl-containing precursor comprises H.sub.2O, and
the oxidizing processing gas comprises ozone.
Description
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. patent application
Ser. No. 11/213,612, entitled "GAP-FILL DEPOSITIONS INTRODUCING
HYDROXYL-CONTAINING PRECURSORS IN THE FORMATION OF SILICON
CONTAINING DIELECTRIC MATERIALS," filed Aug. 26, 2005, which claims
the benefit of U.S. Provisional Application No. 60/605,116, filed
Aug. 27, 2004, and entitled "GAP-FILL DEPOSITIONS INTRODUCING
HYDROXYL-CONTAINING PRECURSORS IN THE FORMATION OF SILICON
CONTAINING DIELECTRIC MATERIALS," the entire contents of which are
herein incorporated by this reference
BACKGROUND OF THE INVENTION
[0002] The fabrication sequence of integrated circuits often
includes several patterning processes. The patterning processes may
define a layer of conductors, such as a patterned metal or
polysilicon layer, or may define isolation structures, such as
trenches. In many cases the trenches are filled with an insulating,
or dielectric, material. This insulating material can serve several
functions. For example, in some applications the material serves to
both electrically isolate one region of the IC from another, and
electrically passivate the surface of the trench. The material also
typically provides a base for the next layer of the semiconductor
to be built upon.
[0003] After patterning a substrate, the patterned material is not
flat. The topology of the pattern can interfere with or degrade
subsequent wafer processing. It is often desirable to create a flat
surface over the patterned material. Several methods have been
developed to create such a flat, or "planarized", surface. Examples
include depositing a conformal layer of material of sufficient
thickness and polishing the wafer to obtain a flat surface,
depositing a conformal layer of material of sufficient thickness
and etching the layer back to form a planarized surface, and
forming a layer of relatively low-melting point material, such as
doped silicon oxide, and then heating the wafer sufficiently to
cause the doped silicon oxide to melt and flow as a liquid,
resulting in a flat surface upon cooling. Each process has
attributes that make that process desirable for a specific
application.
[0004] As semiconductor design has advanced, the feature size of
the semiconductor devices has dramatically decreased. Many circuits
now have features, such as traces or trenches less than a micron
across. While the reduction in feature size has allowed higher
device density, more chips per wafer, more complex circuits, lower
operating power consumption and lower cost among other benefits,
the smaller geometries have also given rise to new problems, or
have resurrected problems that were once solved for larger
geometries.
[0005] An example of the type of manufacturing challenge presented
by sub-micron devices is the ability to completely fill a narrow
trench in a void-free manner. To fill a trench with silicon oxide,
a layer of silicon oxide is first deposited on the patterned
substrate. The silicon oxide layer typically covers the field, as
well as walls and bottom of the trench. If the trench is wide and
shallow, it is relatively easy to completely fill the trench. As
the trench gets narrower and the aspect ratio (the ratio of the
trench height to the trench width) increases, it becomes more
likely that the opening of the trench will "pinch off".
[0006] Pinching off a trench may trap a void within the trench.
FIG. 1 shows such a void 4 formed in the dielectric material 2 that
fills trench 1. These voids commonly occur in gapfill depositions
where dielectric materials are rapidly deposited in high aspect
ratio trenches. Void 4 creates inhomogeneities in the dielectric
strength of the gapfill that can adversely affect the operation of
a semiconductor device.
[0007] One approach to forming fewer voids is to slow down the
dielectric deposition rate. Slower deposition rates facilitate a
more conformal deposition of the dielectric material on the trench
surfaces, which reduces excess buildup of dielectric materials on
the top corners of the trench that can result in pinching off. As a
result, trenches are more evenly filled from the bottom up.
However, lowering the deposition rate of the dielectric material
also reduces process efficiency by increasing the total dielectric
deposition time. The slower dielectric deposition rates not only
increase the time for filling trench 1, but also the bulk
dielectric layer 3 on top of trench 1.
[0008] Another challenge encountered in gap-fill processes is the
formation of weak seams at the interface of the dielectric material
with a trench surface, as well as between surfaces of the
dielectric materials itself. Weak seams can form when the deposited
dielectric materials adhere weakly, or not at all, to the inside
surfaces of a trench. Subsequent process steps (e.g., annealing)
can detach the dielectric material from the trench surface and
create a fissure in the gap-filled trench. Weak seams can also be
formed between dielectric surfaces as illustrated in FIG. 2A, which
shows a weak seam 9 in the middle of trench 5 that has been formed
at the intersection of opposite faces of silicon oxide material 6
growing outward from opposite sidewalls (7a and 7b) of trench
5.
[0009] The dielectric material along seam 9 has a lower density and
higher porosity than other portions of the dielectric material 6,
which can cause an enhanced rate of etching along the seam 9. FIG.
2B illustrates how unwanted dishing 8 can develop along seam 4 when
the dielectric material 6 is exposed to an etchant (e.g., HF)
during processes such as chemical-mechanical polishing (CMP) and
post-CMP cleaning. Like voids, weak seams create inhomogeneities in
the dielectric strength of the gapfill that can adversely affect
the operation of a semiconductor device.
[0010] In some circumstances, voids and weak seams in dielectric
trench fills may be filled in or "healed" using a reflow process.
For example, some doped silicon oxide dielectric materials
experience viscous flow at elevated temperatures, permitting the
reduction of voids and weak seams with high-temperature reflow
processes. However, as the trench becomes narrower, it becomes more
likely that the void will not be filled during these reflow
process. In addition, reflow processes are not practical in many
applications where high melting point dielectrics, such as undoped
silicon oxide, are used for the gapfill. Thus, there remains a need
for new systems and methods to reduce or eliminate voids and weak
seams in dielectric gapfills.
BRIEF SUMMARY OF THE INVENTION
[0011] Embodiments of the invention include a chemical vapor
deposition method for forming a dielectric material in a trench
formed on a substrate. The method includes flowing a
silicon-containing precursor into a process chamber housing the
substrate, flowing an oxidizing gas into the chamber, and providing
a hydroxyl-containing precursor in the process chamber. The method
also includes reacting the silicon-containing precursor, oxidizing
gas and hydroxyl-containing precursor to form the dielectric
material in the trench. The ratio of the silicon-containing
precursor to the oxidizing gas flowed into the chamber is increased
over time to alter a rate of deposition of the dielectric
material.
[0012] Embodiments of the invention also include a chemical vapor
deposition method for forming a dielectric layer on a substrate.
The method includes providing a silicon-containing precursor, an
oxidizing processing gas, and a hydroxyl-containing precursor to a
chamber housing the substrate. These precursors react to form the
dielectric layer on the substrate. The ratio of the
silicon-containing precursor to the oxidizing processing gas flowed
into the chamber may be altered to change the deposition rate of
the dielectric layer. The method may also include annealing the
dielectric layer to increase a density of the dielectric layer.
[0013] Embodiments of the invention further include a substrate
processing apparatus. The apparatus may include a substrate support
configured to support a substrate within a processing chamber, and
a gas delivery system configured to receive a silicon-containing
precursor, a hydroxyl-containing precursor and an oxidizing
processing gas and deliver them to the processing chamber. The
apparatus may further include a controller configured to control
the gas delivery system and the substrate support. The controller
may introduce the silicon-containing precursor, the
hydroxyl-containing precursor and oxidizing processing gas into the
processor chamber to form a dielectric layer on the substrate, and
alter the position of the substrate support relative to the gas
delivery system during the deposition of the dielectric layer.
[0014] Additional embodiments and features are set forth in part in
the description that follows, and in part will become apparent to
those skilled in the art upon examination of the specification or
may be learned by the practice of the invention. The features and
advantages of the invention may be realized and attained by means
of the instrumentalities, combinations, and methods described in
the specification.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 shows a trench filled with a dielectric material that
includes a void;
[0016] FIG. 2A shows a trench filled with a dielectric material
that includes a weak seam;
[0017] FIG. 2B shows the conventional oxide-filled trench of FIG.
2A after a chemical mechanical polishing;
[0018] FIGS. 3A-B are flowcharts illustrating steps that may be
included in processes of forming a dielectric layer on a substrate
according to embodiments of the invention;
[0019] FIGS. 4A-B are simplified graphs plotting the relative
concentration of a silicon-containing components over time
according to embodiments of the invention;
[0020] FIGS. 5A-B are a set of comparative electron micrographs of
gap-filled trenches;
[0021] FIGS. 6A-B are another set of comparative electron
micrographs of gap-filled trenches;
[0022] FIG. 7 is a graph of dielectric film properties versus the
flow rate of water vapor during the deposition of the dielectric
film;
[0023] FIG. 8 shows a simplified cross-sectional view of an
oxide-filled trench in accordance with an embodiment of the present
invention;
[0024] FIG. 9 is a simplified cross section of a portion of an
integrated circuit according to the present invention;
[0025] FIG. 10A is a simplified representation of a CVD apparatus
according to the present invention;
[0026] FIG. 10B is a simplified representation of the user
interface for a CVD system in relation to a deposition chamber in a
multi-chamber system;
[0027] FIG. 10C is a simplified diagram of a gas panel and supply
lines in relation to a deposition chamber; and
[0028] FIG. 10D shows a schematic view of another gas flow system
in accordance with embodiments of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0029] As noted above, the development of voids and weak seams in
trench isolations has become an increasing problem, particularly as
trench widths get smaller (e.g., about 90 nm or less) and trench
aspect ratios get higher (e.g., about 6:1 or higher). The present
invention includes systems and methods of forming dielectric
materials in these trenches using a hydroxyl-containing precursor
(e.g., H.sub.2O, hydrogen peroxide (H.sub.2O.sub.2), etc.) to help
reduce voids and weak seams in the gapfill. The hydroxyl-containing
precursor enhances the flowability and density of the silicon oxide
material, helping to heal weak seams and fill in voids formed
during the deposition.
[0030] Hydroxyl-containing precursors also increase the density of
the silicon oxide material formed in the trench. The higher density
of the material may provide advantages over less dense material,
including giving the material a slower wet etch rate. Less dense
materials deposited in the trenches by, for example, conventional,
moisture free chemical vapor deposition typically have wet etch
rates of about 5:1 or more. The high wet etch rates of the material
can result in the overetching during subsequent planarization
and/or oxide etching processes. This overetching may result in the
formation of bowls or gaps at the tops of the trench
isolations.
[0031] Embodiments of the invention include depositing the
dielectric materials using high aspect ratio processes (HARPs).
These processes include depositing the dielectric material at
different rates in different stages of the process. For example, a
lower deposition rate may be used to form a more conformal
dielectric layer in a trench, while a higher deposition rate is
used to form a bulk dielectric layer above the trench. In other
examples, multiple rates (e.g., 3 or more rates) are used at
various stages of the formation of the dielectric layer. Performing
the deposition at a plurality of dielectric deposition rates
reduces the number of voids and weak seams in the trenches without
significantly reducing the efficiency of the deposition process.
Combining the advantages of HARP with the enhanced flowability and
higher density of dielectric materials formed with
hydroxyl-containing precursors permits the efficient formation of
low defect, high-density dielectric materials in trenches and bulk
dielectric layers.
Exemplary Oxide Deposition Processes
[0032] FIG. 3A is a flowchart that illustrates steps that may be
included in a process of forming a dielectric layer on a substrate
according to embodiments of the invention. These embodiments
include using HARP techniques for varying the deposition rate of
the dielectric materials during the formation of the dielectric
layer. The process includes providing a substrate in a process
chamber at a first distance from the gas distribution manifold
(e.g., showerhead) in step 302. The gas distribution manifold may
include separate inlets for the precursor materials, or a single
inlet through which mixtures of the precursors enter the process
chamber.
[0033] After the substrate is placed in the process chamber, the
precursor materials may flow through the manifold. This may include
flowing an oxidizing gas precursor 306 (e.g., O.sub.2, O.sub.3, NO,
NO.sub.2, mixtures thereof, etc.), a silicon-containing precursor
308 (e.g., silane, dimethylsilane, trimethylsilane,
tetramethylsilane, diethylsilane, tetramethylorthosilicate (TMOS),
tetraethylorthosilicate (TEOS), octamethyltetrasiloxane (OMTS),
octamethylcyclotetrasiloxane (OMCTS), tetramethylcyclotetrasiloxane
(TOMCATS), mixtures thereof, etc.), and a hydroxyl-containing
precursor 310 (e.g., H.sub.2O, H.sub.2O.sub.2, etc.) through the
manifold. Each precursor flows through the manifold and into the
process chamber at an initial flow rate. For example, the
silicon-containing precursor may initially flow through the
manifold at about 20 to about 100 sccm, while the oxidizing
precursor flows at about 60 to about 1000 sccm, and the
hydroxyl-containing precursor flow at about 60 to about 200
sccm.
[0034] Depending on the type of CVD process used, the precursor
materials may first help form a plasma whose products are used to
form the dielectric layer on the substrate. Embodiments of the
invention may be used with plasma CVD techniques such as plasma
enhanced CVD (PECVD), and high density plasma CVD (HDPCVD), as well
as thermal CVD techniques such as atmospheric pressure CVD (APCVD),
sub-atmospheric CVD (SACVD), and low-pressure CVD (LPCVD), among
others.
[0035] The initial flow rates of the precursors establish first
flow rate ratios for the silicon-containing precursor:oxidizing gas
precursor, and the silicon-containing precursor:hydroxyl-containing
precursor. When the initial deposition of dielectric materials
includes trench fills, the ratio of silicon-containing
precursor:oxidizing gas precursor may be relatively low to provide
a slower deposition of dielectric materials in the trenches. As the
deposition progresses, the ratio of silicon-containing
precursor:oxidizing gas precursor may be adjusted in step 312. For
example, once a portion of the trenches has been filled, the ratio
of silicon-containing precursor:oxidizing gas precursor may be
increased to increase the deposition rate of the dielectric
material. The adjustment is made at a stage of the deposition when
there is reduced risk of the higher deposition rate causing voids
or weak seams in the trenches.
[0036] The flow rate ratio of the silicon-containing precursor to
the hydroxyl-containing precursor may also be relatively low in the
initial deposition stage. When the flow rate ratio of
silicon-containing precursor:oxidizing gas precursor is increased,
the ratio of silicon-containing precursor:hydroxyl-containing
precursor may increase as well. Alternatively, the ratio of
silicon-containing precursor:hydroxyl-containing precursor may
remain substantially constant as the ratio of silicon-containing
precursor:oxidizing gas varies, such as embodiments where the
silicon-containing and hydroxyl-containing precursors flow together
into the process chamber.
[0037] FIG. 4A is a simplified graph plotting the concentration of
a silicon-containing gas component relative to a process maximum,
versus time, in an embodiment of a deposition process in accordance
with the present invention featuring a stepped deposition rate
profile. Alternative embodiments in accordance with the present
invention could exhibit a wide variety of changing, non-linear
composition profiles. FIG. 4B is a simplified graph plotting the
concentration of a silicon-containing gas component relative to a
process maximum, versus time, for another alternative embodiment of
a deposition process in accordance with the present invention
featuring a nonlinear profile.
[0038] Changes in composition of process gases flowed during the
dielectric deposition may be accomplished in a variety of ways.
Embodiments of the method have an increasing relative percentage of
the silicon-containing precursor to the overall precursor mixture
flow. Such an increase could be produced by elevating the flow rate
of the silicon-containing precursor, reducing the flow rate of the
oxidizing gas precursor, reducing the flow rate of the
hydroxyl-containing precursor, or any combination of a change in
flow rates of the components of the processing gas mixture which
results in a change in the overall percentage composition of the
silicon-containing precursor.
[0039] Moreover, a change in the relative ratio of components of
the processing gas mixture may be accomplished by other than
changing the flow rates of the components. For example, when ozone
is used as the oxidizing gas precursor, it's frequently formed by
flowing oxygen through an ozone generator, resulting in a gas flow
comprising oxygen and some percentage of ozone. Changes in the
concentration of silicon-containing precursor relative to ozone
(i.e., the oxidizing gas precursor) could also be accomplished by
altering the conditions of generation of the ozone to increase its
concentration, without altering the flow rate of the ozone into the
processing chamber.
[0040] The deposition rate of the dielectric layer may also be
changed by adjusting the distance between the substrate and
manifold to a second distance 314. The process chamber may include
an adjustable lift that can vary the space between the substrate
and the manifold during the deposition. As the substrate moves
closer to the manifold, it enters a zone where the precursor
materials are more concentrated, and form the dielectric layer at a
faster rate. Thus, when the dielectric materials can be deposited
on the substrate at a higher deposition rate without causing voids
or weak seams, the substrate may be moved from an initial first
distance to a second distance that is closer to the process chamber
manifold.
[0041] At the completion of the deposition of the dielectric layer,
the precursor materials stop flowing into the chamber 316.
Additional process steps (e.g., annealing, chemical-mechanical
polishing, etc.) may follow the dielectric deposition, before the
substrate is removed from the process chamber.
[0042] Referring now to FIG. 3B, a flowchart illustrating steps for
forming a dielectric layer on a substrate according to additional
embodiments of the invention is shown. The process includes
providing a substrate in a process chamber in step 301. The
substrate is then heated in step 303 to a temperature at which the
dielectric layer is formed (e.g., about 400.degree. C. or more,
about 450.degree. C. to about 750.degree. C., about 500.degree. C.
to about 600.degree. C., etc.). Heating the substrate facilitates
the chemical vapor deposition of precursor materials into solid,
but flowable dielectric layer having a wet etch rate ratio (WERR)
of about 2.5 or less. When the substrate is not heated, or heated
to lower temperatures (e.g., about 200.degree. C. or less), the
deposited dielectric normally has a spin-on liquid consistency and
has to undergo subsequent heating and/or annealing that can
increase overall deposition time.
[0043] Precursor materials are provided to the heated substrate by
flowing oxidizing gas precursor, silicon-containing precursor, and
hydroxyl-containing precursor to the process chamber in steps 305,
306 and 307. The precursors may be mixed together and flow through
a single channel into the process chamber at a constant flow rate
until the flows are stopped at the end of the deposition 311.
Alternatively, the silicon-containing precursor may flow though a
channel that is independent of the oxidizing gas precursor and/or
hydroxyl-containing precursor, and the flow rates of the precursors
may be independently varied over the course of the deposition. The
timing of the precursor materials may also be varied such that, for
example, the oxidizing gas precursor and/or hydroxyl-containing
precursor may be introduced before the silicon-containing
precursor, or alternatively, all three precursors being introduced
at the same time.
[0044] The dielectric layer formed on the substrate may be annealed
in step 313. The anneal may be performed in the process chamber, or
the substrate may be transferred to a separate annealing chamber.
Exemplary anneal processes that may be used with embodiments of the
invention will now be described.
Exemplary Post-Deposition Anneal Processes
[0045] Following the formation of the dielectric material, a
post-deposition anneal may optionally be performed. The dielectric
material may be annealed in an atmosphere such as N.sub.2,
N.sub.2O, NO or NH.sub.3. In one embodiment, the annealing process
includes heating the substrate and flowing N.sub.2O into the
chamber or furnace. The N.sub.2O interacts with the silicon oxide
material at high temperatures and strengthens any remaining weak
seams. The annealed layer is substantially seam-free and suited for
further treatments such as CMP.
[0046] Annealing may take place in situ or ex situ. For example,
the annealing may take place in the CVD chamber immediately after
the deposition. Annealing alternatively may take place in another
chamber of a multi-chamber system or in a different chamber system
(e.g., a furnace). In some embodiments, annealing comprises a Rapid
Thermal Process (RTP) as more fully described in U.S. Pat. No.
5,660,472, the entire disclosure of which is herein incorporated by
reference for all purposes.
[0047] The annealing temperature may range from about 750.degree.
C. to about 1000.degree. C. for furnace anneal and up to about
1200.degree. C. for RTP anneal. The annealing duration is
temperature dependent and may range from about 10 minutes to around
2 hours for furnace anneal and as few as 5 seconds up to around 3
minutes for RTP. As a result, in most cases, the layer is annealed
by restructuring the SiO.sub.2 network without exceeding the
SiO.sub.2 reflow temperature.
[0048] In other embodiments, the anneal process may include a
multi-step anneal similar to those described in co-assigned U.S.
Prov. Patent App. Ser. No. 60/598,939, titled "MULTISTEP ANNEAL OF
THIN FILMS FOR FILM DENSIFICATION AND IMPROVED GAPFILL," filed Aug.
4, 2004, by Nitin K. Ingle et al., the entire contents of which is
hereby incorporated by reference for all purposes.
EXAMPLES
[0049] In these examples, silicon oxide (SiO.sub.2) dielectric
materials were deposited in substrate trenches using TEOS as the
silicon-containing precursor, ozone as the oxidizing gas precursor
and water vapor as the hydroxyl-containing precursor. The
depositions are performed in a process chamber configured for
thermal CVD.
[0050] Silicon oxide gap-fills were performed according to
embodiments of the methods of the invention and comparative
examples using conventional gap-fill techniques were also run.
FIGS. 5A-B show electron micrographs of trenches filled with
silicon oxide dielectric materials. The trenches had a width of
about 0.15 .mu.m and an aspect ratio (height/width) of about 6:1.
FIG. 5A shows an electron micrograph of trenches filled with a
silicon oxide dielectric using a conventional gap-fill technique.
The conventional technique included a thermal CVD deposition at
540.degree. C. using TEOS as the silicon-containing precursor
flowing at about 5000 milligrams per minute (mgm). No
hydroxyl-containing precursor is introduced during the deposition.
An anneal is performed following the deposition for 30 minutes at
1050.degree. C. in a nitrogen (N.sub.2) atmosphere. The spots in
the middle of the filled trenches and blurred lines around the
edges of the trench in FIG. 5A show extensive formation of voids
and weak seams.
[0051] In comparison, FIG. 5B shows an electron micrograph of
trenches filled with a silicon oxide dielectric according to an
embodiment of the methods of the present invention. During the
deposition, 2500 mgm of H.sub.2O was introduced with the TEOS.
Other deposition conditions were substantially the same as for the
conventional deposition described above for FIG. 5A. The micrograph
in FIG. 5B lacks the spots and blurry trench edges indicative of
the voids and weak seams seen in the gap-filled trenches of FIG.
5A.
[0052] Referring now to FIGS. 6A-B another pair of electron
micrographs of trenches filled with silicon oxide dielectric
materials are shown. Similar to FIGS. 6A-B, the trenches had a
width of about 0.15 .mu.m and an aspect ratio (height/width) of
about 6:1. FIG. 6A shows an electron micrograph of trenches filled
with a silicon oxide dielectric using a conventional gap-fill
technique. The conventional technique included a thermal CVD
deposition at 540.degree. C. using TEOS as the silicon-containing
precursor flowing at about 5000 milligrams per minute (mgm). The
elongated spots in the middle of the filled trenches in FIG. 6A
show extensive formation of voids.
[0053] In comparison, FIG. 6B shows an electron micrograph of
trenches filled with a silicon oxide dielectric according to an
embodiment of the methods of the present invention. During the
deposition, 10 grams/minute of H.sub.2O was introduced with the
TEOS. Other deposition conditions were substantially the same as
for the conventional deposition described above for FIG. 6A. The
micrograph in FIG. 6B does not show any evidence of the elongated
spots seen in FIG. 6A.
[0054] FIG. 7 shows a graph of the wet etch rate ratio (WERR) and
percent shrinkage of the silicon oxide films as a function of water
vapor flow rate (in grams/minute) during film deposition. The graph
shows that the WERR decreases with increasing water vapor flow rate
for depositions at both 850.degree. C. and 1050.degree. C. Also,
the graph shows for the 850.degree. C. deposition that there is a
smaller % shrinkage following a post-deposition anneal as the water
vapor flow rate increases. The drop in % shrinkage is particularly
notable when going from a moisture-free deposition (i.e., 0 gm/min
H.sub.2O) to a deposition that includes some water vapor (i.e., 5
gm/min H.sub.2O).
Exemplary Semiconductor Structure
[0055] FIG. 8 shows a simplified cross-sectional view of an
oxide-filled trench structure formed utilizing an embodiment of a
process in accordance with the present invention. Specifically, the
time-varied flow rate ratio of silicon-containing
precursor:oxidizing gas precursor during the deposition process
results in formation of an oxide film 800 that includes a highly
conformal portion 800a proximate to the surrounding silicon
sidewalls, but which also includes a less-conformal body portion
800b which fills the entire volume of the trench 802 and creates
overlying bulk layer 804 in a reasonable period of time. The
oxide-filled trench 802 of FIG. 8 does not include the voids or
weak seams associated with similar features formed utilizing the
conventional oxide CVD processes previously described.
[0056] Trenches like the ones shown in FIG. 8 may be used in
shallow trench isolation structures like those shown in FIG. 9,
which illustrates simplified cross-section of an integrated circuit
200 according to embodiments of the invention. As shown in FIG. 9,
the integrated circuit 200 includes NMOS and PMOS transistors 203
and 206, which are separated and electrically isolated from each
other by oxide-filled trench isolation structure 220.
Alternatively, field oxide isolation can be used to isolate
devices, or a combination of isolation techniques may be used. Each
of the transistors 203 and 206 comprises a source region 212, a
gate region 215, and a drain region 218.
[0057] A premetal dielectric (PMD) layer 221 separates the
transistors 203 and 206 from the metal layer 240, with connections
between metal layer 240 and the transistors made by contacts 224.
The premetal dielectric layer 221 may comprise a single layer or
multiple layers. The metal layer 240 is one of four metal layers,
240, 242, 244, and 246, included in the integrated circuit 200.
Each metal layer is separated from adjacent metal layers by
intermetal dielectric layers 227, 228, and 229. Adjacent metal
layers are connected at selected openings by vias 226. Planarized
passivation layers 230 are deposited over the metal layer 246.
[0058] A silicon oxide layer according to the present invention may
be used to form one or more of the dielectric layers shown in
integrated circuit 200. For example, a silicon oxide layer
deposited according to the present invention may be used to create
trench isolation structure 220. A silicon oxide layer deposited
according to the present invention may also be used to create PMD
layer 221, or the higher layer intermetal dielectric layers 227-229
of the overlying interconnect structure.
[0059] A silicon oxide layer according to the present invention may
also be used in damascene layers, which are included in some
integrated circuits. In damascene layers, a blanket layer is
deposited over a substrate, selectively etched through to the
substrate, and then filled with metal and etched back or polished
to form metal contacts 224. After the metal layer is deposited, a
second blanket deposition is performed and selectively etched. The
etched areas are then filled with metal and etched back or polished
to form vias 226.
[0060] It should be understood that the simplified integrated
circuit 200 is for illustrative purposes only. One of ordinary
skill in the art could implement the present method for fabrication
of other integrated circuits, such as microprocessors,
application-specific integrated circuits (ASICs), memory devices,
and the like.
Exemplary Deposition System
[0061] FIG. 10A is a simplified diagram of a chemical vapor
deposition ("CVD") system 10 according to embodiments of the
invention. This system is suitable for performing thermal,
sub-atmospheric CVD ("SACVD") processes, as well as other
processes, such as reflow, drive-in, cleaning, etching, and
gettering processes. Multiple-step processes can also be performed
on a single substrate or wafer without removing the substrate from
the chamber. The major components of the system include, among
others, a vacuum chamber 15 that receives process and other gases
from a gas delivery system 89, a vacuum system 88, a remote
microwave plasma system 55, and a control system 53. These and
other components are described below in order to understand the
present invention.
[0062] The CVD apparatus 10 includes an enclosure assembly 102
housing a vacuum chamber 15 with a gas reaction area 16. A gas
distribution plate 20 is provided above the gas reaction area 16
for dispersing reactive gases and other gases, such as purge gases,
through perforated holes in the gas distribution plate 20 to a
wafer (not shown) that rests on a vertically movable heater 25
(also referred to as a wafer support pedestal). The heater 25 can
be controllably moved between a lower position, where a wafer can
be loaded or unloaded, for example, and a processing position
closely adjacent to the gas distribution plate 20, indicated by a
dashed line 13, or to other positions for other purposes, such as
for an etch or cleaning process. A center board (not shown)
includes sensors for providing information on the position of the
wafer.
[0063] The heater 25 includes an electrically resistive heating
element (not shown) enclosed in a ceramic. The ceramic protects the
heating element from potentially corrosive chamber environments and
allows the heater to attain temperatures up to about 800.degree. C.
In an exemplary embodiment, all surfaces of the heater 25 exposed
to the vacuum chamber 15 are made of a ceramic material, such as
aluminum oxide (Al.sub.2O.sub.3 or alumina) or aluminum
nitride.
[0064] Reactive and carrier gases are supplied through the supply
line 43 into a gas mixing box (also called a gas mixing block) 273,
where they are preferably mixed together and delivered to the gas
distribution plate 20. For example, silicon-containing precursor,
such as silane, dimethylsilane, trimethylsilane, tetramethylsilane,
diethylsilane, tetramethylorthosilicate (TMOS),
tetraethylorthosilicate (TEOS), octamethyltetrasiloxane (OMTS),
octamethylcyclotetrasiloxane (OMCTS), tetramethylcyclotetrasiloxane
(TOMCATS), or mixtures thereof may be supplied to supply line 43
along with an oxide gas, such as oxygen (O.sub.2), ozone (O.sub.3),
NO, NO.sub.2, or mixtures thereof, and a hydroxyl-containing
precursors such as H.sub.2O, hydrogen peroxide, or mixtures
thereof.
[0065] In alternate embodiments, the hydroxyl-containing precursor
may be generated by combustion reactions that occur in (or near)
vacuum chamber 15. For example, the hydroxyl-containing precursor
may be in-situ generated steam (ISSG) that is generated by the
combustion of hydrogen (H.sub.2) and oxygen (O.sub.2) in or near
vacuum chamber 15 to form water vapor.
[0066] The gas mixing box 273 is preferably a dual input mixing
block coupled to a process gas supply line 43 and to a
cleaning/etch gas conduit 47. A valve 280 operates to admit or seal
gas or plasma from the gas conduit 47 to the gas mixing block 273.
The gas conduit 47 receives gases from an integral remote microwave
plasma system 55, which has an inlet 57 for receiving input gases.
During deposition processing, gas supplied to the plate 20 is
vented toward the wafer surface (as indicated by arrows 21), where
it may be uniformly distributed radially across the wafer surface,
typically in a laminar flow.
[0067] Purging gas may be delivered into the vacuum chamber 15 from
the plate 20 and/or an inlet port or tube (not shown) through the
bottom wall of enclosure assembly 102. The purging gas flows upward
from the inlet port past the heater 25 and to an annular pumping
channel 40. An exhaust system then exhausts the gas (as indicated
by arrows 22) into the annular pumping channel 40 and through an
exhaust line 60 to a vacuum system 88, which includes a vacuum pump
(not shown). Exhaust gases and entrained particles are drawn from
the annular pumping channel 40 through the exhaust line 60 at a
rate controlled by a throttle valve system 63.
[0068] In other embodiments (not shown) the silicon-containing
precursors and the hydroxyl-containing precursors may travel
through separate supply lines to a gas distribution plate in order
to prevent them from reacting prematurely before reaching the
substrate. As example of the dual channel supply line and
showerhead design is described in co-assigned U.S. Pat. No.
6,624,091, titled "METHODS OF FORMING GAP FILL AND LAYERS FORMED
THEREBY," filed May 7, 2001, the entire contents of which is hereby
incorporated by this reference for all purposes.
[0069] The remote microwave plasma system 55 can produce a plasma
for selected applications, such as chamber cleaning or etching
native oxide or residue from a process wafer. Plasma species
produced in the remote plasma system 55 from precursors supplied
via the input line 57 are sent via the conduit 47 for dispersion
through the plate 20 to the vacuum chamber 15. Precursor gases for
a cleaning application may include fluorine, chlorine, and other
reactive elements. The remote microwave plasma system 55 also may
be adapted to deposit plasma-enhanced CVD films by selecting
appropriate deposition precursor gases for use in the remote
microwave plasma system 55.
[0070] The system controller 53 controls activities and operating
parameters of the deposition system. The processor 50 executes
system control software, such as a computer program stored in a
memory 70 coupled to the processor 50. Preferably, the memory 70
may be a hard disk drive, but of course the memory 70 may be other
kinds of memory, such as read-only memory or flash memory. In
addition to a hard disk drive (e.g., memory 70), the CVD apparatus
10 in a preferred embodiment includes a floppy disk drive and a
card rack (not shown).
[0071] The processor 50 operates according to system control
software, which includes sets of instructions that dictate the
timing, mixture of gases, chamber pressure, chamber temperature,
microwave power levels, susceptor position, and other parameters of
a particular process. Other computer programs such as those stored
on other memory including, for example, a floppy disk or another
computer program product inserted in a disk drive or other
appropriate drive, may also be used to operate the processor 50 to
configure the CVD system 10 into various apparatus.
[0072] The processor 50 has a card rack (not shown) that contains a
single-board computer, analog and digital input/output boards,
interface boards and stepper motor controller boards. Various parts
of the CVD system 10 conform to the Versa Modular European (VME)
standard which defines board, card cage, and connector dimensions
and types. The VME standard also defines the bus structure having a
16-bit data bus and 24-bit address bus.
[0073] FIG. 10B is a simplified diagram of a user interface in
relation to the CVD apparatus chamber 30. The CVD apparatus 10
includes one chamber of a multichamber system. Wafers may be
transferred from one chamber to another for additional processing.
In some cases the wafers are transferred under vacuum or a selected
gas. The interface between a user and the processor is via a CRT
monitor 73a and a light pen 73b. A mainframe unit 75 provides
electrical, plumbing, and other support functions for the CVD
apparatus 10. Exemplary mainframe units compatible with the
illustrative embodiment of the CVD apparatus are currently
commercially available as the PRECISION 5000.TM., the CENTURA
5200.TM., and the PRODUCER SE.TM. systems from APPLIED MATERIALS,
INC. of Santa Clara, Calif.
[0074] In the preferred embodiment two monitors 73a are used, one
mounted in the clean room wall 71 for the operators, and the other
behind the wall 72 for the service technicians. Both monitors 73a
simultaneously display the same information, but only one light pen
73b is enabled. The light pen 73b detects light emitted by the CRT
display with a light sensor in the tip of the pen. To select a
particular screen or function, the operator touches a designated
area of the display screen and pushes the button on the pen 73b.
The touched area changes its highlighted color, or a new menu or
screen is displayed, confirming communication between the light pen
and the display screen. Of course, other devices, such as a
keyboard, mouse, or other pointing or communication device, may be
used instead of or in addition to the light pen 73b to allow the
user to communicate with the processor.
[0075] FIG. 10C illustrates a general overview of an embodiment of
the CVD apparatus 10 in relation to a gas supply panel 80 located
in a clean room. As discussed above, the CVD system 10 includes a
chamber 15 with a heater 25, a gas mixing box 273 with inputs from
an inlet tube 43 and a conduit 47, and remote microwave plasma
system 55 with input line 57. As mentioned above, the gas mixing
box 273 is for mixing and injecting deposition gas(es) and clean
gas(es) or other gas(es) through the inlet tube 43 to the
processing chamber 15.
[0076] The remote microwave plasma system 55 is integrally located
and mounted below the chamber 15 with the conduit 47 coming up
alongside the chamber 15 to the gate valve 280 and the gas mixing
box 273, located above the chamber 15. Microwave generator 110 and
ozonator 115 are located remote from the clean room. Supply lines
83 and 85 from the gas supply panel 80 provide reactive gases to
the gas supply line 43. The gas supply panel 80 includes lines from
gas or liquid sources 90 that provide the process gases for the
selected application. The gas supply panel 80 has a mixing system
93 that mixes selected gases before flow to the gas mixing box 273.
In some embodiments, gas mixing system 93 includes a liquid
injection system for vaporizing reactant liquids including
silicon-containing precursors such as tetramethylorthosilicate
("TMOS"), tetraethylorthosilicate ("TEOS"), octamethyltetrasiloxane
(OMTS), octamethylcyclotetrasiloxane (OMCTS),
tetramethylcyclotetrasiloxane (TOMCATS), hydroxyl-containing
precursors such as water, and hydrogen peroxide, and dopants such
as triethylborate ("TEB"), triethylphosphate ("TEPO") and diborane
(B.sub.2H.sub.6). Vapor from the liquids is usually combined with a
carrier gas, such as helium. Supply lines for the process gases may
include (i) shut-off valves 95 that can be used to automatically or
manually shut off the flow of process gas into line 85 or line 57,
and (ii) liquid flow meters (LFM) 100 or other types of controllers
that measure the flow of gas or liquid through the supply
lines.
[0077] As an example, a mixture including TEOS as a silicon source
may be used with gas mixing system 93 in a deposition process for
forming a silicon oxide film. The TEPO is a liquid source that may
be vaporized by conventional boiler-type or bubbler-type hot boxes.
However, a liquid injection system is preferred as it provides
greater control of the volume of reactant liquid introduced into
the gas mixing system. The liquid is typically injected as a fine
spray or mist into the carrier gas flow before being delivered to a
heated gas delivery line 85 to the gas mixing block and chamber.
One or more sources, such as oxygen (O.sub.2), ozone (O.sub.3), NO
or NO.sub.2 flow to the chamber through another gas delivery line
83, to be combined with the reactant gases from heated gas delivery
line 85 near or in the chamber. Of course, it is recognized that
other sources of dopants, silicon, and oxygen also may be used.
[0078] FIG. 10D is a simplified schematic diagram of a CVD
deposition apparatus for depositing oxide layers in accordance with
embodiments of the present invention. While the apparatus may be
used to deposit silicon oxide films, it may also beneficially be
applied to single- or multiple-layer doped silicon glass films,
such as borophosphosilicate glass ("BPSG"), phosphosilicate glass
("PSG"), borosilicate glass ("BSG"), arsenic-silicon glass
("AsSG"), or similar films.
[0079] CVD deposition apparatus 400 comprises oxidizing gas source
416 and hydroxyl containing precursor source 417 in fluid
communication with vacuum chamber 15 through gas mixing box 273.
The oxidizing gas source 416 may contain oxygen (O.sub.2), ozone
(O.sub.3), NO, NO.sub.2, and mixtures of these gases, among other
oxidizing gases. The hydroxyl containing precursor source 417 may
contain H.sub.2O, hydrogen peroxide (H.sub.2O.sub.2), and mixtures
thereof, among other hydroxyl containing precursors. The hydroxyl
containing precursors and oxidizing gases may be stored in sources
416 and 417 as liquids and/or gases.
[0080] Carrier gas source 410, silicon-containing gas source 411,
first dopant gas (e.g., TEPO) source 412, and second dopant gas
(e.g., TEB) source 413 are in fluid communication with vacuum
chamber 15 through select valve 414 gas mixing system 93, and gas
mixing box 273. Select valve 414 is selectively operable to shunt
silicon- and dopant-containing gases such as TEOS vapor through
divert line 402 to foreline 408 of chamber exhaust system 88,
thereby circumventing vacuum chamber 15 entirely. Select valve 414
and divert line 402 allow the flow of silicon-containing gas to
stabilize prior to its being routed to the vacuum chamber to
commence an oxide CVD step in accordance with an embodiment of the
present invention.
[0081] As noted above, the systems and methods of the invention may
also be implemented on plasma based chemical vapor deposition
systems. For example, the present invention may be used with plasma
systems like the one described in commonly assigned U.S. Pat. No.
6,734,155, titled "PLASMA PROCESSES FOR DEPOSITING LOW DIELECTRIC
CONSTANT FILMS," filed Aug. 27, 2002, and HDP-CVD systems like the
one described in commonly-assigned U.S. Pat. No. 6,740,601, titled
"HDP-CVD DEPOSITION PROCESSES FOR FILLING HIGH ASPECT RATIO GAPS,"
filed May 11, 2001, the entire contents of both patents being
hereby incorporated by reference for all purposes.
[0082] While the above is a complete description of specific
embodiments of the present invention, various modifications,
variations, and alternatives may be employed. Alternative
embodiments of process recipes in accordance with the present
invention could call for flowing the silicon-containing component
of the process gas flow at a sufficiently high initial
concentration to allow the process gases to be introduced directly
into the chamber, without an initial flow diversion phase.
[0083] Moreover, other techniques for varying the parameters of
deposition of an oxide layer could be employed in conjunction with
the variation in concentration of the process gas flow components
described so far. Examples of other possible parameters to be
varied include but are not limited to the temperature of
deposition, the pressure of deposition, and the flow rate of
processing gases containing dopants such as arsenic (As), boron
(B), and phosphorous (P).
[0084] Having described several embodiments, it will be recognized
by those of skill in the art that various modifications,
alternative constructions, and equivalents may be used without
departing from the spirit of the invention. Additionally, a number
of well known processes and elements have not been described in
order to avoid unnecessarily obscuring the present invention.
Accordingly, the above description should not be taken as limiting
the scope of the invention.
[0085] Where a range of values is provided, it is understood that
each intervening value, to the tenth of the unit of the lower limit
unless the context clearly dictates otherwise, between the upper
and lower limits of that range is also specifically disclosed. Each
smaller range between any stated value or intervening value in a
stated range and any other stated or intervening value in that
stated range is encompassed within the invention. The upper and
lower limits of these smaller ranges may independently be included
or excluded in the range, and each range where either, neither or
both limits are included in the smaller ranges is also encompassed
within the invention, subject to any specifically excluded limit in
the stated range. Where the stated range includes one or both of
the limits, ranges excluding either or both of those included
limits are also included in the invention.
[0086] As used herein and in the appended claims, the singular
forms "a", "and", and "the" include plural referents unless the
context clearly dictates otherwise. Thus, for example, reference to
"a process" includes a plurality of such processes and reference to
"the electrode" includes reference to one or more electrodes and
equivalents thereof known to those skilled in the art, and so
forth.
[0087] Also, the words "comprise," "comprising," "include,"
"including," and "includes" when used in this specification and in
the following claims are intended to specify the presence of stated
features, integers, components, or steps, but they do not preclude
the presence or addition of one or more other features, integers,
components, steps, or groups.
* * * * *