U.S. patent application number 11/862632 was filed with the patent office on 2008-01-24 for one mask high density capacitor for integrated circuits.
This patent application is currently assigned to Texas Instruments Incorporated. Invention is credited to Edmund Burke, Satyavolu S. Papa Rao, Timothy A. Rost.
Application Number | 20080020538 11/862632 |
Document ID | / |
Family ID | 34550192 |
Filed Date | 2008-01-24 |
United States Patent
Application |
20080020538 |
Kind Code |
A1 |
Rost; Timothy A. ; et
al. |
January 24, 2008 |
One Mask High Density Capacitor for Integrated Circuits
Abstract
An on-chip decoupling capacitor (106) and method of fabrication.
The decoupling capacitor (104) is integrated at the top metal
interconnect level (104) and may be implemented with only one
additional masking layer. The decoupling capacitor (106) is formed
on a copper interconnect line (104a). An aluminum cap layer (118)
provides electrical connection to the top electrode (112) of the
decoupling capacitor (106).
Inventors: |
Rost; Timothy A.; (Plano,
TX) ; Burke; Edmund; (Dallas, TX) ; Papa Rao;
Satyavolu S.; (Garland, TX) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
US
|
Assignee: |
Texas Instruments
Incorporated
Dallas
TX
|
Family ID: |
34550192 |
Appl. No.: |
11/862632 |
Filed: |
September 27, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10696816 |
Oct 30, 2003 |
7291897 |
|
|
11862632 |
Sep 27, 2007 |
|
|
|
Current U.S.
Class: |
438/381 ;
257/E21.008; 257/E21.09 |
Current CPC
Class: |
H01L 23/5223 20130101;
H01L 2924/0002 20130101; H01L 2924/0002 20130101; H01L 28/40
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
438/381 ;
257/E21.09 |
International
Class: |
H01L 21/20 20060101
H01L021/20 |
Claims
1-10. (canceled)
11. A method of fabricating an integrated circuit comprising the
steps of: providing a semiconductor body having a plurality of
metal interconnect levels formed thereon, a topmost one of said
plurality of metal interconnect levels having a first and a second
metal interconnect line; and forming a decoupling capacitor over
said topmost one of said plurality of metal interconnect
levels.
12. The method of claim 11, wherein a bottom electrode of said
decoupling capacitor is electrically connected to said first metal
interconnect line.
13. The method of claim 11, further comprising the step of forming
a metal capping layer over said topmost one of said plurality of
metal interconnect levels and said decoupling capacitor, wherein
said metal capping layer electrically connects a top electrode of
said decoupling capacitor to said second metal interconnect
line.
14. The method of claim 11, wherein said step of forming said
decoupling capacitor comprises the steps of: forming a bottom
electrode material over said topmost one of said plurality of metal
interconnect levels; forming a capacitor dielectric over said
bottom electrode material; and forming a top electrode material
over said capacitor dielectric.
15. The method of claim 14, wherein said top electrode comprises
TaN, said capacitor dielectric comprises tantalum-oxide, and said
bottom electrode comprises TaN.
16. The method of claim 14, wherein said step of forming a
capacitor dielectric comprises the steps of: depositing a layer of
tantalum-oxide over said bottom electrode; and annealing said layer
of tantalum-oxide in oxygen to reduce impurities and increase the
oxygen content.
17. A method of fabricating an integrated circuit comprising the
steps of: providing a semiconductor body having a plurality of
copper interconnect levels formed therein, a topmost one of said
plurality of copper interconnect levels having a first and a second
copper interconnect line; forming a bottom electrode material over
said topmost one of said plurality of copper interconnect levels,
said bottom electrode in direct contact with said first copper
interconnect level; forming a capacitor dielectric over said bottom
electrode material; forming a top electrode material over said
capacitor dielectric; patterning and etching the capacitor stack
forming an aluminum cap layer over said topmost one of said
plurality of copper interconnect levels and said top electrode,
wherein said aluminum cap layer electrically connects said top
electrode to said second copper interconnect line.
18. The method of claim 17, wherein said top electrode comprises
TaN, said capacitor dielectric comprises tantalum-oxide, and said
bottom electrode comprises TaN.
19. The method of claim 17, wherein said step of forming a
capacitor dielectric comprises the steps of: depositing a layer of
tantalum-oxide over said bottom electrode; and annealing said layer
of tantalum-oxide in oxygen.
20. The method of claim 17, wherein said top and bottom electrodes
each comprise one or more layers of material selected from the
group consisting of TaN, TiN, Ir, Ru, and Ta.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The following co-pending patent applications are related and
hereby incorporated by reference:
[0002] U.S. patent application Ser. No. (TI-35260), ______ filed to
Burke et al.
[0003] U S. patent application Ser. No. (TI-36382), ______ filed to
Papa Rao et al.
FIELD OF THE INVENTION
[0004] The invention is generally related to the field of forming
capacitors in semiconductor devices and more specifically to
forming high density capacitors at the top metal interconnect
level.
BACKGROUND OF THE INVENTION
[0005] As semiconductor technology continues to scale, the supply
or operating voltage of the integrated circuit becomes lower and
lower. The nominal supply voltage has decreased from 5V to 3.3V to
1.8V and below. Transistors with operating voltages of 1.1V are
currently being developed.
[0006] As the supply voltage decreases it becomes increasingly
important to limit the voltage swing on the supply voltage lines.
This is due to the fact that smaller voltage swings can cause
unacceptable amounts or current leakage and even unintentionally
switch the state of the transistor. Voltage swing may be minimized
by providing capacitance on the power supply. Typically this is
accomplished with off-chip decoupling capacitors. As the amount of
voltage swing that can be tolerated is reduced, more and more
decoupling capacitance is required.
SUMMARY OF THE INVENTION
[0007] The invention is an on-chip decoupling capacitor and method
of fabrication. The decoupling capacitor is integrated at the top
metal interconnect level and may be implemented with only one
additional masking layer.
[0008] An advantage of the invention is providing on-chip
decoupling capacitance.
[0009] This and other advantages will be apparent to those of
ordinary skill in the art having reference to the specification in
conjunction with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] In the drawings:
[0011] FIG. 1 is a cross-sectional diagram of a high density
capacitor according to an embodiment of the invention.
[0012] FIGS. 2A-2G are cross-sectional diagrams of the high density
capacitor of FIG. 1 at various stages of fabrication.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0013] The invention will now be described in conjunction with
copper damascene process utilizing an aluminum cap layer. Those of
ordinary skill in the art will appreciate that the benefits of the
invention can be applied to other metal interconnect processes.
[0014] As semiconductor devices continue to scale, the decoupling
capacitance requirements increase significantly. The parasitic
resistance of off-chip capacitance can result in performance
penalties. Placing the decoupling capacitors on-chip can reduce or
even avoid these performance penalties. However, integrating the
decoupling capacitors on-chip can cause other concerns. For
example, using a gate oxide capacitor (in which a MOSFET gate oxide
layer is also used as the capacitor dielectric) consumes active
area. There are also leakage concerns with gate oxide capacitors.
Adding a capacitor between contact and M1 (the first level of metal
interconnect) adds a mask, may require routing restrictions above
the capacitor and causes planarity and thermal budget concerns.
Adding a capacitor between metal interconnect lines also causes
planarity and thermal budget concerns.
[0015] To alleviate some of these concerns, the preferred
embodiment of the invention incorporates a high density capacitor
at the top metal interconnect level. The top metal interconnect
level is generally used for routing power and ground lines. As
such, the interconnect routing is not as dense as the lower metal
interconnect levels and there is more space available for forming
the decoupling capacitors. Furthermore, since it is the uppermost
interconnect level. planarity is not as much of a concern. Thermal
budget is also less of a concern because there are fewer remaining
steps and those steps remaining are generally performed at lower
temperatures.
[0016] A preferred embodiment of the invention is shown in FIG. 1.
A high density capacitor 106 is formed above the top metal
interconnect 104 between the top metal interconnect 104 and the
aluminum cap layer 118. Aluminum cap layer 118 provides a bonding
surface which offers better adhesion for ball bonds, bond wires,
etc. than copper. Bonding typically occurs during packaging of the
integrated circuit to provide connection to the semiconductor
device. So, while the aluminum cap layer is metal, it is not
considered a metal interconnect level, but merely a capping layer
to provide better connection during packaging to the top metal
interconnect level 104.
[0017] Top metal interconnect level 104 is formed over
semiconductor body 102. Semiconductor body 102 comprises a
semiconductor substrate, transistors and other devices, as well as
other metal interconnect levels. Only the top metal interconnect
level 104 is shown for simplicity. In this embodiment, the top
metal interconnect level 104 comprises copper interconnect lines
104a, 104b with appropriate barrier layers.
[0018] High density capacitor 106 comprises a bottom electrode 108,
capacitor dielectric 110, and top electrode 112. The top 112 and
bottom 108 electrodes comprise an electrically conductive material.
In the preferred embodiment, TaN is used. TaN is often used as a
barrier in copper interconnects and offers good compatibility with
copper processes. Other electrically conductive materials, such as
TiN, Ir, Ru, Ta and sandwiches/multi-layer combinations thereof may
alternatively be used. Although TaN is used for both he top and
bottom electrodes in the preferred embodiment, different materials
may in fact be used for the top and bottom electrodes. The
capacitor dielectric 110 preferably comprises a high dielectric
constant dielectric. In the preferred embodiment, tantalum-oxide is
used. Other high-k dielectrics such as hafnium oxide may
alternatively be used. While high-k dielectrics are preferred, less
high-k materials such as SiN can alternatively be used.
[0019] The high density capacitor 106 is located over first copper
interconnect line 104a such that first copper interconnect line
104a is electrically connected to the bottom electrode 108.
Connection to the top electrode 112 is made via aluminum cap layer
118. A portion of the aluminum cap layer 118 is electrically
connected between the top electrode 112 and a second copper
interconnect line 104b. So, for example, first copper interconnect
line 104a may be designed as power supply line for which capacitive
decoupling is desired and second copper interconnect line 104b may
be designed as a ground line.
[0020] A method for fabricating the decoupling capacitor of FIG. 1
will now be discussed with reference to FIGS. 2A-2G. A
semiconductor body 102 is processed through the formation of top
metal interconnect level 104, as shown in FIG. 2A. Semiconductor
body 102 comprises a semiconductor (e.g., silicon) substrate,
transistors, and other devices as well as one or more metal
interconnect levels. Only the top metal interconnect level 104 is
shown for simplicity. The top metal interconnect level 104 may be
formed by depositing an etchstop layer 122 (e.g., SiN or SiC),
depositing a low-k dielectric layer 124 (e.g., organo-silicate
glass or fluorine-doped silicon-oxide glass) and depositing an
optional hardmask 126. A trench is etched in the low-k dielectric
layer 124 and then a barrier layer (e.g., Ta/TaN) and copper seed
layer are deposited over the surface. Copper ECD (electro-chemical
deposition) may then be used to overfill the trench with copper.
Finally, copper CMP (chemical-mechanical polish) s performed to
planarize the surface and remove the excess copper and barrier
materials, resulting in the structure of FIG. 2A.
[0021] Referring to FIG. 2B, a bottom electrode material 108 is
deposited over the surface of metal interconnect level 104. Bottom
electrode material 108 comprises an electrically conductive
material. Preferably, bottom electrode material 108 comprises a
material that also acts as a diffusion barrier to cooper to prevent
copper from diffusing out from copper interconnect lines 104a,
104b. In the preferred embodiment, bottom electrode material 108
comprises TaN. Suitable materials include TaN, TiN, Ir, Ru, Ta, and
sandwiches/multi-layer combinations thereof. For example, instead
of entirely comprising a copper diffusion barrier, the bottom
electrode may instead comprise bilayers in which only one of the
layers comprises a copper diffusion barrier. Specifically, the
bottom electrode may comprise a TaN layer with a TiN layer as the
dielectric interface.
[0022] Next, a capacitor dielectric 110 is formed over bottom
electrode layer 108. Preferably, capacitor dielectric 110 comprises
a high dielectric constant material such as tantalum-oxide. A high
dielectric constant material allows for a larger capacitance value
to be formed in a smaller area. Other high-k dielectric materials
such as hafnium oxide or less high-k dielectrics such as SiN may
alternatively be used. In the preferred embodiment, a layer of
tantalum-oxide 130 is deposited over bottom electrode material 108,
as shown in FIG. 2B. The layer of tantalum-oxide 130 is then
annealed in O.sub.2 to reduce impurities in the tantalum-oxide 130
and increase the oxygen content, thus forming the capacitor
dielectric 110 in FIG. 2C.
[0023] Still referring to FIG. 2C, the top electrode material 112
is deposited over the capacitor dielectric 110. The top electrode
material 112 comprises an electrically conductive material and may
comprise the same or a different material than bottom electrode
material 108. In the preferred embodiment top electrode material
112 comprises TaN.
[0024] Next, a pattern 132 is formed over top electrode material
112, as shown in FIG. 2D. Pattern 132 covers the area where
decoupling capacitors are desired. Top electrode material 112,
capacitor dielectric 110 and bottom electrode material 108 are then
etched, using pattern 132 to create high density capacitor 106. An
etch that can etch the bottom electrode selectively with respect to
the copper of copper interconnect liner 104b should be selected.
For example, the etch chemistry may comprise fluorocarbon and argon
gas mixtures. Pattern 132 is then removed.
[0025] Referring to FIG. 2E, the protective overcoat 116 is
deposited. In the preferred embodiment, a layer of SiN 114 is first
deposited over the surface followed by the deposition of the
protective overcoat 116. For example, protective overcoat 116 may
comprise a silicon-oxynitride or oxide layer. Protective overcoat
116 and SiN 114 are then patterned and etched to expose a portion
of copper interconnect line 104b and a portion of top electrode 114
as well as all other areas of the device where external connections
are desired (i.e., bondpad areas).
[0026] Referring to FIG. 2F, a metal capping layer 118 is deposited
over the structure. Typically, metal capping layer 118 comprises
aluminum to improve adhesion of the bond wires typically applied
during packaging. Metal capping layer 118 is patterned and etched
to provide individual caps (i.e. unconnected) for each bondpad, as
is known in the art. However, where decoupling capacitors are
placed, metal capping layer 118 connects between the top electrode
112 and a neighboring copper interconnect line 104b. FIG. 2G, shows
a third copper interconnect line 104c having a standard metal cap
134.
[0027] Processing then continues to package the semiconductor
devices. During packaging, ball bonds and other bonding methods are
used to connect the bondpads of a semiconductor device to the
external pins of the integrated circuit.
[0028] While this invention has been described with reference to
illustrative embodiments, this description is not intended to be
construed in a limiting sense. Various modifications and
combinations of the illustrative embodiments, as well as other
embodiments of the invention, will be apparent to persons skilled
in the art upon reference to the description. It is therefore
intended that the appended claims encompass any such modifications
or embodiments.
* * * * *