U.S. patent application number 11/585088 was filed with the patent office on 2007-10-25 for wafer level semiconductor module and method for manufacturing the same.
This patent application is currently assigned to Samsung Electronics Co. Ltd.. Invention is credited to Seung-Duk Baek, Hyun-Soo Chung, Seong-Deok Hwang, Dong-Hyeon Jang, Dong-Ho Lee.
Application Number | 20070246826 11/585088 |
Document ID | / |
Family ID | 38160887 |
Filed Date | 2007-10-25 |
United States Patent
Application |
20070246826 |
Kind Code |
A1 |
Chung; Hyun-Soo ; et
al. |
October 25, 2007 |
Wafer level semiconductor module and method for manufacturing the
same
Abstract
A wafer level semiconductor module may include a module board
and an IC chip set mounted on the module board. The IC chip set may
include a plurality of IC chips having scribe lines areas between
the adjacent IC chips. Each IC chip may have a semiconductor
substrate having an active surface with a plurality of chip pads
and a back surface. A passivation layer may be provided on the
active surface of the semiconductor substrate of each IC chip and
may having openings through which the chip pads may be exposed.
Sealing portions may be formed in scribe line areas.
Inventors: |
Chung; Hyun-Soo;
(Hwaseong-si, KR) ; Baek; Seung-Duk; (Yongin-si,
KR) ; Lee; Dong-Ho; (Seongnam-si, KR) ; Jang;
Dong-Hyeon; (Suwon-si, KR) ; Hwang; Seong-Deok;
(Seoul, KR) |
Correspondence
Address: |
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 8910
RESTON
VA
20195
US
|
Assignee: |
Samsung Electronics Co.
Ltd.
|
Family ID: |
38160887 |
Appl. No.: |
11/585088 |
Filed: |
October 24, 2006 |
Current U.S.
Class: |
257/734 |
Current CPC
Class: |
H01L 2224/05008
20130101; H01L 2224/05166 20130101; H01L 2924/01006 20130101; H01L
2924/01029 20130101; H01L 2224/05171 20130101; H01L 25/50 20130101;
H01L 2924/14 20130101; H01L 25/0655 20130101; H01L 2924/01079
20130101; H01L 2224/05022 20130101; H01L 24/13 20130101; H01L
2924/01078 20130101; H01L 2924/01023 20130101; H01L 2224/13024
20130101; H01L 2224/13099 20130101; H01L 2224/02377 20130101; H01L
2224/05647 20130101; H01L 2224/05144 20130101; H01L 2224/13
20130101; H01L 2924/014 20130101; H01L 2924/19042 20130101; H01L
24/05 20130101; H01L 2224/05147 20130101; H01L 2924/01013 20130101;
H01L 23/3114 20130101; H01L 2224/05001 20130101; H01L 2924/01024
20130101; H01L 2224/274 20130101; H01L 2924/01022 20130101; H01L
2224/05024 20130101; H01L 24/10 20130101; H01L 2924/351 20130101;
H01L 2224/05548 20130101; H01L 2924/01033 20130101; H01L 2924/3025
20130101; H01L 2224/05155 20130101; H01L 2924/01074 20130101; H01L
2924/19041 20130101; H01L 2224/13 20130101; H01L 2924/00 20130101;
H01L 2924/351 20130101; H01L 2924/00 20130101; H01L 2224/05647
20130101; H01L 2924/00014 20130101; H01L 2224/05144 20130101; H01L
2924/00014 20130101; H01L 2224/05147 20130101; H01L 2924/00014
20130101; H01L 2224/05155 20130101; H01L 2924/00014 20130101; H01L
2224/05166 20130101; H01L 2924/00014 20130101; H01L 2224/05171
20130101; H01L 2924/00014 20130101 |
Class at
Publication: |
257/734 |
International
Class: |
H01L 23/48 20060101
H01L023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 21, 2006 |
KR |
10-2006-0036312 |
Claims
1. A wafer level semiconductor module comprising: a module board;
and an IC chip set mounted on the module board, the IC chip set
including: a plurality of IC chips having scribe line areas between
adjacent IC chips, each IC chip having a semiconductor substrate
with an active surface with a plurality of chip pads and a back
surface, a passivation layer provided on the active surface of the
semiconductor substrate of each IC chip having openings through
which the chip pads are exposed, and sealing portions provided in
the scribe line areas.
2. The module of claim 1, wherein the sealing portions have a width
substantially equal to a width of the corresponding scribe line
areas.
3. The module of claim 1, wherein each IC chip has an interlayer
dielectric layer provided on the active surface of the
semiconductor substrate, a redistribution layer provided on the
interlayer dielectric layer, and an insulating layer provided on
the redistribution layer.
4. The module of claim 3, wherein the sealing portions are integral
with the interlayer dielectric layer.
5. The module of claim 3, wherein the sealing portions are integral
with the insulating layer.
6. The module of claim 1, wherein the sealing portions are formed
in a multilayered structure.
7. The module of claim 1, wherein the sealing portions are formed
from polymer composition.
8. The module of claim 7, wherein the polymer composition includes
lower-temperature-cured polymer.
9. The module of claim 1, wherein the sealing portions are formed
from at least one elastomer composition.
10. The module of claim 3, further comprising external connection
terminals provided on the redistribution layer and configured to
connect the IC chip set to the module board.
11. The module of claim 10, wherein the external connection
terminals are arranged at uniform intervals.
12. The module of claim 1, wherein the back surface of each IC chip
has a protection layer.
13. The module of claim 12, wherein the protection layer is an
adhesive tape.
14. The module of claim 1, wherein the plurality of IC chips
provided are in a matrix arrangement.
15. A method for manufacturing a wafer level semiconductor module
comprising: providing a wafer having an IC chip set having a
plurality of IC chips and scribe line areas between adjacent IC
chips, each IC chip having a semiconductor substrate having an
active surface with a plurality of chip pads and a back surface;
forming trenches in the scribe line areas; and. filling the
trenches to form sealing portions.
16. The method of claim 15, further comprising: separating the
wafer into IC chip sets; and mounting the IC chip set on the module
board.
17. The method of claim 15, wherein the trenches have a width
substantially equal to a width of the corresponding scribe line
areas.
18. The method of claim 15, further comprising: forming a
passivation layer on the active surface of the semiconductor
substrate exposing the chip pads; forming an interlayer dielectric
layer on the passivation layer; forming a redistribution layer
connected to the chip pads on the passivation layer; forming an
insulating layer on the redistribution layer and the interlayer
dielectric layer to expose a portion of the redistribution
layer.
19. The method of claim 18, wherein the sealing portions are formed
integrally with the interlayer dielectric layer.
20. The method of claim 18, wherein the sealing portions are formed
integrally with the insulating layer.
21. The method of claim 15, wherein the sealing portions are formed
in a multilayered structure.
22. The method of claim 16, wherein the wafer is separated into IC
chips sets having a matrix arrangement.
23. The method of claim 15, wherein the sealing portions are formed
by providing polymer in the trenches.
24. The method of claim 23, wherein the polymer is a
lower-temperature-cured polymer.
25. The method of claim 15, wherein the sealing portions are formed
by providing elastomer in the trenches.
26. The method of claim 18, wherein the redistribution layer is a
multilayered redistribution layer formed using the interlayer
dielectric layer.
27. The method of claim 18, further comprising removing a portion
of the back surface of the semiconductor substrate to expose a
portion of the sealing portion.
28. The method of claim 27, further comprising: forming a
protection layer on the wafer where the back surface was
removed.
29. The method of claim 28, wherein the protection layer is an
adhesive tape.
30. The method of claim 18, further comprising: providing external
connection terminals on the exposed portion of the redistribution
layer.
31. The method of claim 30, wherein the external connection
terminals are arranged over the IC chip set at uniform intervals.
Description
PRIORITY STATEMENT
[0001] This U.S. non-provisional application claims benefit of
priority under 35 U.S.C. .sctn.119 from Korean Patent Application
No. 2006-36312, filed on Apr. 21, 2006 in the Korean Intellectual
Property Office (KIPO), the entire contents of which are
incorporated herein by reference.
BACKGROUND
[0002] 1. Field
[0003] Example, non-limiting embodiments relate generally to a
semiconductor module and a method for manufacturing the
semiconductor module, for example, to a wafer level semiconductor
module implementing an integrated circuit (IC) chip set and a
method for manufacturing the wafer level semiconductor module.
[0004] 2. Description of the Related Art
[0005] The electronic industry seeks methods, techniques and
designs that provide electronic products which may be smaller,
lighter, faster, more efficient, provide multiple functions and/or
result in improved performance, at an effective cost. One such
development has been in the area of semiconductor packaging
techniques, such as chip scale packages (CSP's), wafer level
packages, or wafer level chip scale packages (WLCSP's), for
example. Another such development has been in the area of board
fabrication techniques, for example embedded printed circuit boards
(PCB's) that may include passive devices, for example capacitors or
inductors. However, it is rare to develop techniques for mounting
semiconductor packages at the module level.
[0006] FIG. 1 is a plan view of a conventional semiconductor module
500. FIG. 2 is a cross-sectional view of the conventional
semiconductor module 500.
[0007] Referring to FIGS. 1 and 2, the semiconductor module 500 may
include a module board 535, and semiconductor packages 510 and
passive devices 531 that are mounted on the module board 535 using
solder balls 529. The semiconductor package 510 may be implemented
for interconnections by a wire bonding method, a TAB bonding method
or a flip chip bonding method. The semiconductor package 510 may
have a semiconductor chip 511 that may be formed of various
structures.
[0008] The conventional semiconductor module 500 may implement the
semiconductor package 510 that may be completed through a series of
processes including a wafer fabrication process, an electric die
sorting test process and a package assembly process. Thereby, the
semiconductor module 500 may be manufactured by a complicated,
time-consuming and cost-ineffective process. Further, there may be
limitations in reducing the size of the semiconductor module
500.
SUMMARY
[0009] Example, non-limiting embodiments may provide a wafer level
semiconductor module that may reduce the size of an electronic
module, and a method for manufacturing the wafer level
semiconductor module.
[0010] In an example embodiment, a wafer level semiconductor module
may include a module board. An IC chip set may be mounted on the
module board. The IC chip set may include a plurality of IC chips
having scribe line areas between the adjacent IC chips. Each IC
chip may have a semiconductor substrate having an active surface
with a plurality of chip pads and a back surface. Sealing portions
may be provided in the scribe line areas.
[0011] According to an example embodiment, the sealing portions may
have a width substantially equal to a width of the corresponding
scribe line areas.
[0012] According to an example embodiment, each IC chip may have an
interlayer dielectric layer provided on the semiconductor
substrate, a redistribution layer may be provided on the interlayer
dielectric layer, and an insulating layer may be provided on the
redistribution layer.
[0013] According to an example embodiment, the sealing portions may
be formed integrally with the interlayer dielectric layer or the
insulating layer.
[0014] According to an example embodiment, the sealing portions may
be formed in a multilayered structure.
[0015] According to an example embodiment, the sealing portions may
be formed from polymer composition. The polymer composition may
include low-temperature-cure polymer.
[0016] According to an example embodiment, the sealing portions may
be formed from elastomer composition.
[0017] According to an example embodiment, the module may further
include external connection terminals provided on the
redistribution layer and may be configured to connect the IC chip
set to the module board. The external connection terminals may be
arranged at uniform intervals.
[0018] According to an example embodiment, the back surface of each
IC chip may have a protection layer. The protection layer may be an
adhesive tape.
[0019] According to an example embodiment, the IC chip set may
include a plurality of IC chips that may be provided in a matrix
arrangement.
[0020] In an example embodiment, a method for manufacturing a wafer
level semiconductor module may involve providing a wafer. The wafer
may have an IC chip set having a plurality of IC chips and scribe
line areas between the adjacent IC chips. Each adjacent IC chip may
have a semiconductor substrate having an active surface with a
plurality of chip pads and a back surface. A passivation layer may
be provided on the active surface of the semiconductor substrate
leaving the chip pads exposed. Trenches may be provided in the
scribe line areas. Sealing portions may be provided in the
trenches. The wafer may be separated into individual IC chip sets.
The IC chip set may be mounted on the module board.
[0021] According to an example embodiment, an interlayer dielectric
layer may be provided on the passivation layer and a redistribution
layer, the redistribution layer may be connected to the chip pads.
An insulating layer may be provided on the redistribution layer and
the interlayer dielectric layer to expose a portion of the
redistribution layer.
[0022] According to an example embodiment, the trenches may have a
width substantially equal to a width of the corresponding scribe
line areas.
[0023] According to an example embodiment, the sealing portions may
be formed integrally with the interlayer dielectric layer or the
insulating layer. The sealing portions may be formed in a
multilayered structure.
[0024] According to an example embodiment, the wafer may be
separated into IC chips having a matrix arrangement.
[0025] According to an example embodiment, the sealing portions may
be formed by providing polymer in the trenches. The polymer
provided in the trenches may be a low-temperature-cure polymer.
[0026] According to an example embodiment, the sealing portions may
be formed by providing elastomer in the trenches.
[0027] According to an example embodiment, the redistribution layer
may be a multilayered redistribution layer that may be formed using
the interlayer dielectric layer.
[0028] According to an example embodiment, a portion of the back
surface of the semiconductor substrate may be removed to expose a
portion of the sealing portions. A protection layer may be attached
to the wafer where the back surface was removed. The protection
layer may be an adhesive tape.
[0029] According to an example embodiment, external connection
terminals may be provided on the exposed portion of the
redistribution layer. The external connection terminals may be
arranged over the IC chip set at uniform intervals.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Example embodiments will be readily understood with
reference to the following detailed description thereof in
conjunction with the accompanying drawings, wherein like reference
numerals designate like structural elements.
[0031] FIG. 1 is a plan view of a conventional semiconductor
module.
[0032] FIG. 2 is a cross-sectional view of the conventional
semiconductor module in FIG. 1.
[0033] FIG. 3 is a plan view of a wafer level semiconductor module
in accordance with an example, non-limiting embodiment.
[0034] FIG. 4 is an example cross-sectional view of the wafer level
semiconductor module in FIG. 3.
[0035] FIG. 5 is an example cross-sectional view of the structure
of an IC chip set of the wafer level semiconductor module in FIG.
4.
[0036] FIGS. 6 to 16 are schematic views of a method that may be
implemented to manufacture a wafer level semiconductor module in
accordance with an example, non-limiting embodiment.
[0037] FIG. 17 is a plan view of a wafer level semiconductor module
in accordance with another example, non-limiting embodiment.
[0038] FIG. 18 is an example cross-sectional view of the wafer
level semiconductor module in FIG. 17.
[0039] FIG. 19 is a plan view of a wafer level semiconductor module
in accordance with another example, non-limiting embodiment.
[0040] FIG. 20 is a plan view of a wafer level semiconductor module
in accordance with another example, non-limiting embodiment.
[0041] FIG. 21 is a plan view of a wafer level semiconductor module
in accordance with another example, non-limiting embodiment.
[0042] FIG. 22 is a cross-sectional view of the structure of an IC
chip set of a wafer level semiconductor module in accordance with
another example, non-limiting embodiment.
[0043] FIG. 23 is a cross-sectional view of the structure of an IC
chip set of a wafer level semiconductor module in accordance with
another, non-limiting example embodiment.
[0044] FIG. 24 is a cross-sectional view of the structure of an IC
chip set of a wafer level semiconductor module in accordance with
another example, non-limiting embodiment.
[0045] FIG. 25 is a cross-sectional view of the structure of an IC
chip set of a wafer level semiconductor module in accordance with
another, non-limiting example embodiment.
[0046] FIG. 26 is a cross-sectional view of a wafer level
semiconductor module in accordance with another example,
non-limiting embodiment.
[0047] The drawings are for illustrative purposes only and are not
drawn to scale. The spatial relationships and/or relative sizing of
the elements illustrated in the various embodiments may have been
reduced, expanded or rearranged to improve the clarity of the
figures with respect to the corresponding description. The figures,
therefore, should not be interpreted as accurately reflecting the
relative sizing and/or positioning of the corresponding structural
elements that could be encompassed by an actual device manufactured
according to the example embodiments.
DESCRIPTION OF EXAMPLE NON-LIMITING EMBODIMENTS
[0048] Example, non-limiting embodiments will now be described more
fully hereinafter with reference to the accompanying drawings. This
invention may, however, be embodied in many different forms and
should not be construed as limited to the example embodiments set
forth herein. Rather, the disclosed embodiments are provided so
that this disclosure will be thorough and complete, and will fully
convey the scope of the invention to those skilled in the art. The
principles and features of this invention may be employed in varied
and numerous embodiments without departing from the scope of the
invention.
[0049] The figures are intended to illustrate the general
characteristics of methods and/or devices of example embodiments of
this invention, for the purpose of the description of such example
embodiments herein. The drawings are not, however, to scale and may
not precisely reflect the characteristics of any given embodiment,
and should not be interpreted as defining or limiting the range of
values or properties of example embodiments within the scope of
this invention. Rather, for simplicity and clarity of illustration,
the dimensions of some of the elements may be exaggerated relative
to other elements.
[0050] Well-known structures and processes are not described or
illustrated in detail to avoid obscuring the example
embodiments.
[0051] An element is considered as being mounted (or provided) "on"
another element when mounted or provided) either directly on the
referenced element or mounted (or provided) on other elements
overlaying the referenced element. Throughout this disclosure,
spatial terms such as "upper," "lower," "above" and "below" (for
example) are used for convenience in describing various elements or
portions or regions of the elements as shown in the figures. These
terms do not, however, require that the structure be maintained in
any particular orientation.
[0052] FIG. 3 is a plan view of a wafer level semiconductor module
100 in accordance with an example embodiment. FIG. 4 is a
cross-sectional view of the wafer level semiconductor module 100 in
FIG. 3.
[0053] Referring to FIGS. 3 and 4, the semiconductor module 100 may
include a module board 135 and an IC chip set 110 mounted on the
module board 135 by external connection terminals 129, for example
conductive bumps. The IC chip set 110 may include a plurality of IC
chips 111 provided in a matrix arrangement. By way of example only,
eight IC chips 111 may be arranged in a row. The plurality of IC
chips 111 may have scribe line areas (SL), which may also be
referred to as scribe lanes or sawing lanes, between the adjacent
IC chips 111. Sealing portions 117a may be provided in the scribe
line areas (SL) to surround the side surfaces of the IC chips 111.
The external connection terminals 129 may, for example, be formed
through a rerouting process at wafer level.
[0054] In an example embodiment, the plurality of IC chips 111 that
have completed a package assembly process at wafer level may be
directly attached to the module board 135. The IC chip set 110
including the plurality of IC chips 111 may be separated from a
wafer as a single entity. In this way, the semiconductor module 100
may be manufactured by a simplified process and the size of the
semiconductor module 100 may be reduced. In comparison with a
conventional semiconductor module of the same size, the
semiconductor module 100 may accommodate a greater number of the IC
chips and/or larger IC chips. Further, the module board 135 may
have an increased flexibility of design.
[0055] The module board 135, the external connection terminals 129
and the plurality of IC chip 111 may have different coefficients of
thermal expansion. The sealing portions 117a provided in the scribe
line areas (SL) may absorb mechanical stresses which may result
from the difference in coefficients of thermal expansion.
Additionally, the sealing portions 117a may serve as an electrical
shield between the plurality of IC chips 111 to reduce or prevent
electrical interference between the IC chips 111. Accordingly, the
sealing portions 117a may reduce the likelihood that warpage may
occur in edges of the IC chip set 110.
[0056] FIG. 5 is an example cross-sectional view illustrating the
structure of the IC chip set 110 of the wafer level semiconductor
module 100 in FIG. 4.
[0057] Referring to FIG. 5, each of the IC chips 111 may have a
semiconductor substrate 112 having an active surface with chip pads
113 and a back surface. A passivation layer 114 may be provided on
the active surface of the semiconductor substrate 112, which may
expose the chip pads 113. An interlayer dielectric layer 117 may be
provided on the passivation layer 114. A redistribution layer 123
may be provided on the interlayer dielectric layer 117. An
insulating layer 124 may be provided on the redistribution layer
123, which may expose a portion of the redistribution layer 123.
The external connection terminals 129 may be provided on the
exposed portion of the redistribution layer 123.
[0058] By way of example only, the sealing portions 117a may be
formed from resin, for example a polymer composition. The polymer
composition may include lower-temperature-cure polymer, of which
the curing temperature may be 200.degree. C. or lower, for example.
The lower-temperature-cure polymer may reduce the likelihood that
lower productivity may result from deterioration of the IC chips
that may occur during curing of the polymer.
[0059] In an alternative example embodiment, the sealing portions
117a may be formed from elastomer composition. The sealing portions
117a may be integral with the interlayer dielectric layer 117 and
may be formed from the same material as the interlayer dielectric
layer 117. For example, the sealing portions 117a may be formed by
providing insulating materials in trenches 115 while the interlayer
dielectric layer 117 is formed.
[0060] The width of the sealing portions 117a may be substantially
equal to the width of the corresponding scribe line areas (SL). The
sealing portions 117a may run through the full depth of the
semiconductor substrate 112. In this way, the sealing portions 117a
may secure the maximum volume between the adjacent IC chips 111 to
provide the maximum stress-absorbing effect. Alternatively, the
sealing portions 117a may run through a portion of the
semiconductor substrate 112, or the width of the sealing portions
117a may be smaller than the width of the corresponding scribe line
areas (SL).
[0061] A protection layer 125, for example, adhesive tape, may be
provided on the back surface of the semiconductor substrate 112 and
may be configured to protect the back surface of the semiconductor
substrate 112. By way of example only, the protection layer 125 may
be a polyimide tape. Alternatively, the protection layer 125 may be
other various elements for protecting the back surface of the
semiconductor substrate 112.
[0062] FIGS. 6 to 16 are schematic views of a method for
manufacturing a wafer level semiconductor module in accordance with
an example embodiment.
[0063] Referring to FIG. 6, a wafer (W) may include an IC chip set
having a plurality of IC chips 111. Each IC chip 111 may have a
silicon semiconductor substrate 112, chip pads 113 and a
passivation layer 114. By way of example only, the chip pads 113
may be formed from metals, for example aluminum. The passivation
layer 114 may be formed from nitride, for example. The passivation
layer 114 may be provided on the active surface of each IC chip 111
and may expose the chip pads 113. The chip pads 113 may be arranged
along the opposing edges of each IC chip 111 or at the center of
each IC chip 111, for example. The IC chip set may have scribe line
areas (SL) between adjacent IC chips 111.
[0064] Referring to FIG. 7, trenches 115 may be formed in the
scribe line areas (SL). The trenches 115 may run to a determined
depth of the semiconductor substrate 112 through the passivation
layer 114. By way of example only, the trenches 115 may be formed
using a photolithographic process and an etching process. The width
of the trenches 115 may be smaller than or equal to the width of
the corresponding scribe line areas (SL). If the width of the
trenches 115 is equal to the width of the corresponding scribe line
areas (SL), the volume of the sealing portions 117a that may be
provided in the trenches 115 may be maximumized. To secure the
maximum volume, the trenches 115 may extend perpendicularly to the
wafer surface from the edges of the scribe line areas (SL). The
shape of the trenches 115 may vary.
[0065] Referring to FIG. 8, the trenches 115 may be filled. An
interlayer dielectric layer 117 may be provided on the passivation
layer 114 that may expose the chip pads 113. While the interlayer
dielectric layer 117 is being formed, the trenches 115 may be
filled with materials to form sealing portions 117a. For example,
the interlayer dielectric layer 117 and the sealing portions 117a
may serve as thermal stress absorption and/or electrical
insulation. By way of example only, the interlayer dielectric layer
117 may be formed from polymer composition, for example
photosensitive polyimide (PSPI), benzo-cyclo-butene (BCB), or
epoxy. For example, the interlayer dielectric layer 117 may be
provided on the surface of the semiconductor substrate 112 using a
spin coating method, and a portion of the interlayer dielectric
layer 117 may be removed using a photo process to expose the chip
pads 113.
[0066] Referring to FIG. 9, a seed metal layer 119 may be provided
on the interlayer dielectric layer 117 and may be connected to the
chip pads 113. By way of example only, the seed metal layer 119 may
be formed using a deposition method or a sputtering method. The
seed metal layer 119 may be multilayered using alloy of various
metals, for example, Ti/Cu, Cr/Cu, Cr/Ni, CrN, Ti/Cu/Ni, or
Cr/Ni/Au.
[0067] A photoresist layer 121 may be provided on the seed metal
layer 119. For example, the photoresist layer 121 may be formed
through application, exposure and development of photoresist
materials. The photoresist layer 121 may be used to expose a
portion of the seed metal layer 119.
[0068] Referring to FIG. 10, a redistribution layer 123 may be
provided on the exposed portion of the seed metal layer 119. The
redistribution layer 123 may be formed from materials having
improved electrical conductivity, for example, Cu. The
redistribution layer 123 may be connected to the chip pads 113. By
way of example only, the redistribution layer 123 may be formed by
an electroplating process using the seed metal layer 119 as a
plating electrode. The electroplating process may be replaced with
an electroless process, a mechanical vapor deposition process or a
chemical vapor deposition process, for example. After the
redistribution layer 123 is provided, the photoresist layer 121 may
be removed.
[0069] Referring to FIG. 11, the exposed portion of the seed metal
layer 119 may be removed using the redistribution layer 123 as a
mask. By way of example only, removal of the seed metal layer 119
may be implemented by an anisotropic etching method or an isotropic
etching method.
[0070] Referring to FIG. 12, an insulating layer 124 may be
provided on the redistribution layer 123 and the interlayer
dielectric layer 117. A portion of the insulating layer 124 may be
removed so that external connection terminals may be provided on
the exposed redistribution layer 123. By way of example only, the
insulating layer 124 may be formed from the same material as the
interlayer dielectric layer 117. The resultant wafer (W) may be
backlapped to reduce the thickness. The backlapping process may
expose a portion of the sealing portions 117a.
[0071] Referring to FIG. 13, a protection layer 125, for example an
adhesive tape, may be attached to the back surface of the wafer
(W). The protection layer 125 may protect the back surface of the
IC chip 111 from the external environment. By way of example only,
the protection layer 125 may be an insulating tape having adhesive
property, for example a polyimide tape. Elements and/or processes
for protecting the IC chip 111 may vary.
[0072] Referring to FIG. 14, external connection terminals 129 may
be provided on the exposed portion of the redistribution layer 123.
A multilayered under bump metallurgic (UBM) layer may be provided
under the external connection terminals 129. The external
connection terminals 129 may be aligned on and attached to the
exposed portion of the redistribution layer 123 using a reflow
process. By way of example only, the external connection terminals
129 may be conductive bumps formed from metals, for example, Cu, Au
or Ni. Although the external connection terminals 129 may be formed
using a plating method, formation of the external connection
terminals 129 may be not limited in this regard. For example, the
external connection terminals 129 may be formed using a bump
placement method or a stencil printing method.
[0073] Referring to FIGS. 14-16, an IC chip set 110 may be
separated from the wafer (W). The IC chip set 110 may include a
plurality of the IC chips 111 provided in an m*n matrix
arrangement, for example 1*8. The IC chip set 110 may be sawed
along the scribe line areas (SL) using a sawing blade 150.
[0074] Returning to FIG. 4, the IC chip set 110 may be mounted on a
module board 135 using the external connection terminals 129.
[0075] FIG. 17 is a plan view of a wafer level semiconductor module
200 in accordance with another example embodiment. FIG. 18 is a
cross-sectional view of the wafer level semiconductor module 200 in
FIG. 17.
[0076] Referring to FIGS. 17 and 18, the wafer level semiconductor
module 200 may include a module board 235 and an IC chip set 210
mounted on the module board 235. For example, the IC chip set 210
may include a plurality of IC chips 211 provided in a 2*4 matrix
arrangement. The two-row arrangement of the IC chips 211 may allow
for reduced length of the semiconductor module 200. Sealing
portions 217a may be configured to absorb thermal stresses.
[0077] FIG. 19 is a plan view of a wafer level semiconductor module
301 in accordance with another example embodiment. FIG. 20 is a
plan view of a wafer level semiconductor module 302 in accordance
with another example embodiment. FIG. 21 is a plan view of a wafer
level semiconductor module 303 in accordance with another example
embodiment.
[0078] Referring to FIG. 19, the wafer level semiconductor module
301 may include a module board 335 and an IC chip set 310 mounted
on the module board 335. For example, the IC chip set 310 may
include a plurality of IC chips 311 provided in a 1*8 matrix
arrangement.
[0079] Referring to FIG. 20, the wafer level semiconductor module
302 may include a module board 335 and an IC chip set 310a mounted
on the module board 335. For example, the IC chip set 310a may
include a plurality of IC chips 311 provided in a 1*11 matrix
arrangement.
[0080] Referring to FIG. 21, the wafer level semiconductor module
303 may include a module board 335 and an IC chip set 310b mounted
on the module board 335. For example, the IC chip set 310b may
include a plurality of IC chips 311 provided in a 2*11 matrix
arrangement.
[0081] FIG. 22 is a cross-sectional view illustrating the structure
of an IC chip set 410a of a wafer level semiconductor module in
accordance with another example embodiment. FIG. 23 is a
cross-sectional view of the structure of an IC chip set 410b of a
wafer level semiconductor module in accordance with another example
embodiment. FIG. 24 is a cross-sectional view of the structure of
an IC chip set 410c of a wafer level semiconductor module in
accordance with another example embodiment. FIG. 25 is a
cross-sectional view of the structure of an IC chip set 410d of a
wafer level semiconductor module in accordance with another example
embodiment.
[0082] Referring to FIG. 22, in the structure of the IC chip set
410a, sealing portions 418 may be unconnected to an interlayer
dielectric layer 417. Before the interlayer dielectric layer 417 is
provided, polymer may be filled in trenches 415 to form the sealing
portions 418. By way of example only, the sealing portions 418 may
be formed from materials different from the interlayer dielectric
layer 417, such as an elastomer composition.
[0083] Referring to FIG. 23, in the structure of the IC chip set
410b, sealing portions may be formed of a multilayered dielectric
structure. An interlayer dielectric layer 417a and an insulating
layer 424a may be provided in trenches 415 to form the sealing
portions. For example, the interlayer dielectric layer 417a and the
insulating layer 424a may each be filled in the trenches 415 at a
predetermined thickness.
[0084] Referring to FIG. 24, in the structure of the IC chip set
410c, a multilayered, for example two-layered, redistribution layer
423a and 423b may be formed with interlayer dielectric layers 417
and 420. While an insulating layer 424 is being formed, the
insulating layer 424 may be filled in trenches 415 to form sealing
portions 424a.
[0085] Referring to FIG. 25, in the structure of the IC chip set
410d, interlayer dielectric layers 417a and 420a and an insulating
layer 424a may be provided in trenches 415 to form multilayered
sealing portions. For example, the interlayer dielectric layers
417a and 420a and the insulating layer 424a may each be filled in
the trench 415 at a predetermined or desired thickness.
[0086] FIG. 26 is a cross-sectional view of a wafer level
semiconductor module 400 in accordance with another example
embodiment.
[0087] Referring to FIG. 26, the wafer level semiconductor module
400 may include a module board 435 and an IC chip set 410f mounted
on the module board 435 using external connection terminals 429a.
External connection terminals 429a, for example the conductive
bumps, may be uniformly arranged over the back surface of the IC
chip set 410f. The arrangement of the external connection terminals
may be made with regard to a chip or an IC chip set. The
arrangement of the external connection terminals may (for example)
reduce electrical connection routes of a semiconductor module.
[0088] In accordance with example, non-limiting embodiments, a
wafer level semiconductor module in which an IC chip set may be
mounted on a module board may reduce the size and/or increase
capacity of the module board. Further, sealing portions provided in
scribe line areas may absorb thermal stresses to reduce warpage of
an IC chip set and/or prevent electrical interference between IC
chips, which may improve the electrical and thermal characteristics
of a semiconductor module.
[0089] Although example, non-limiting embodiments have been
described in detail hereinabove, it should be understood that many
variations and/or modifications of the basic inventive concepts
taught herein, which may appear to those skilled in the art, will
still fall within the spirit and scope as defined by the appended
claims.
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