U.S. patent application number 11/475400 was filed with the patent office on 2007-09-27 for chip package and fabricating method thereof.
Invention is credited to Chia-Jung Chang, Kwun-Yao Ho, Moriss Kung.
Application Number | 20070222072 11/475400 |
Document ID | / |
Family ID | 38532500 |
Filed Date | 2007-09-27 |
United States Patent
Application |
20070222072 |
Kind Code |
A1 |
Chang; Chia-Jung ; et
al. |
September 27, 2007 |
Chip package and fabricating method thereof
Abstract
A chip package including a chip, a package substrate, and a
plurality of bumps is provided. The chip has a plurality of chip
pads disposed on a surface of the chip. The package substrate has a
plurality of first substrate pads, a plurality of second substrate
pads, and a surface bonding layer. The first substrate pads and
second substrate pads are disposed on a surface of the package
substrate. The surface bonding layer is disposed on the first
substrate pads and second substrate pads, and covers a part of each
second substrate pad. The bumps are respectively disposed between
the chip pads and the surface bonding layer. The chip is
electrically connected to the package substrate through the bumps.
Each first substrate pad is electrically connected to one of the
bumps, and each second substrate pad is electrically connected to
at least two of the bumps.
Inventors: |
Chang; Chia-Jung; (Hsin-Tien
City, TW) ; Ho; Kwun-Yao; (Hsin-Tien City, TW)
; Kung; Moriss; (Hsin-Tien City, TW) |
Correspondence
Address: |
J.C. Patents, Inc.;Suite 250
4 Venture
Irvine
CA
92618
US
|
Family ID: |
38532500 |
Appl. No.: |
11/475400 |
Filed: |
June 26, 2006 |
Current U.S.
Class: |
257/737 ;
257/E21.503; 257/E23.021 |
Current CPC
Class: |
H01L 24/10 20130101;
H01L 2224/73203 20130101; H01L 2224/81193 20130101; H01L 2924/14
20130101; H01L 2924/01029 20130101; H01L 24/81 20130101; H01L
2924/014 20130101; H01L 21/563 20130101; H01L 2224/13021 20130101;
H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L 2924/01078
20130101; H01L 2224/13 20130101; H01L 2224/16238 20130101; H01L
2924/01082 20130101; H01L 2924/01079 20130101; H01L 2224/13
20130101; H01L 2224/16237 20130101; H01L 2224/13099 20130101; H01L
2224/05572 20130101; H01L 2224/05001 20130101; H01L 2224/05022
20130101; H01L 2224/13144 20130101; H01L 2224/13147 20130101; H01L
2224/81191 20130101; H01L 2924/00014 20130101; H01L 2224/81203
20130101; H01L 2224/16501 20130101; H01L 2924/0105 20130101; H01L
2224/81801 20130101; H01L 2924/01006 20130101; H01L 2924/15311
20130101; H01L 24/13 20130101; H01L 2224/1601 20130101; H01L
2924/01033 20130101; H01L 2924/00 20130101; H01L 2224/05099
20130101; H01L 2224/05599 20130101 |
Class at
Publication: |
257/737 |
International
Class: |
H01L 23/48 20060101
H01L023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 24, 2006 |
TW |
95110239 |
Claims
1. A chip package, comprising: a chip having a plurality of chip
pads disposed on a surface of the chip; a package substrate having
a plurality of first substrate pads, a plurality of second
substrate pads, and a surface bonding layer, wherein the first
substrate pads and the second substrate pads are disposed on a
surface of the package substrate, wherein the surface bonding layer
is disposed on the first substrate pads and the second substrate
pads, wherein the second substrate pad has a first region and a
second region and the surface bonding layer covers the first region
of the second substrate pad; and a plurality of bumps disposed
between the chip pads and the surface bonding layer, wherein the
chip is electrically connected to the package substrate through the
bumps, each first substrate pad is electrically connected to one of
the bumps, and each second substrate pad is electrically connected
to at least two of the bumps.
2. The chip package according to claim 1, wherein the thickness of
the surface bonding layer is less than 5 .mu.m.
3. The chip package according to claim 1, wherein the package
substrate comprises a first solder mask layer disposed on the
second substrate pads and having a plurality of openings, wherein
the surface bonding layer covers the second region of the second
substrate pads is disposed in the openings.
4. The chip package according to claim 1, wherein the package
substrate comprises a second solder mask layer disposed on the
surface of the package substrate and exposing the first substrate
pads and the second substrate pads.
5. The chip package according to claim 1, wherein each first
substrate pad is partially embedded in one of the bumps.
6. The chip package according to claim 1, wherein the material of
the bumps is a lead-free material.
7. The chip package according to claim 6, wherein the material of
the bumps comprises Au, Cu, Sn, or Ni.
8. The chip package according to claim 1, further comprising an
interface metal layer disposed between the bumps and the surface
bonding layer, wherein the melting point of the interface metal
layer is lower than that of the bumps.
9. The chip package according to claim 1, wherein the chip pads are
disposed on the surface of the chip in a plane array.
10. A method of fabricating the chip package, comprising: providing
a chip having a plurality of chip pads and a plurality of bumps,
wherein the chip pads are disposed on a surface of the chip, and
the bumps are disposed on the chip pads; providing a package
substrate having a plurality of first substrate pads and a
plurality of second substrate pads, wherein the first substrate
pads and the second substrate pads are disposed on a surface of the
package substrate; forming a surface bonding layer on the first
substrate pads and the second substrate pads; and performing a
thermal compression bonding process to make the bumps bonded to the
surface bonding layer.
11. The method of fabricating the chip package according to claim
10, wherein in the step of providing a package substrate, the
package substrate comprises a solder mask layer disposed on the
surface of the package substrate and exposing the first substrate
pads and the second substrate pads.
12. The method of fabricating the chip package according to claim
10, wherein during the thermal compression bonding process, when
the bumps are bonded to the surface bonding layer, the bumps
chemically react with the surface bonding layer to form an
interface metal layer.
13. The method of fabricating the chip package according to claim
10, wherein the surface bonding layer exposes a part of the second
substrate pads.
14. The method of fabricating the chip package according to claim
10, wherein each first substrate pad is electrically connected to
one of the bumps, each second substrate pad is electrically
connected to at least two of the bumps, and the melting point of
the bumps is at least 50.degree. C. higher than an operation
temperature of the thermal compression bonding process.
15. The method of fabricating the chip package according to claim
10, further comprising: forming a first solder mask layer on the
surface bonding layer of the second substrate pads; and forming a
plurality of openings on the first solder mask layer to expose
parts of the surface bonding layer.
16. The method of fabricating the chip package according to claim
15, wherein in the step of providing a package substrate, the
package substrate comprises a second solder mask layer disposed on
the surface of the package substrate and exposing the first
substrate pads and the second substrate pads.
17. A method of fabricating the chip package, comprising: providing
a chip having a plurality of chip pads and a plurality of bumps,
wherein the chip pads are disposed on a surface of the chip, and
the bumps are respectively disposed on the chip pads; providing a
package substrate having a plurality of first substrate pads and a
plurality of second substrate pads, wherein the first substrate
pads and the second substrate pads are disposed on a surface of the
package substrate; forming a first solder mask layer on the second
substrate pads; patterning the first solder mask layer, so as to
make the first solder mask layer have a plurality of openings to
expose a part of the second substrate pads respectively; forming a
surface bonding layer on the first substrate pads and the second
substrate pads, wherein parts of the surface bonding layer are
formed in the openings respectively; and performing a thermal
compression bonding process to make the bumps bonded to the surface
bonding layer.
18. The method of fabricating the chip package according to claim
17, wherein in the step of providing a package substrate, the
package substrate comprises a second solder mask layer disposed on
the surface of the package substrate and exposing the first
substrate pads and the second substrate pads.
19. The method of fabricating the chip package according to claim
17, wherein during the thermal compression bonding process, when
the bumps are bonded to the surface bonding layer, the bumps
chemically react with the surface bonding layer to form an
interface metal layer.
20. The method of fabricating the chip package according to claim
17, wherein each first substrate pad is electrically connected to
one of the bumps, each second substrate pad is electrically
connected to at least two of the bumps, and the melting point of
the bumps is at least 50.degree. C. higher than an operation
temperature of the thermal compression bonding process.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefit of Taiwan
application serial no. 95110239, filed on Mar. 24, 2006. All
disclosure of the Taiwan application is incorporated herein by
reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of Invention
[0003] The present invention relates to a semiconductor device and
the fabricating method thereof, and more particularly to a chip
package and the fabricating method thereof.
[0004] 2. Description of Related Art
[0005] In the semiconductor industry, the manufacture of integrated
circuits (IC) is mainly divided into three stages, namely IC
design, IC process, and IC package.
[0006] During the fabrication of ICs, a chip is obtained through
steps of wafer fabrication, IC forming, and wafer dicing. The wafer
has an active surface which generally refers to the surface of the
wafer with active devices. After the IC on the wafer is finished, a
plurality of chip pads is disposed on the active surface of the
wafer, such that the chip formed finally through wafer dicing is
electrically connected to a carrier through the chip pads. The
carrier is, for example, a leadframe or a package substrate. The
chip is connected to the carrier by means of wire bonding or flip
chip bonding, so as to make the chip pads of the chip electrically
connected to the contact of the carrier. Thus, a chip package is
formed.
[0007] As for the flip chip bonding technology, usually after the
chip pads are formed on the active surface of the wafer, a bump is
fabricated on each of the chip pads for use in electrically
connecting the chip to the external package substrate. Since the
bumps are usually arranged on the active surface of the chip in a
plane array, the flip chip bonding technology is suitable for chip
packages of high contact number and high contact density, for
example, a flip chip/ball grid array package commonly used in the
semiconductor package industry. Besides, compared with the wire
bonding technology, the flip chip bonding technology may enhance
the electrical performance of the chip package because the bumps
provide a short transmission path between the chip and the
carrier.
[0008] Referring to FIG. 1, it is a sectional view of a
conventional chip package. A conventional chip package 100 includes
a chip 110, a package substrate 120, a plurality of bumps 130, and
an interface metal layer 140. The chip 110 has a plurality of chip
pads 112 disposed on a surface 114 of the chip 110. The package
substrate 120 has a plurality of first substrate pads 122, a
plurality of second substrate pads 124, and a surface bonding layer
126. The first substrate pads 122 and the second substrate pads 124
are disposed on a surface 128 of the package substrate 120. The
surface bonding layer 126 (the material thereof is Sn) is disposed
on the first substrate pads 122 and the second substrate pads 124,
and the layer 126 also completely covers the first substrate pads
122 and the second substrate pads 124.
[0009] The bumps 130 are respectively disposed between the chip
pads 112 and the surface bonding layer 126. The interface metal
layer 140 is disposed between the bumps 130 and the surface bonding
layer 126. The chip 110 is electrically connected to the package
substrate 120 through the bumps 130. Additionally, each first
substrate pad 122 is electrically connected to one of the bumps
130, and each second substrate pad 124 is electrically connected to
two or more of the bumps 130. It should be noted that the surface
bonding layer 126 is used to provide a better bonding between the
bumps 130 and the correspondingly-connected first substrate pads
122 or second substrate pads 124.
[0010] In general, the surface area of the surface bonding layer
126 formed on the second substrate pads 124 is much larger than the
total contact surface area of the connected bumps 130, while the
surface area of the surface bonding layer 126 formed on the first
substrate pads 122 is slightly larger than the contact surface area
of the connected bumps 130.
[0011] The conventional chip package 100 is formed by a thermal
compression bonding process. In particular, after the bumps 130 are
respectively formed on the chip pads 112 in advance, and the
surface bonding layer 126 is formed on the first substrate pads 122
and the second substrate pads 124, each of the bumps 130 is then
pressed onto one of the first substrate pads 122 or of the second
substrate pads 124 by means of high-temperature compression. Each
of the bumps 130 chemically reacts with the surface bonding layer
126 to form the interface metal layer 140, so that the chip 110 is
electrically connected to the package substrate 120.
[0012] During the thermal compression bonding process, as the
surface area of the surface bonding layer 126 formed on the first
substrate pads 122 is slightly larger than the contact surface area
of the connected bumps 130, the contact surface area may be quickly
increased to be equal to the surface area of the surface bonding
layer 126 formed on the first substrate pads 122. As such, the
material of the surface bonding layer 126 may be completely used to
connect the bumps 130.
[0013] However, as for the second substrate pads 124, the overall
contact surface area of the bumps 130 may not be increased to be
equal to the surface area of the surface bonding layer 126 formed
on the second substrate pads 124, so parts of the surface bonding
layer 126 respectively disposed on the second substrate pads 124 in
a melting state rises along the side of the bumps 130 toward the
chip 110 and further contaminates the chip 110.
SUMMARY OF THE INVENTION
[0014] The present invention provides a chip package, which
comprises a chip, a package substrate, and a plurality of bumps.
The chip has a plurality of chip pads disposed on a surface of the
chip. The package substrate has a plurality of first substrate
pads, a plurality of second substrate pads, and a surface bonding
layer. The first substrate pads and the second substrate pads are
disposed on a surface of the package substrate. The surface bonding
layer is disposed on the first substrate pads and the second
substrate pads and covers the first region of the second substrate
pad. The bumps are respectively disposed between the chip pads and
the surface bonding layer. The chip is electrically connected to
the package substrate through the bumps. Each first substrate pad
is electrically connected to one of the bumps and each second
substrate pad is electrically connected to at least two of the
bumps.
[0015] The present invention provides a method of fabricating the
chip package, which comprises the following steps. First, a chip is
provided, which has a plurality of chip pads and a plurality of
bumps, wherein the chip pads are disposed on a surface of the chip,
and the bumps are disposed on the chip pads. Then, a package
substrate is provided, which has a plurality of first substrate
pads and a plurality of second substrate pads, wherein the first
substrate pads and the second substrate pads are disposed on a
surface of the package substrate. After that, a surface bonding
layer is formed on the first substrate pads and the second
substrate pads. Then, a thermal compression bonding process is
performed to make the bumps bonded to the surface bonding layer. As
such, each first substrate pad is electrically connected to one of
the bumps, and each second substrate pad is electrically connected
to at least two of the bumps.
[0016] The present invention provides a method of fabricating the
chip package, which comprises the following steps. First, a chip is
provided, which has a plurality of chip pads and a plurality of
bumps, wherein the chip pads are disposed on a surface of the chip,
and the bumps are respectively disposed on the chip pads. Then, a
package substrate is provided, which has a plurality of first
substrate pads and a plurality of second substrate pads, wherein
the first substrate pads and the second substrate pads are disposed
on a surface of the package substrate. Next, a first solder mask
layer is formed on the second substrate pads. After that, the first
solder mask layer is patterned to have a plurality of openings to
expose a part of the second substrate pads respectively. Then, a
surface bonding layer is formed on the first substrate pads and the
second substrate pads, wherein parts of the surface bonding layer
are formed in the openings respectively. Next, a thermal
compression bonding process is performed to make the bumps bonded
to the surface bonding layer. As such, each first substrate pad is
electrically connected to one of the bumps, and each second
substrate pad is electrically connected to at least two of the
bumps.
[0017] In order to the make aforementioned and other features and
advantages of the present invention more comprehensible, a
plurality of embodiments accompanied with figures is described in
detail below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a sectional view of the conventional chip
package.
[0019] FIG. 2 is a sectional view of a chip package according to
the first embodiment of the present invention.
[0020] FIGS. 3A to 3E are sectional views of the method of
fabricating the chip package in FIG. 2.
[0021] FIG. 4 is a sectional view of a chip package according to
the second embodiment of the present invention.
[0022] FIGS. 5A to 5D are sectional views of a part of steps of the
method of fabricating the chip package as shown in FIG. 4.
[0023] FIG. 6 is a sectional view of a chip package according to
the third embodiment of the present invention.
[0024] FIGS. 7A to 7D are sectional views of a part of steps of the
method of fabricating the chip package in FIG. 6.
DESCRIPTION OF EMBODIMENTS
The First Embodiment
[0025] Referring to FIG. 2, it is the sectional view of a chip
package according to the first embodiment of the present invention.
In the first embodiment, a chip package 200 comprises a chip 210, a
package substrate 220, and a plurality of bumps 230. The chip 210
has a plurality of chip pads 212 that are, for example, disposed on
a surface 214 of the chip 210 in a plane array. The package
substrate 220 has a plurality of first substrate pads 222, a
plurality of second substrate pads 224, and a surface bonding layer
226. The first substrate pads 222 and the second substrate pads 224
are disposed on a surface 228 of the package substrate 220. The
surface bonding layer 226 is disposed on the first substrate pads
222 and the second substrate pads 224, and the layer 226 covers a
part of each second substrate pad 224.
[0026] The bumps 230 are respectively disposed between the chip
pads 212 and the surface bonding layer 226. The chip 210 is
electrically connected to the package substrate 220 through the
bumps 230. Each first substrate pad 222 (for example, signal pad)
is electrically connected to one of the bumps 230, and each second
substrate pad 224 (for example, power supply pad or ground pad) is
electrically connected to at least two of the bumps 230. It should
be noted that the surface bonding layer 226 is used to provide a
better bonding between the bumps 230 and the correspondingly
connected first substrate pads 222 or second substrate pads
224.
[0027] In the first embodiment, the material of the surface bonding
layer 226 is, for example, Sn, Sn-base alloys, or Sn-base
compounds, and the thickness thereof is, for example, less than 5
.mu.m. The package substrate 220 includes a solder mask layer M
disposed on the surface 228 of the package substrate 220 and
exposing the first substrate pads 222 and the second substrate pads
224. The solder mask layer M is used to protect surface lines (not
shown) in other areas of the surface 228 of the package substrate
220. In FIG. 2, each first substrate pad 222 may be partially
embedded in each of the correspondingly connected bumps 230, so as
to provide a better bonding between each first substrate pad 222
and each correspondingly connected bump 230. Additionally, the
shape of the bumps 230 may be spherical, ellipsoidal, or columnar,
and the material thereof may be a lead-free material, for example,
Au, Cu, Sn, Ni, or alloys or compounds of Au, Cu, Sn, or Ni.
[0028] The materials mentioned in the first embodiment may be
applied to subsequent embodiments, and the dimension mentioned in
the first embodiment may also be applied to subsequent
embodiments.
[0029] In the first embodiment, the chip package 200 further
comprises an interface metal layer 240, an underfill layer 250, and
a plurality of electrical contacts 260. The interface metal layer
240 is disposed between the bumps 230 and the surface bonding layer
226, and the melting point of the interface metal layer 240 is
lower than that of the bumps 230. The underfill layer 250 is
disposed between the chip 210 and the package substrate 220, and
covers the bumps 230. The underfill layer 250 is used to protect
the bumps 230 and to alleviate the mismatch of the thermal strains
generated by heating the package substrate 220 and the chip
210.
[0030] Besides, the electrical contacts 260 are disposed on a
surface 228a of the package substrate 220 away from the chip 210 to
electrically connect other electronic devices (not shown). The
electrical contacts 260 of the first embodiment are conductive
balls for providing signal input/output interfaces of ball grid
array (BGA). Moreover, the electrical contacts 260 may also be
conductive pins or conductive columns for respectively providing
signal input/output interfaces of pin grid array (PGA) or column
grid array (CGA) (both not shown).
[0031] The method of fabricating the chip package 200 is
illustrated as follows. FIGS. 3A to 3E are sectional views of the
method of fabricating the chip package in FIG. 2.
[0032] First, referring to FIG. 3A, a chip 210 is provided. The
chip 210 has a plurality of chip pads 212 and a plurality of bumps
230. The chip pads 212 are disposed on a surface 214 of the chip
210, and the bumps 230 are respectively disposed on the chip pads
212.
[0033] Then, a package substrate 220 is provided. The package
substrate 220 has a plurality of first substrate pads 222 and a
plurality of second substrate pads 224. The first substrate pads
222 and the second substrate pads 224 are disposed on a surface 228
of the package substrate 220. Besides, the package substrate 220
includes a solder mask layer M disposed on the surface 228 of the
package substrate 220 and exposing the first substrate pads 222 and
the second substrate pads 224.
[0034] Afterward, referring to FIG. 3B, a surface bonding layer 226
is formed on the first substrate pads 222 and the second substrate
pads 224 by means of plating or methods other than plating.
[0035] Next, referring to FIG. 3C, the surface bonding layer 226
disposed on the second substrate pads 224 is patterned through
lithography and etching processes to expose a part of each of the
second substrate pads 224.
[0036] Then referring to FIG. 3D, a thermal compression bonding
process is performed to make the bumps 230 bonded to the surface
bonding layer 226. Each first substrate pad 222 is electrically
connected to one of the bumps 230, and each second substrate pad
224 is electrically connected to at least two of the bumps 230.
Additionally, the melting point of the bumps 230 is at least
50.degree. C. higher than an operation temperature of the thermal
compression bonding process, i.e., a temperature for pressing the
bumps 230 and the first substrate pads 222 or second substrate pads
224. During the thermal compression bonding process as shown in
FIG. 3D, when the bumps 230 are bonded to the surface bonding layer
226, the bumps 230 chemically react with the surface bonding layer
226 to form an interface metal layer 240.
[0037] It should be noted that, the surface bonding layer 226 on
the second substrate pads 224, which is in an area not
correspondingly connected to the bumps 230, is almost removed
through the patterning step as shown in FIG. 3B, so in the thermal
compression bonding process shown in FIG. 3D, the surface bonding
layer 226 on the second substrate pads 224 is not easily to rise
along the side of the bumps 230 toward the chip 210 through the
effect cf surface tension. Thus, the surface bonding layer 226 on
the second substrate pads 224 does not contaminate the chip
210.
[0038] Next, referring to FIG. 3E, an underfill layer 250 is formed
between the chip 210 and the package substrate 220, and covers the
bumps 230.
[0039] After that, a plurality of electrical contacts 260 (for
example, conductive balls) is formed on the surface 228a of the
package substrate 220 away from the chip 210.
[0040] The chip package 200 is completed through the above
steps.
The Second Embodiment
[0041] Referring to FIGS. 2 and 4, FIG. 4 is a sectional view of a
chip package according to the second embodiment of the present
invention. The difference between a chip package 300 of the second
embodiment and the chip package 200 of the first embodiment is that
a package substrate 320 of the chip package 300 includes two solder
mask layers M1 and M2. The function and allocation of the solder
mask layer M2 are the same as those of the aforementioned solder
mask layer M of the first embodiment. The solder mask layer M1 is
disposed on the second substrate pads 324 and has a plurality of
openings O. A surface bonding layer 326 disposed on the second
substrate pads 324 is located in the openings O.
[0042] Further, the method of fabricating the chip package 300 is
different from that of the chip package 200. FIGS. 5A to 5D are
sectional views of a part of steps of the method of fabricating the
chip package as shown in FIG. 4.
[0043] After the steps as shown in FIG. 3A and disclosed in the
related descriptions, i.e., after the steps of providing a chip 310
and a package substrate 320 in the second embodiment, referring to
FIG. 5A, a solder mask layer M1 is formed on the second substrate
pads 324.
[0044] Next, referring to FIG. 5B, the solder mask layer M1 is
patterned by, for example, the lithography and etching processes,
so as to make the solder mask layer M1 have a plurality of openings
O to expose a part of each of the second substrate pads 324.
[0045] Then, referring to FIG. 5C, a surface bonding layer 326 is
formed on the first substrate pads 322 and the second substrate
pads 324 by plating or methods other than plating, wherein a part
of the surface bonding layer 326 are formed in the openings O
respectively, i.e., a part of the surface bonding layer 326 formed
on the second substrate pads 324 respectively is located in the
openings O respectively.
[0046] Afterward, referring to FIG. 5D, a thermal compression
bonding process is performed to make the bumps 330 bonded to the
surface bonding layer 326. The manner of connecting the bumps 330
and the first substrate pads 322 or the second substrate pads 324
and the relation between the melting point of the bumps 330 and the
operation temperature of the thermal compression bonding process
are the same as those in the first embodiment, and they will not be
described herein again.
[0047] Then, an underfill layer 350 and a plurality of electrical
contacts 360 are formed at the same relative position and in the
same manner as those of the first embodiment.
[0048] The chip package 300 is completed through the above
steps.
The Third Embodiment
[0049] Referring to FIGS. 4 and 6, FIG. 6 is a sectional view of a
chip package according to the third embodiment of the present
invention. The difference between a chip package 400 of the third
embodiment and the chip package 300 of the second embodiment is the
arrangement of a solder mask layer M1' and a surface bonding layer
426 of a package substrate 420 of the chip package 400. The surface
bonding layer 426 is disposed on the first substrate pads 422 and
the second substrate pads 424. The solder mask layer M1' is
disposed on the surface bonding layer 426 of the second substrate
pads 422 and has a plurality of openings O' to expose the surface
bonding layer 426.
[0050] Moreover, the method of fabricating the chip package 400 is
different from the methods of fabricating the chip packages 200,
300.
[0051] FIGS. 7A to 7D are sectional views of a part of steps of the
method of fabricating the chip package in FIG. 6.
[0052] After the steps as shown in FIG. 3A and disclosed in the
related description, i.e., after the steps of providing a chip 410
and a package substrate 420 in the third embodiment, referring to
FIG. 7A, a surface bonding layer 426 is formed on the first
substrate pads 422 and the second substrate pads 424 by plating or
methods other than plating.
[0053] Then, referring to FIG. 7B, a solder mask layer M1' is
formed on the surface bonding layer 426 of the second substrate
pads 424.
[0054] Afterwards, referring to FIG. 7C, the solder mask layer M1'
is patterned by the lithography and etching processes to have a
plurality of openings O' to expose a part of the surface bonding
layer 426.
[0055] Then referring to FIG. 7D, a thermal compression bonding
process is performed to make the bumps 430 bonded to the surface
bonding layer 426. The manner of connecting the bumps 430 and the
first substrate pads 422 or the second substrate pads 424 and the
relation between the melting point of the bumps 430 and the
operation temperature of the thermal compression bonding process
are the same as those of the first embodiment, and they will not be
described herein again.
[0056] Then, an underfill layer 450 and a plurality of electrical
contacts 460 are formed at the same relative position and in the
same manner as those of the first embodiment.
[0057] The chip package 400 is completed through the above
steps.
[0058] In view of the above, according to the chip package and the
fabricating method thereof provided by the present invention, the
surface bonding layer on the second substrate pads, which is in an
area not correspondingly connected to the bumps, is removed or
restricted by the solder mask layer, so in the thermal compression
bonding process, the surface bonding layer on the second substrate
pads may not rise along the side of the bumps toward the chip
through the effect of surface tension. Thus, the surface bonding
layer on the second substrate pads does not contaminate the chip,
thereby maintaining the normal operation of the chip package.
[0059] It should be noted that the second substrate pad can be
considered having two regions. In the embodiments related to FIG.
2, the surface bonding layer covers only one region, while in the
embodiments related FIGS. 4. and 6, the surface bonding layer
covers all regions.
[0060] Though the present invention has been disclosed above by a
plurality of embodiments, they are not intended to limit the
invention. Anybody skilled in the art can make some modifications
and variations without departing from the spirit and scope of the
invention. Therefore, the protecting range of the present invention
falls in the appended claims.
* * * * *