U.S. patent application number 11/744992 was filed with the patent office on 2007-09-06 for registration mark within an overlap of dopant regions.
This patent application is currently assigned to ATMEL CORPORATION. Invention is credited to Franz Dietz, Volker Dudek, Michael Graf, Gayle W. JR. Miller, Stefan Schwantes.
Application Number | 20070207589 11/744992 |
Document ID | / |
Family ID | 37804794 |
Filed Date | 2007-09-06 |
United States Patent
Application |
20070207589 |
Kind Code |
A1 |
Dietz; Franz ; et
al. |
September 6, 2007 |
REGISTRATION MARK WITHIN AN OVERLAP OF DOPANT REGIONS
Abstract
A first mark, in a double-well integrated circuit technology, is
formed by a first etching of a first mask layer on top of an ONO
stack. After a first well is doped, a second etching occurs at the
first etching sites in the uppermost layer of oxide of the ONO
stack forming a first alignment artifact. A second mask layer is
applied after removing the first mask layer. A second well doping
occurs at second mask layer etching sites to maintain clearance
between the two wells within active areas and provide an overlap of
the two wells in a frame area. At the first alignment artifact in
the overlap of the two wells, further etchings remove remaining
layers of the ONO stack and remove silicon from the upper most
layer of the semiconductor forming a second registration mark,
which may be covered by a protective layer.
Inventors: |
Dietz; Franz;
(Untereisesheim, DE) ; Dudek; Volker;
(Brackenheim, DE) ; Graf; Michael; (Leutenbach,
DE) ; Schwantes; Stefan; (Heilbronn, DE) ;
Miller; Gayle W. JR.; (Colorado Springs, CO) |
Correspondence
Address: |
SCHNECK & SCHNECK
P.O. BOX 2-E
SAN JOSE
CA
95109-0005
US
|
Assignee: |
ATMEL CORPORATION
2325 Orchard Parkway
San Jose
CA
95131
|
Family ID: |
37804794 |
Appl. No.: |
11/744992 |
Filed: |
May 7, 2007 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11217250 |
Aug 31, 2005 |
7230342 |
|
|
11744992 |
May 7, 2007 |
|
|
|
Current U.S.
Class: |
438/401 |
Current CPC
Class: |
G03F 7/70633 20130101;
G03F 7/70425 20130101; G03F 9/7076 20130101 |
Class at
Publication: |
438/401 |
International
Class: |
H01L 21/76 20060101
H01L021/76 |
Claims
1. A method of fabricating a device with an alignment feature, the
method comprising: applying at least one protective layer onto an
uppermost surface of a substrate; applying a first photoresist on
the at least one protective layer; patterning a plurality of first
openings in the first photoresist; doping the substrate with a
first dopant substantially within the plurality of first openings;
removing the first photoresist; applying a second photoresist on
the at least one protective layer; patterning second openings in
the second photoresist; doping the substrate with a second dopant
substantially within the second openings; aligning the second
openings with the plurality of first openings so as to form an
overlap region of the second dopant with the first dopant; and
etching a registration mark recess through both the at least one
protective layer and a first portion of an upper layer of the
substrate in the overlap region so as to form a registration
mark.
2. The method of claim 1 further comprising: etching a registration
mark artifact in an uppermost portion of the at least one
protective layer within each of the plurality of first
openings.
3. The method of claim 1 further comprising: removing the second
photoresist and the at least one protective layer; and applying a
further at least one protective layer onto the surface of the
substrate and over the registration mark.
4. The method of claim 1 further comprising: applying an ONO stack
on to the surface of the substrate.
5. The method of claim 1 further comprising: removing the second
photoresist and the at least one protective layer; applying a third
photoresist on the substrate; aligning a pattern of dopant windows
in the third photoresist, the alignment being relative to the
registration mark; and doping the substrate with a third
dopant.
6. A method of fabricating a double-well device with an alignment
feature, the method comprising: applying a first layer of oxide, a
layer of silicon nitride, and a second layer of oxide onto an
uppermost surface of a substrate; patterning a plurality of first
openings in a first photoresist on an uppermost surface of the
second layer of oxide; doping the substrate with a first dopant
substantially within the plurality of first openings forming a
first dopant region; removing the first photoresist; patterning
second openings in a second photoresist on an uppermost surface of
the device; doping the substrate with a second dopant substantially
within the second openings forming a second dopant region; aligning
the second openings with the plurality of first openings so as to
form an overlap region of the second dopant region with the first
dopant region; and etching a registration mark recess through the
silicon nitride layer, the first oxide layer, the second layer of
oxide, and a first portion of the upper layer of the substrate in
the overlap region so as to form a registration mark.
7. The method of claim 6 further comprising: etching a registration
mark artifact in the second layer of oxide within each of the
plurality of first openings.
8. The method of claim 6 further comprising: removing the first
layer of oxide, the layer of silicon nitride, and the second layer
of oxide; and applying a third oxide layer over the uppermost
surface of a substrate and over the registration mark.
9. The method of claim 6 further comprising: removing the first
layer of oxide, the layer of silicon nitride, and the second layer
of oxide; applying a third photoresist on the substrate; aligning a
pattern of dopant windows in the third photoresist, the alignment
being relative to the registration mark; and doping the substrate
with a third dopant.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This is a divisional application of pending U.S. patent
application Ser. No. 11/217,250 filed Aug. 31, 2005.
TECHNICAL FIELD
[0002] The present invention relates to the general fabrication of
an integrated circuit. More specifically, the invention is a
registration mark for mask alignment and a method of fabrication of
the mark in a semi-conductor technology.
BACKGROUND ART
[0003] In integrated circuit production, a layer-to-layer alignment
and registration of fabrication masks is critical. The alignment of
one mask layer to another or of a mask layer to a previously
applied dopant is frequently critical to the fabrication of active
devices or to electrical properties such as isolation capabilities,
threshold parameters, or breakdown voltages. A misalignment of a
sequence of fabrication steps may mean that a device is out of
specification or inoperable. Yield and performance numbers for a
device in production may vary significantly causing considerable
cost consequences.
[0004] Typically a device site on a semiconductor wafer will have
alignment or registration marks in the kerf or scribe line area.
These registration marks allow automated or manually adjusted
optical equipment, such as mask alignment tools, to register a mask
layer to the die site. Many interdependencies exist in mask
alignment including a lack of "run-out" (nonlinearity) in the
features across the mask surface as well as an accurate planarity
of the mask relative to the die surface. Variation of these
quantities must be kept to a minimum over a considerable distance
in order for features in the middle of the die area to be rendered
accurately.
[0005] Certain technologies require device dimensions to be
critically positioned in order to meet specifications and perform
as intended. Device performance parameters such as breakdown
voltages, threshold voltages, and electrical isolation capabilities
depend critically on fabrication layer-to-layer registration in
certain integrated circuit technologies such as high-voltage MOS
(HVMOS), DMOS and BCDMOS (Bipolar CMOS-DMOS). These technologies
rely crucially on fabrication alignment to have sufficient
electrical performance characteristics and yield.
[0006] For example, in DMOS technology, a drain-to-source breakdown
voltage (BVDSS) and an "on-channel resistance" (R.sub.DS(ON)) vary
directly with a variation in layer-to-layer registration. What is
needed is a method and structure to allow mask alignment and
registration of the critical layers to be accomplished within
either a die site frame or a die site itself.
DISCLOSURE OF INVENTION
[0007] A double-well integrated circuit technology is fabricated
with an overlap of two dopant regions. Within the overlap region, a
registration mark is fabricated by further etching through
protection layers and an upper layer of a semiconductor substrate
at a first dopant window. Following etching, a passivation layer is
applied. The first dopant window is an artifact of a doping step of
the first well and a first etching of an uppermost protection
layer. The overlap region is formed from two dopants. Improved
alignment capabilities provide commensurate enhancement of critical
device electrical operating parameters that depend on topological
registration. No extra masks are required to fabricate the
registration mark and no additional topological buildup occurs as
with registration marks fabricated with oxide layers. The ability
to avoid extra oxide fabrication means that the wafer remains flat
which enhances the ability to perform subsequent fabrication steps
with a planar surface.
BRIEF DESCRIPTION OF DRAWINGS
[0008] FIGS. 1-8 are exemplary cross-sectional diagrams of a
registration mark formation in a semiconductor technology.
[0009] FIG. 9 is an exemplary process flow diagram of a
registration mark fabrication of the present invention in a
semiconductor technology.
MODES FOR CARRYING OUT THE INVENTION
[0010] With reference to FIG. 1, an exemplary starting
cross-section of a double well technology 100 begins with an oxide
isolation layer 110 positioned on top of a semiconductor substrate
105. A continuous layer of silicon on insulator layer 115 is
produced over the oxide isolation layer 110.
[0011] In a specific exemplary embodiment, the oxide isolation
layer 110 ranges from 3,000 to 20,000 angstroms (.ANG.) of silicon
dioxide (SiO.sub.2). The oxide isolation layer 110 is, for example,
thermally grown on top of the semiconductor substrate 105 if the
substrate 105 is silicon. The silicon on insulator layer 115 is
fabricated on top of the oxide isolation layer 110 to a thickness
ranging from 0.2 to 20 micrometers (.mu.m). The first oxide layer
120 is a 100 .ANG. pad oxide thermally grown on the silicon on
insulator layer 110. 200 .ANG. of silicon nitride (SiN) is applied
upon the first oxide layer 120 to form a silicon nitride layer 125.
Upon the silicon nitride layer 125, a 500 .ANG. layer of oxide is
produced by high-density plasma chemical vapor deposition (HDP-CVD)
to form the second oxide layer 130.
[0012] With reference to FIG. 2, a first photoresist 205 is
applied, for example, 6000 .ANG., on top of the second oxide 130.
The application is performed, for example, both in a frame area 222
and an active area 255. The first photoresist 205 is treated as a
critical layer and patterned to form a plurality of first dopant
windows 215 for nwell regions. First dopant regions 210 are formed
beneath the first thermal oxide 120. Formation of the first dopant
regions 210 is accomplished by, for example, a range of 10 to 1,000
keV of phosphorus doping by ion beam implantation at a dose of
1.times.10.sup.12 to 5.times.10.sup.14 cm.sup.-2 through the first
dopant windows 215 into an upper surface of the silicon on
insulator layer 115. The first dopant regions 210 overlap a
defining edge of the first photoresist 205 by a first lateral
diffusion overlap 235. After the implant, an annealing step
eliminates any lattice damage in the silicon on insulator layer
115.
[0013] With reference to FIG. 3, etched second oxide windows 305
are positioned in the second oxide layer 130. The second oxide
windows 305 are etched in the second oxide 130 at locations of the
first dopant windows 215 (FIG. 2). Remnants of the second oxide
windows 305 are first alignment artifacts for forming a
registration mark (not shown) described infra.
[0014] With reference to FIG. 4, a second photoresist 405 is
applied to the surface of a double well technology device. The
second photoresist 405 is applied to a thickness of, for example,
6000 .ANG. above the second oxide layer 130 and fills the locations
of the second oxide windows 305. The second oxide windows 305
formed at the sites of the first dopant windows 215 forms a
self-aligned layer over the first dopant regions 210 for protection
from subsequent implantation.
[0015] With reference to FIG. 5, a patterned second photoresist 505
resides on top of the second oxide 130 and the silicon nitride 125
after patterning of the second photoresist 405. A correctly
patterned second photoresist 505 assists in forming a subsequent
doped region. The patterned second photoresist 505 forms oxide
dopant windows 510a over the second oxide 130 and nitride dopant
windows 510b over the silicon nitride layer 125. A second dopant
region 515 of an acceptor dopant, for example, is implanted into an
upper surface of the device through both types of dopant windows
510a, 510b. A dose of an acceptor dopant, for example, such as
boron difluoride (BF.sub.2) at about a range of 1.times.10.sup.12
to 5.times.10.sup.14 cm.sup.-2 forms the second dopant region
515.
[0016] The oxide dopant windows 510a are positioned in the active
area 255 and the frame area 222 relative to the first alignment
artifacts. The first alignment artifacts are the second oxide
windows 305 (FIG. 3). In the active area 255, a second oxide window
to oxide dopant window spacing 555 is maintained between edges of
second oxide windows 305 and edges of oxide dopant windows 510a.
The second dopant region 515 overlaps a defining edge of the second
photoresist 505 by a second lateral diffusion overlap 535. The
first dopant region 210 is positioned relative to the second dopant
region 515 by maintaining a first dopant to second dopant spacing
545 as a minimum to ensure that no overlap of the two regions
occurs in the active area 255. The second oxide window to oxide
dopant window spacing 555 is chosen sufficiently large to maintain
the first dopant to second dopant spacing 545.
[0017] Where the second dopant region 515 overlaps the first dopant
region 210 in the frame area 222 (FIG. 2), an overlap region 520 is
formed. In the frame area 222, a nitride dopant window to second
oxide window overlap 525 is maintained between edges of nitride
dopant windows 510b and edges of oxide dopant windows 510a. The
nitride dopant windows 510b are the same first alignment artifacts,
or remnants of the second oxide windows 305 (FIG. 3), mentioned
supra.
[0018] With reference to FIG. 6, a registration mark recess 605 is
formed by etching through the nitride dopant window 510b (FIG. 5),
the first thermal oxide 120, and through the vertical extent of the
overlap region 520. The upper layer on the overlap region 520 is
etched, for example, to a depth of at least 250 .ANG., to form a
lowermost extent of the registration mark recess 605. Geometries of
the etching through the nitride dopant window 510b and the first
thermal oxide 120 combined with the selectivity of a silicon
etchant, ensure that the etching of the upper surface layer of the
overlap region 520 is limited in lateral extent. Therefore, no
etching of the registration mark recess 605 extends laterally past
the overlap region 520.
[0019] With reference to FIG. 7, a registration mark 710 is formed
by removing protective layers and photoresist and by applying a
third oxide layer 720. In a specific exemplary embodiment, the
registration mark 710 is formed by stripping the 6000 .ANG.
critical photoresist, the ONO structure, and applying a 200 .ANG.
third oxide layer 720.
[0020] The ONO structure is removed by the application of a
buffered oxide etch (BOE) and hot phosphoric acid in the sequence
BOE/Hot Phosphoric/BOE. For example, silicon oxide removal is
performed using a BOE solution of six parts 40% NH.sub.4F and one
part 49% HF for an etch rate of about 1200 .ANG./min at 22.degree.
C. A hot phosphoric acid bath of H.sub.3PO.sub.4 in an etchant of
H.sub.3PO.sub.4:CrO.sub.3:NaCN, for example, will remove the
silicon nitride layer but not etch the remaining silicon dioxide
layer. The third oxide layer 720 is grown thermally on top of the
silicon on insulator 115 and covers the registration mark recess
605 (FIG. 6).
[0021] With reference to FIG. 8, a third photoresist 805 is applied
to an upper surface of the third oxide layer 720 and patterned for
a third dopant. The third photoresist 805 is, for example, a 13,300
.ANG. thick resist layer. The patterning occurs relative to the
registration mark 710 within the overlap region 520. A set of third
dopant regions 810 is formed. The third dopant region 810 may be
formed for example, with a 150 keV ion implant of phosphorus and a
dose of 5.4.times.10.sup.12 cm.sup.-2.
[0022] In FIG. 9, an exemplary process flow diagram 900 of a
registration mark formation process begins by applying 905 a
protective stack to an upper surface of a semiconductor substrate
and producing a first dopant region in a device. The first dopant
is produced by applying 910 a first photoresist, patterning 915 the
first photoresist, and doping 920 the device with a first dopant.
The process continues with fabrication of a second dopant by
etching 925 an upper portion of the protective layer, applying 930
a second photoresist, patterning 935 the second photoresist, and
doping 940 the device with a second dopant. Preparation of the area
for the registration mark continues with forming 945 an overlap
region, etching 950 a registration mark recess in the overlap
region, and applying 955 a protective layer to an uppermost surface
of the device, including covering the registration mark recess with
the protective layer.
[0023] Additional exemplary process flow steps for forming a
registration mark continue by utilizing the registration mark for
applying 965 a third photoresist to the uppermost surface of the
device, aligning 970 a pattern of the third photoresist relative to
the registration mark, and doping 975 with a third dopant.
[0024] An improved registration mark has been presented which
requires no additional masks nor uses any further oxide buildup in
its formation. Avoidance of further oxide buildup maintains a
planar wafer surface easing registration of further fabrication
steps. The improved alignment capabilities provide commensurate
enhancement of critical device electrical operating parameters that
depend on topological registration.
[0025] While various process steps have been portrayed within the
present invention in a particular manner, a skilled artisan would
recognize that fabrication steps, application of dopants, and
stripping processes for various layers is readily accomplished with
a variety of different techniques. For instance, a dopant has been
described as being applied within an uppermost surface layer of a
semiconductor device. A skilled artisan would recognize that such a
dopant may be applied as an ion beam implant, diffused from a
dopant gas applied within a chamber at an elevated temperature, or
applied as a spin-on dopant and diffused at an elevated
temperature. An etching process has been described as being
performed to provide critical features in a silicon substrate
through existing layers of silicon nitride, silicon dioxide, and
lightly doped silicon. A skilled artisan would recognize that
etching may be performed by wet chemical processes, ion milling,
and reactive ion etching. An artisan, skilled in the craft, would
also recognize that certain etching processes, such as the wet
chemical processes, are either isotropic or anisotropic in a
directional selectivity nature. While an application of a first and
second dopant has been presented as preceding an etching of an
upper portion of the protective layer or an etching of a
registration mark recess in an overlap region respectively, an
artisan skilled in the field would readily understand that the
order of these two steps are reversible.
[0026] A registration mark has been described as being fabricated
within a double-well technology, being located in a frame area. A
skilled artisan would recognize that the registration mark could
also be located in a scribe line, a kerf area, or the "streets"
between dice. One skilled in the art of semiconductor fabrication
would recognize that a registration mark of the present invention
may be fabricated within any semiconductor process capable of
forming an overlap region of two dopants. A skilled artisan would
also recognize that a registration mark of the present invention is
also able to be located within any region, including an active
area, where, for example, the mark may be utilized for critical
alignment of active layer dopants.
[0027] Furthermore, the skilled artisan would readily understand
how the same registration mark may be fabricated and utilized for
registration of maskable features in a wide variety of
semiconductor regions to register features for well dopants, active
devices, and passive devices. Additionally, a skilled artisan would
be able to conceive of the use of a registration mark of the
present invention to, in effect, align a maskless fabrication step
that in turn relied on a directly registered process step utilizing
the present invention. Likewise, the skilled artisan would
recognize the applicability of the present invention to a substrate
that is not a semiconductor structure, the present invention would
be applicable to any substrate amenable to implantation,
deposition, coatings, etching, or equivalent fabrication processes
to those exemplified.
* * * * *