Schwantes; Stefan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Schwantes; Stefan.The latest application filed is for "method and system for incorporating high voltage devices in an eeprom".

Company Profile

0.9.20

Schwantes; Stefan - Heilbronn DE
Schwantes; Stefan - Heibronn DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and system for incorporating high voltage devices in an EEPROM Grant 8,093,640 - Schwantes , et al. January 10, 2	2012-01-10
Lateral DMOS transistor and method for the production thereof Grant 7,973,333 - Dietz , et al. July 5, 2	2011-07-05
Electrostatic discharge (ESD) protection structure and a circuit using the same Grant 7,848,070 - Schwantes , et al. December 7, 2	2010-12-07
Method And System For Incorporating High Voltage Devices In An Eeprom App 20090273883 - Schwantes; Stefan ; et al.	2009-11-05
Semiconductor array and method for manufacturing a semiconductor array App 20090258472 - Florian; Tobias ; et al.	2009-10-15
Method and system for incorporating high voltage devices in an EEPROM Grant 7,560,334 - Schwantes , et al. July 14, 2	2009-07-14
Semiconductor array and method for manufacturing a semiconductor array App 20090160009 - Dietz; Franz ; et al.	2009-06-25
DMOS transistor with optimized periphery structure Grant 7,521,756 - Dietz , et al. April 21, 2	2009-04-21
High-voltage field-effect transistor Grant 7,504,692 - Dudek , et al. March 17, 2	2009-03-17
Method For Manufacturing A Semiconductor Arrangement, Use Of A Trench Structure, And Semiconductor Arrangement App 20090057911 - Hoffmann; Thomas ; et al.	2009-03-05
Dmos Device With Sealed Channel Processing App 20080290426 - Miller; Gayle W. ; et al.	2008-11-27
Electrostatic Discharge (esd) Protection Structure And A Circuit Using The Same App 20080278874 - Schwantes; Stefan ; et al.	2008-11-13
DMOS device with sealed channel processing Grant 7,407,851 - Miller , et al. August 5, 2	2008-08-05
Electrostatic discharge (ESD) protection structure and a circuit using the same Grant 7,402,846 - Schwantes , et al. July 22, 2	2008-07-22
High Voltage Vertically Oriented Eeprom Device App 20080108212 - Moss; Thomas S. ; et al.	2008-05-08
Semiconductor protective structure for electrostatic discharge App 20080006847 - Grombach; Peter ; et al.	2008-01-10
Method for producing a semiconductor arrangement, semiconductor arrangement and its application App 20070290226 - Berntgen; Juergen ; et al.	2007-12-20
High-voltage field-effect transistor and method for manufacturing a high-voltage field-effect transistor App 20070262376 - Dudek; Volker ; et al.	2007-11-15
Lateral DMOS transistor and method for the production thereof App 20070235779 - Dietz; Franz ; et al.	2007-10-11
DMOS device with sealed channel processing App 20070221965 - Miller; Gayle W. ; et al.	2007-09-27
Registration Mark Within An Overlap Of Dopant Regions App 20070207589 - Dietz; Franz ; et al.	2007-09-06
Semiconductor array and method for manufacturing a semiconductor array App 20070164443 - Florian; Tobias ; et al.	2007-07-19
DMOS transistor with optimized periphery structure App 20070132019 - Dietz; Franz ; et al.	2007-06-14
Registration mark within an overlap of dopant regions Grant 7,230,342 - Dietz , et al. June 12, 2	2007-06-12
Electrostatic discharge (ESD) protection structure and a circuit using the same App 20070120190 - Schwantes; Stefan ; et al.	2007-05-31
Method and system for incorporating high voltage devices in an EEPROM App 20070090432 - Schwantes; Stefan ; et al.	2007-04-26
Registration mark within an overlap of dopant regions App 20070048959 - Dietz; Franz ; et al.	2007-03-01
Integrated circuit and method for manufacturing an integrated circuit App 20060278923 - Dudek; Volker ; et al.	2006-12-14
MOS transistor with reduced kink effect and method for the manufacture thereof App 20060110876 - Dudek; Volker ; et al.	2006-05-25

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