U.S. patent application number 11/645039 was filed with the patent office on 2007-07-26 for three-dimensional package and method of making the same.
Invention is credited to Po-Jen Cheng, Min-Lung Huang, Chian-Chi Lin, Jian-Wen Lo, Ching-Huei Su, Wei-Chung Wang, Kuo-Chung Yee.
Application Number | 20070172983 11/645039 |
Document ID | / |
Family ID | 38286045 |
Filed Date | 2007-07-26 |
United States Patent
Application |
20070172983 |
Kind Code |
A1 |
Huang; Min-Lung ; et
al. |
July 26, 2007 |
Three-dimensional package and method of making the same
Abstract
The present invention relates to a three-dimensional package and
a method of making the same. The three-dimensional package
comprises a first wafer, at least one first hole, a first isolation
layer, a first conductive layer, a first solder, a second wafer, at
least one second hole, a second isolation layer, a second
conductive layer, and a second solder. The first wafer has at least
one first pad and a first protection layer exposing the first pad.
The first hole penetrates the first wafer. The first isolation
layer is disposed on the side wall of the first hole. The lower end
of the first conductive layer extends below the surface of the
first wafer. The first solder is disposed in the first hole, and is
electrically connected to the first pad via the first conductive
layer. The second wafer has at least one second pad and a second
protection layer exposing the second pad. The second hole
penetrates the second wafer. The second isolation layer is disposed
on the side wall of the second hole. The lower end of the second
conductive layer extends to below the surface of the second wafer
and contacts the upper end of the first solder. The second solder
is disposed in the second hole and is electrically connected to the
second pad via the second conductive layer.
Inventors: |
Huang; Min-Lung; (Kaohsiung,
TW) ; Wang; Wei-Chung; (Kaohsiung, TW) ;
Cheng; Po-Jen; (Kaohsiung, TW) ; Yee; Kuo-Chung;
(Kaohsiung, TW) ; Su; Ching-Huei; (Kaohsiung,
TW) ; Lo; Jian-Wen; (Kaohsiung, TW) ; Lin;
Chian-Chi; (Kaohsiung, TW) |
Correspondence
Address: |
VOLENTINE & WHITT PLLC
ONE FREEDOM SQUARE, 11951 FREEDOM DRIVE SUITE 1260
RESTON
VA
20190
US
|
Family ID: |
38286045 |
Appl. No.: |
11/645039 |
Filed: |
December 26, 2006 |
Current U.S.
Class: |
438/109 |
Current CPC
Class: |
H01L 21/76898 20130101;
H01L 2924/0002 20130101; H01L 2924/0002 20130101; H01L 25/0657
20130101; H01L 2225/06513 20130101; H01L 2225/06527 20130101; H01L
25/50 20130101; H01L 2225/06541 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
438/109 |
International
Class: |
H01L 21/00 20060101
H01L021/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 25, 2006 |
TW |
095102836 |
Claims
1. A three-dimensional package, comprising: a first unit,
comprising: a first wafer, having a first surface and a second
surface, the first surface having at least one first pad and a
first protection layer exposing the first pad; at least one first
hole, penetrating the first wafer; a first isolation layer,
disposed on the side wall of the first hole; a first conductive
layer, covering the first pad, a part of the first protection
layer, and the first isolation layer, wherein the lower end of the
first conductive layer extends below the second surface of the
first wafer; and a first solder, disposed in the first hole and
electrically connected to the first pad via the first conductive
layer; and a second unit stacked on the first unit, comprising: a
second wafer, having a first surface and a second surface, wherein
the first surface has at least one second pad and a second
protection layer exposing the second pad; at least one second hole
penetrating the second wafer; a second isolation layer, disposed on
the side wall of the second hole; a second conductive layer,
covering the second pad, a part of the second protection layer, and
the second isolation layer, wherein the lower end of the second
conductive layer extends to below the second surface of the second
wafer and contacts the upper end of the first solder, and a second
solder, disposed in the second hole and electrically connected to
the second pad via the second conductive layer.
2. The three-dimensional package according to claim 1, wherein the
first hole penetrates the first pad.
3. The three-dimensional package according to claim 1, wherein the
second hole penetrates the second pad.
4. The three-dimensional package according to claim 1, wherein the
first unit further comprises a first passivation layer covering the
first conductive layer.
5. The three-dimensional package according to claim 1, wherein the
second unit further comprises a second passivation layer covering
the second conductive layer.
6. The three-dimensional package according to claim 1, wherein the
first unit further comprises a first barrier layer covering the
lower end of the first conductive layer.
7. The three-dimensional package according to claim 1, wherein the
second unit further comprises a second barrier layer covering the
lower end of the second conductive layer.
8. The three-dimensional package according to claim 1, further
comprising at least one solder ball disposed at the lower end of
the first conductive layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a package and a method of
making the same, and more particularly to a three-dimensional
package and a method of making the same.
[0003] 2. Description of the Related Art
[0004] Referring to FIG. 1, it shows a schematic view of a
three-dimensional package before reflow disclosed in U.S. Pat. No.
4,499,655. The conventional three-dimensional package 1 comprises a
first unit 10 and a second unit 20. The first unit 10 comprises a
first wafer 11, at least one first hole 12, a first conductive
layer 13 and a first solder 14. The first wafer 11 has a first
surface 111 and a second surface 112. The first surface 111 has at
least one first pad (not shown) and a first protection layer 113
exposing the first pad. The first hole 12 penetrates the first
wafer 11. The first conductive layer 13 is disposed on the side
wall of the first hole 12 and covers the first pad and the first
protection layer 113. The first solder 14 is disposed in the first
hole 12 and is electrically connected to the first pad via the
first conductive layer 13. The upper end of the first solder 14
extends above the first surface 111 of the first wafer 11, and the
lower end extends below the second surface 112 of the first wafer
11.
[0005] The second unit 20 is stacked on the first unit 10. The
second unit 20 comprises a second wafer 21, at least one second
hole 22, a second conductive layer 23 and a second solder 24. The
second wafer 21 has a first surface 211 and a second surface 212.
The first surface 211 has at least one second pad (not shown) and a
second protection layer 213 exposing the second pad. The second
hole 22 penetrates the second wafer 21. The second conductive layer
23 is disposed on the side wall of the second hole 22 and covers
the second pad and the second protection layer 213. The second
solder 24 is disposed in the second hole 22 and is electrically
connected to the second pad via the second conductive layer 23. The
upper end of the second solder 24 extends above the first surface
211 of the second wafer 21, and the lower end of the second solder
24 extends below the second surface 212 of the second wafer 21. The
lower end of the second solder 24 is aligned with and contacts the
upper end of the first solder 14. After performing a reflow
process, the first unit 10 and the second unit 20 are joined to
form a conventional three-dimensional package 1, as shown in FIG.
2.
[0006] In the conventional three-dimensional package 1, the first
solder 14 and the second solder 24 are formed by disposing the
first wafer 11 and the second wafer 21 above a solder bath, and the
solder enter the first hole 12 and the second hole 22 according to
the capillary phenomenon so as to form the first solder 14 and the
second solder 24.
[0007] The disadvantages of the conventional three-dimensional
package 1 are described as follows. As the first solder 14 and the
second solder 24 are formed according to the capillary phenomenon,
the upper and the lower ends of the foregoing solders are in a
hemispherical shape (FIG. 1). As such, when the first unit 10 and
the second unit 20 are aligned and joined, alignment becomes more
difficult and the joining between the first unit 10 and the second
unit 20 after reflow is not stable. Moreover, after the joining of
the first unit 10 and the second unit 20, the overall height cannot
be effectively reduced due to the excess hemispherical solders.
[0008] Therefore, it is necessary to provide a three-dimensional
package and a method of making the same to solve the above
problems.
SUMMARY OF THE INVENTION
[0009] The main objective of the invention is to provide a method
of making a three-dimensional package, which comprises the
following steps:
[0010] (a) providing a wafer, having a first surface and a second
surface, the first surface having at least one pad and a protection
layer exposing the pad;
[0011] (b) forming at least one blind hole on the first surface of
the wafer;
[0012] (c) forming an isolation layer on the side wall of the blind
hole;
[0013] (d) forming a conductive layer covering the pad, the
protection layer, and the isolation layer;
[0014] (e) forming a dry film on the conductive layer, wherein the
dry film has an opening at the position corresponding to the blind
hole;
[0015] (f) filling the blind hole with a solder;
[0016] (g) removing the dry film;
[0017] (h) patterning the conductive layer;
[0018] (i) removing a part of the second surface of the wafer and a
part is of the isolation layer, so as to expose a part of the
conductive layer;
[0019] (j) stacking a plurality of the wafers, so as to perform the
reflow process; and
[0020] (k) cutting the stacked wafers, so as to form a plurality of
three-dimensional packages.
[0021] As such, the lower end of the conductive layer is exposed
below the second surface of the wafer. Therefore, during the reflow
process after stacking, the lower end of the conductive layer is
inserted into the solder of the lower wafer, so as to enhance the
joint between the conductive layer and the solder, and effectively
reduce the overall height of the three-dimensional package after
joining.
[0022] Another objective of the present invention is to provide a
three-dimensional package, which comprises a first unit and a
second unit. The first unit comprises a first wafer, at least one
first hole, a first isolation layer, a first conductive layer, and
a first solder.
[0023] The first wafer has a first surface and a second surface.
The first surface has at least one first pad and a first protection
layer exposing the first pad. The first hole penetrates the first
wafer. The first isolation layer is disposed on the side wall of
the first hole. The first conductive layer covers the first pad, a
part of the first protection layer, and the first isolation layer.
The lower end of the first conductive layer extends below the
second surface of the first wafer. The first solder is disposed in
the first hole, and is electrically connected to the first pad via
the first conductive layer.
[0024] The second unit is stacked on the first unit. The second
unit comprises a second wafer, at least one second hole, a second
isolation layer, a second conductive layer, and a second solder.
The second wafer has a first surface and a second surface. The
first surface has at least one second pad and a second protection
layer exposing the second pad. The second hole penetrates the
second wafer. The second isolation layer is disposed on the side
wall of the second hole. The second conductive layer covers the
second pad, a part of the second protection layer, and the second
isolation layer. The lower end of the second conductive layer
extends to below the second surface of the second wafer and
contacts the upper end of the first solder. The second solder is
disposed in the second hole and is electrically connected to the
second pad via the second conductive layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] FIG. 1 shows a schematic view of the three-dimensional
package before reflow disclosed in U.S. Pat. No. 4,499,655;
[0026] FIG. 2 shows a schematic view of the three-dimensional
package after reflow disclosed in U.S. Pat. No. 4,499,655;
[0027] FIG. 3 shows a schematic flow chart of the method for making
a three-dimensional package according to the first embodiment of
the present invention;
[0028] FIGS. 4 to 17 show the schematic views of each step of the
method of making a three-dimensional package according to the first
embodiment of the present invention;
[0029] FIG. 18 shows a schematic flow chart of the method for
making a three-dimensional package according to the second
embodiment of the present invention;
[0030] FIGS. 19 to 21 show the schematic views of a part of the
steps of the method for making a three-dimensional package
according to the second embodiment of the present invention;
and
[0031] FIG. 22 shows a cross-sectional view of the
three-dimensional package according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0032] Referring to FIG. 3, it shows a schematic flow chart of the
method for making a three-dimensional package according to the
first embodiment of the present invention. Referring to FIGS. 4 to
17, the schematic views of each step of the method for making a
three-dimensional package according to the first embodiment of the
present invention are shown. First, referring to FIGS. 3 and 4, as
shown in step S301, a wafer 31 is provided. The wafer 31 has a
first surface 311 and a second surface 312. The first surface 311
has at least one pad 32 and a protection layer 33 exposing the pad
32.
[0033] Then, referring to FIGS. 3 and 5, as shown in step S302, at
least one blind hole 34 is formed in the first surface 311 of the
wafer 31. In the embodiment, the blind hole 34 is disposed beside
the pad 32. However, in other applications, the blind hole 34 can
penetrate the pad 32.
[0034] Next, referring to FIGS. 3 and 6, as shown in step S303, an
isolation layer 35 is formed on the side wall of the blind hole
34.
[0035] Afterward, referring to FIGS. 3 and 7, as shown in step
S304, a conductive layer 36 is formed to cover the pad 32, the
protection layer 33, and the isolation layer 35. The conductive
layer 36 is made of Ti, Cu, Cu/Ti alloy, or other metals.
[0036] Then, referring to FIGS. 3 and 8, as shown in step S305, a
dry film 37 is formed on the conductive layer 36. The dry film 37
has an opening 371 at the position corresponding to the blind hole
34.
[0037] After that, referring to FIGS. 3 and 9, preferably, as shown
in step S306, the blind hole 34 is filled with a solder 38. In the
embodiment, the blind hole 34 is filled with the solder 38 by
plating. However, it should be understood that the blind hole 34
can be filled with the solder 38 by other manners.
[0038] Then, referring to FIGS. 3 and 10, as shown in step S307,
the dry film 37 is removed, and the conductive layer 36 is
patterned.
[0039] Afterward, referring to FIGS. 3 and 11, preferably, as shown
in step S308, a passivation layer 39 is formed on the conductive
layer 36 to protect the patterned conductive layer 36. The
passivation layer 39 can be formed by any conventional manners.
Moreover, it should be understood that this step is optional.
[0040] Then, as shown in step S309, a part of the second surface
312 of the wafer 31 and a part of the isolation layer 35 are
removed to expose a part of the conductive layer 36. Referring to
FIG. 12, in the present embodiment, the second surface 312 of the
wafer 31 is first ground by means of backside grinding until the
second surface 312 and the lower end of the isolation layer 35 are
at the same level, i.e., the lower end of the isolation layer 35 is
exposed on the second surface 312. Then, the second surface 312 of
the wafer 31 and the lower end of the isolation layer 35 are etched
to expose the lower end of the conductive layer 36. At this moment,
the lower end of the conductive layer 36 extends below the second
surface 312 of the wafer 31, as shown in FIG. 13. However, it
should be understood that in other applications, the second surface
312 of the wafer 31 can be directly etched to expose the lower end
of the conductive layer 36, without using the backside grinding
method.
[0041] Afterward, referring to FIGS. 3 and 14, preferably, as shown
in step S310, a barrier layer 40 is formed on the lower end of the
conductive layer 36, and covers the lower end of the exposed
conductive layer 36. The barrier layer 40 is Ni, Cr, Cr/Cu alloy,
or other metals. It should be understood that this step is
optional. Moreover, preferably, a lower solder 41 is further formed
below the barrier layer 40 or the conductive layer 36 and is
attached to the barrier layer 40 or the lower end of the exposed
conductive layer 36. It should be understood that this step is also
optional.
[0042] Next, referring to FIGS. 3 and 15, as shown in step S311, a
plurality of the wafers 31 are stacked. The conductive layers 36
and the solders 38 of the upper and lower wafers 31 are aligned
with each other.
[0043] Then, referring to FIGS. 3 and 16, as shown in step S312,
the reflow process is performed to make the wafers 31 joined by
welding the conductive layer 36 and the solder 38.
[0044] Finally, referring to FIGS. 3 and 17, as shown in step S313,
the stacked wafer 31 is cut to form a plurality of
three-dimensional package structures 42. Preferably, as shown in
step S314, at least one solder ball 43 is formed below the
three-dimensional package structure 42. The solder ball 43 is
disposed on the lower end of the conductive layer 36 in the lower
wafer 31. It should be understood that this step is optional.
[0045] Referring to FIG. 18, it shows the schematic flow chart of
the method for making a three-dimensional package structure
according to the second embodiment of the present invention. The
steps S401 to S410 are identical to the steps S301 to S310 of the
first embodiment. The difference between the second embodiment and
the first embodiment is described as follows. In the step S411 of
the present embodiment, the wafer 31 is cut to form a plurality of
units 44, 45, as shown in FIG. 19. Then, in step S412, the units
44, 45 are stacked, wherein the conductive layers 36 and the
solders 38 of the upper and the lower wafers 31 are aligned with
each other, as shown in FIG. 20. Finally, in step S413, the reflow
process is performed to form a plurality of three-dimensional
package structures 42, as shown in FIG. 21. The three-dimensional
package structure 42 (FIG. 21) made according to this embodiment is
identical to the three-dimensional package structure 42 (FIG. 17)
made according to the first embodiment.
[0046] Preferably, in step S414, at least one solder ball 43 is
formed below the three-dimensional package structure 42. The solder
ball 43 is disposed on the lower end of the conductive layer 36 in
the lower wafer 31. It should be understood that this step is
optional.
[0047] Referring to FIG. 22, it shows a cross-sectional view of the
three-dimensional package of the present invention. The
three-dimensional package 5 in this figure is identical to the
three-dimensional package 42 in FIGS. 17 and 21. However, for the
convenience of illustration, the identical elements are designated
by different reference numbers. The three-dimensional package 5
comprises a first unit 50 and a second unit 60. The first unit 50
comprises a first wafer 51, at least one first hole 52, a first
isolation layer 53, a first conductive layer 54, and a first solder
55.
[0048] The first wafer 51 is a wafer or a chip, and has a first
surface 511 and a second surface 512. The first surface 511 has at
least one first pad 513 and a first protection layer 514 exposing
the first pad 513. The first hole 52 penetrates the first wafer 51.
In the present embodiment, the first hole 52 is disposed beside the
first pad 513. However, in other applications, the first hole 52
can penetrate the first pad 513.
[0049] The first isolation layer 53 is disposed on the side wall of
the first hole 52. The first conductive layer 54 covers the first
pad 513, a part of the first protection layer 514, and the first
isolation layer 53. The lower end of the first conductive layer 54
extends below the lower end of the second surface 512 of the first
wafer 51. Preferably, the first unit 50 further comprises a first
barrier layer (not shown) covering the lower end of the first
conductive layer 54.
[0050] The first solder 55 is disposed inside the first hole 52,
and is electrically connected to the first pad 513 via the first
conductive layer 54. Preferably, a passivation layer (not shown) is
further disposed above the first conductive layer 54 and covers the
first conductive layer 54 to protect the first conductive layer
54.
[0051] The second unit 60 is stacked above the first unit 50. The
second unit 60 comprises a second wafer 61, at least one second
hole 62, a second isolation layer 63, a second conductive layer 64,
and a second solder 65. The second wafer 61 is a wafer or a chip,
and has a first surface 611 and a second surface 612. The first
surface 611 has at least one second pad 613 and a second protection
layer 614 exposing the second pad 613. The second hole 62
penetrates the second wafer 61. In the present embodiment, the
second hole 62 is disposed beside the second pad 613. However, in
other applications, the second hole 62 can penetrate the second pad
613.
[0052] The second isolation layer 63 is dispose on the side wall of
the second hole 62. The second conductive layer 64 covers the
second pad 613, a part of the second protection layer 614, and the
second isolation layer 63. The lower end of the second conductive
layer 64 extends below the second surface 612 of the second wafer
61 and contacts the upper end of the first solder 55. Preferably,
the second unit 60 further comprises a second barrier layer (not
shown) covering the lower end of the second conductive layer
64.
[0053] The second solder 65 is disposed inside the second hole 62
and is electrically connected to the second pad 613 via the second
conductive layer 64. Preferably, a passivation layer (not shown) is
disposed above the second conductive layer 64 and covers the second
conductive layer 64 to protect the second conductive layer 64.
[0054] Preferably, the three-dimensional package structure 5
further comprises at least one solder ball 43 disposed on the lower
end of the first conductive layer 54.
[0055] In the three-dimensional package structure 5, as the lower
end of the second conductive layer 64 is exposed below the second
surface 612 of the second unit 60, during the reflow process, the
lower end of the second conductive layer 64 is inserted into the
first solder 55, so as to enhance the joint between the second
conductive layer 64 and the first solder 55. Further, the first
hole 52 and the second hole 62 can be designed as a taper shape to
enhance the foregoing joint. Moreover, the lower end of the second
conductive layer 64 is inserted into the first solder 55, such that
the overall height of the three-dimensional package 5 after joining
can be effectively reduced.
[0056] While several embodiments of the present invention have been
illustrated and described, various modifications and improvements
can be made by those skilled in the art. The embodiments of the
present invention are therefore described in an illustrative but
not restrictive sense. It is intended that the present invention
may not be limited to the particular forms as illustrated, and that
all modifications which maintain the spirit and scope of the
present invention are within the scope as defined in the appended
claims.
* * * * *