U.S. patent application number 11/641986 was filed with the patent office on 2007-05-03 for ultrathin leadframe bga circuit package.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Setho Sing Fee, Tan Yong Kian, Teck Kheng Lee.
Application Number | 20070099344 11/641986 |
Document ID | / |
Family ID | 29212570 |
Filed Date | 2007-05-03 |
United States Patent
Application |
20070099344 |
Kind Code |
A1 |
Lee; Teck Kheng ; et
al. |
May 3, 2007 |
Ultrathin leadframe BGA circuit package
Abstract
A circuit package is formed using a leadframe. The leadframe is
formed or etched to align a plurality of bond pad structures above
a reference plane while supporting leadframe fingers are positioned
below the reference plane. Jumper wires are wirebonded between
terminals on the die and the bond pads to form a package
subassembly. The subassembly is encapsulated and then background to
remove the leadframe fingers and surrounding frame. The bond pads
which remain embedded in the encapsulation material are exposed on
the lower surface of the package for connection to further
conductors.
Inventors: |
Lee; Teck Kheng; (Singapore,
SG) ; Kian; Tan Yong; (Singapore, SG) ; Fee;
Setho Sing; (Singapore, SG) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG, WOESSNER & KLUTH, P.A.
P.O. BOX 2938
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
29212570 |
Appl. No.: |
11/641986 |
Filed: |
December 18, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10931363 |
Aug 31, 2004 |
7183134 |
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11641986 |
Dec 18, 2006 |
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10233159 |
Aug 29, 2002 |
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10931363 |
Aug 31, 2004 |
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Current U.S.
Class: |
438/106 ;
257/E23.037; 257/E23.047; 257/E23.049 |
Current CPC
Class: |
H01L 23/49551 20130101;
H01L 23/3128 20130101; H01L 2224/85399 20130101; H01L 23/3107
20130101; H01L 21/56 20130101; H01L 23/49503 20130101; H01L
2224/48257 20130101; H01L 2224/48095 20130101; H01L 2924/14
20130101; H01L 2924/00014 20130101; H01L 2224/05599 20130101; H01L
2224/45099 20130101; H01L 23/49558 20130101; H01L 24/48 20130101;
H01L 21/4832 20130101; H01L 2224/73265 20130101; H01L 2224/48091
20130101; H01L 2924/15311 20130101; H01L 2224/49433 20130101; H01L
2924/181 20130101; H01L 2224/48247 20130101; H01L 21/568 20130101;
H01L 2224/48091 20130101; H01L 2924/00014 20130101; H01L 2224/48095
20130101; H01L 2924/00014 20130101; H01L 2924/181 20130101; H01L
2924/00012 20130101; H01L 2224/85399 20130101; H01L 2924/00014
20130101; H01L 2224/05599 20130101; H01L 2924/00014 20130101; H01L
2924/00014 20130101; H01L 2224/45015 20130101; H01L 2924/207
20130101; H01L 2924/00014 20130101; H01L 2224/45099 20130101; H01L
2924/14 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
438/106 |
International
Class: |
H01L 21/00 20060101
H01L021/00 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 19, 2002 |
SG |
200202330-7 |
Claims
1. A method for forming an integrated circuit package, comprising:
forming a leadframe having at least one bond pad and a support
member coupled to the bond pad and extending away from the bond
pad, the bond pad and the support member formed from a conductive
material having a lower surface that defines a reference plane;
positioning a portion of the support member extending away from the
bond pad on a first side of the reference plane; positioning a die
adjacent the bond pad with a lower surface of the die positioned on
an opposing second side of the reference plane; coupling a terminal
on the die to the bond pad; encapsulating the die, the bond pad and
the support member in an interstitial material; and removing at
least a portion of the interstitial material on the first side of
the reference plane to expose a lower face of the bond pad.
2. The method of claim 1, wherein positioning a portion of the
support member extending away from the bond pad on a first side of
the reference plane further comprises deforming the leadframe to
position the portion of the support member onto the first side of
the reference plane.
3. The method of claim 2, wherein a portion of a length of the
support members is fixably adhered to a support surface.
4. The method of claim 1, wherein positioning a portion of the
support member extending away from the bond pad on a first side of
the reference plane further comprises selectively etching portions
of the leadframe to reduce a dimension of the support member to
position an upper surface of the support member on the first side
of the reference plane.
5. The method of claim 1, wherein positioning a die further
comprises coupling the die to a die pad having a lower surface
positioned on the second side of the reference plane.
6. The method of claim 1, wherein coupling a terminal on the die to
the bond pad further comprises wirebonding a jumper wire between
the terminal and the bond pad.
7. The method of claim 1, wherein removing at least a portion of
the interstitial material further comprises mechanically grinding
the interstitial material.
8. A method for forming an integrated circuit package, comprising:
forming a leadframe having a frame member enclosing a space for
receiving a semiconductor integrated circuit die, the frame member
having at least one finger coupled to the frame member and
extending into the space and having a bond pad configured to be
coupled to the die; positioning a die in the space and coupling the
bond pad to a terminal on the die; offsetting a surface of the
frame member and at least a portion of a length of the finger to be
positioned below a lower one of the die and the bond pad; providing
an interstitial material that encapsulates the leadframe and the
die; and removing a portion of the interstitial material to define
a package to expose the bond pad.
9. The method of claim 8, wherein the leadframe further comprises a
die pad; and further wherein positioning a die comprises bonding
the die to the die pad.
10. The method of claim 9, wherein bonding the die to the die pad
further comprises fixably adhering a surface of the die to the die
pad.
11. A method comprising: forming a leadframe having at least one
finger coupled to a frame portion that encloses the finger, an end
portion of the finger supporting a bond pad; positioning at least a
portion of the finger below a reference plane defined by a lower
surface of the bond pad; coupling a die to a die pad approximately
aligned with the reference plane; fixably adhering a portion of the
leadframe to a support surface; coupling a terminal on the die to
the bond pad; encapsulating the die, the die pad, the bond pad and
the at least a portion of the finger by providing an interstitial
material; and removing a portion of the interstitial material below
the reference plane to expose a surface of the bond pad.
12. The method of claim 11, wherein coupling a terminal on the die
to the bond pad further comprises wirebonding a conductor between
the terminal and the bond pad.
13. The method of claim 11, wherein positioning at least a portion
of the finger below a reference plane further comprises deforming
the leadframe to move the portion of the finger below the reference
plane.
14. The method of claim 11, wherein positioning at least a portion
of the finger below a reference plane further comprises etching the
portion of the finger to position a surface of the finger below the
reference plane.
15. A method, comprising: forming a leadframe having a frame
portion with at least one finger extending inwardly from the frame
portion, the finger supporting a bond pad; placing a portion of the
finger below a reference plane defined by a surface of the bond
pad; mounting a die on a die pad proximate to the reference plane;
coupling a terminal on the die to the bond pad; and encapsulating
the die, the die pad, the at least one bond pad and the portion of
the finger with an encapsulating material to form an integrated
circuit package; and removing encapsulating material below the
reference plane to expose a surface of the bond pad.
16. The method of claim 15, wherein removing encapsulating material
comprises grinding the integrated circuit package.
17. The method of claim 16, further comprising grinding a portion
of the finger.
18. The method of claim 14, wherein removing encapsulating material
further comprises singulating the integrated circuit package.
19. A method, comprising forming a leadframe having an at least
partially surrounding frame portion with at least one finger
extending inwardly from the frame portion, a portion of the finger
supporting a bond pad; placing the portion of the finger below a
reference plane defined by a lower surface of the bond pad by
etching the portion of the finger so that the lower surface of the
bond pad lies below a surface of a die pad; mounting a die on the
die pad, wherein a lower surface of the die pad is positioned
adjacent to the reference plane; coupling a terminal on the die to
the bond pads; encapsulating the die, the die pad, the bond pads
and the portions of the finger with an encapsulating material to
form an integrated circuit package; and removing the encapsulating
material adjacent the reference plane to expose the bond pad.
20. The method of claim 19, wherein placing the portion of the
finger below a reference plane defined by a lower surface of the
bond pad comprises upsetting the bond pad and the die pad relative
to the finger and the at least partially surrounding frame.
21. The method of claim 19, wherein mounting the die on the die pad
further comprises adhering the die to the die pad with a double
backed adhesive tape.
22. The method of claim 19, wherein mounting the die on the die pad
further comprises securing the die to the die pad using an adhesive
material.
23. The method of claim 19, further comprising bonding a solder
ball to a surface of the bond pad.
24. The method of claim 23, further comprising affixing the solder
ball to a terminal on a motherboard to couple the die to a
system.
25. The method of claim 19, further comprising applying a layer of
a metal to the die pad.
26. A method of providing an electrical contact for a semiconductor
package, comprising: including the electrical contact in a
leadframe structure; encapsulating a first portion of the leadframe
structure that includes the electrical contact while a second
portion of the leadframe structure remains non-encapsulated;
removing the second portion of the leadframe structure from the
first portion; and exposing the electrical contact.
27. The method of claim 26, wherein encapsulating a first portion
of the leadframe structure comprises providing an interstitial
material to the first portion.
28. The method of claim 26, wherein removing the second portion of
the leadframe structure comprises grinding the second portion until
the electrical contact is uncovered.
29. The method of claim 28, wherein grinding the second portion
comprises grinding a bottom surface of the second portion.
30. A method of modifying an in-process package that includes a
leadframe structure, comprising: encapsulating the in-process
package to provide a first portion of the leadframe structure that
is coupled to a semiconductor die and a second portion extending
away from the semiconductor die; separating the first portion of
the leadframe structure from the second portion of the leadframe
structure; and exposing a region within a perimeter of the
interstitial material that includes the interstitial material and
the first portion.
31. The method of claim 30, wherein encapsulating the in-process
package comprises providing an interstitial material to the
in-process package.
32. The method of claim 30, wherein separating the first portion of
the leadframe structure from the second portion of the leadframe
structure comprises grinding the in-process package to remove the
second portion.
33. The method of claim 30, wherein exposing a region comprises
revealing an electrical contact that is coupled to the
semiconductor die.
34. A method of modifying an in-process package that includes a
leadframe structure, comprising: encapsulating the in-process
package to define a first portion of the leadframe structure that
is coupled to a semiconductor die and a second portion extending
away from the semiconductor die; removing at least part of the
second portion of the leadframe structure; and exposing at least
one electrical contact positioned within the first portion.
35. The method of claim 34, wherein removing at least part of the
second portion comprises subjecting the second portion of the
in-process package to a material removing operation.
36. The method of claim 35, wherein subjecting the second portion
of the in-process package to a material removing operation
comprises grinding the second portion of the in-process
package.
37. The method of claim 34, wherein encapsulating the in-process
package comprises providing an interstitial material to the
in-process package.
38. A package, comprising: an interstitial material encapsulating
the package; and at least a portion of a leadframe structure that
is flush with the interstitial material.
39. The package of claim 38, wherein the interstitial material
comprises a moldable material.
40. The package of claim 39, wherein the moldable material
comprises a thermosetting material.
41. The package of claim 38, wherein the leadframe structure
comprises one or more bond pads.
42. The package of claim 41, wherein the leadframe structure
comprises a first portion that includes the one or more bond pads,
and a second portion extending outwardly from the first
portion.
43. The package of claim 38, wherein the interstitial material
defines a perimeter of the package, and the leadframe structure
extends at least to the perimeter of the package.
44. The package of claim 43, wherein the leadframe structure does
not extend beyond the perimeter of the package.
45. The package of claim 38, wherein the package comprises an
in-process package.
46. The package of claim 38, wherein the package further comprises
a semiconductor die.
47. The package of claim 46, wherein the package comprises a die
pad region that retains the semiconductor die.
Description
[0001] This application is a Continuation of U.S. application Ser.
No. 10/931,363, filed Aug. 31, 2004, which is a Divisional of U.S.
application Ser. No. 10/233,159, filed Aug. 29, 2002, which claims
priority under 35 U.S.C. 119 from Singapore application No.
200202330-7, filed Apr. 19, 2002, all of which are incorporated
herein by reference.
BACKGROUND
[0002] Leadframes have been used to support terminals for
connection to integrated circuit dies as a package is formed.
[0003] In some embodiments of the present invention a leadframe
provides a die pad and surrounding bondpads. A die is mounted on
the die pad and connections are made between the die and some of
the bondpads. The support members for the bondpads and the
remainder of the leadframe are positioned to lie below a reference
plane defined relative to the lower surface of the die and the
lower surface of the bondpads. The leadframe, die and bondpads are
encapsulated in insulating material and the package is processed to
remove all of the interstitial and leadframe material that lie
below the reference plane. The lower surface of the resulting
package has an array of bondpads adjacent the die pad.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 is a sectional elevation view of an integrated
circuit package formed according to an embodiment of the
invention;
[0005] FIG. 2 is a view of an embodiment of a leadframe in
accordance with the invention and which is constructed and arranged
for assembly into a circuit package in accordance with an
embodiment of the invention;
[0006] FIG. 3 is a detailed side elevation cross-section view
showing an etching operation which may be a part of the process for
preparing the leadframe for assembly of a package in accordance
with an embodiment of the invention;
[0007] FIG. 4 is a detailed side elevation cross-section views
showing a mechanical forming operation which may be a part of the
process for preparing the leadframe for assembly of a package in
accordance with an embodiment of the invention;
[0008] FIG. 5 is a side elevation cross-section view showing a an
embodiment of a subassembly of a leadframe and die for use in
forming an integrated circuit package in accordance with an
embodiment of the invention;
[0009] FIG. 6 is a side elevation cross sectional view of an
oversized molded integrated circuit package prior to singulation
and backgrinding;
[0010] FIG. 7 is a cross-section elevation view of the oversized
package of FIG. 6 after removal of interstitial material and the
distal support members; and
[0011] FIG. 8 is a flow chart of integrated circuit package forming
operations in accordance with an embodiment of the present
invention.
DESCRIPTION OF EMBODIMENTS
[0012] In the following detailed description, reference is made to
the accompanying drawings which form a part hereof, and in which is
shown by way of illustration specific embodiments in which the
invention may be practiced. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention, and it is to be understood that other embodiments
may be utilized and that structural changes may be made without
departing from the spirit and scope of the present invention.
[0013] For convenience, reference has been made in the
specification and claims to various surfaces as "upper" or "lower".
It is not intended that such descriptions be absolute, since
repositioning of a described object to an orientation other than
that shown in the attached drawings may change their
classification, but not their orientation relative to each other.
Thus such terms are used in a relative rather than an absolute
sense.
[0014] The following detailed description is not to be taken in a
limiting sense, and the scope of the present invention is defined
by the appended claims.
[0015] In FIG. 1, an integrated circuit package 10 carrying a
semiconductor die 12 illustrates a package manufactured in
accordance with an embodiment of the invention. Die 12 has its
inactive, or lower, face attached to a die pad 14 by conventional
die attachment or lead-on-chip (LOC) process technology for
attaching a die to a die pad using adhesive or double backed tape,
as known in the art. The active, or upper, surface of die 12 has on
it a number of terminals or vias which connect to various points in
electronic circuits within die 12.
[0016] A plurality of bond pads 16 are each connected by jumper
wires or conductors 18 to the terminals or vias exposed on the
upper surface of die 12. One end of a jumper wire or conductor 18
is wirebonded or otherwise conductively attached to a terminal or
via on the upper surface of die 12. The other end of conductor 18
is connected to a corresponding bond pad 16. The die 12, die pad
14, jumper wires 18 and bond pads 16 together form a subassembly
which may then be encapsulated in a suitable thermoplastic or
thermoset material 22 to form an oversized electronic circuit
package. After the lower surface of bond pads 16 is exposed as
described below, solder balls 20 are applied to the lower surface
of each bond pad. The solder balls 20 facilitate the connection of
bond pads 16 of package 10 to circuit conductors on a motherboard
or other printed circuit board providing electrical connections
between die 12 and other circuits to form an electronic system.
[0017] FIG. 2 is a top view of a leadframe structure used in an
embodiment of the invention for arranging bondpads 16 surrounding
die pad 14. In one embodiment of the invention the leadframe 24 may
be etched or stamped from a single sheet of a suitable conductive
material such as copper or a copper alloy. In another embodiment of
the invention a further layer of material may be added to at least
the die pad region 14 to facilitate its functioning as a heat
spreader to conduct heat away from individual concentrations of
heat on the lower surface of die 12.
[0018] Etching the sheet material to manufacture the leadframe 24
may permit the creation of more complex arrangements of bond pads
16 in the open portion 23 of the leadframe 24 adjacent die pad 14.
Multiple leadframes 24 may be produced on a large sheet in the
stamping or etching process and later singulated into separate
leadframes 24 for use in individual packages 10 at various stages
of the manufacturing process. Though the drawings in the present
application illustrate the manufacture of a single integrated
circuit package 10 from a single leadframe 24, it will be
appreciated by one skilled in the art that the various embodiments
of the manufacturing process described herein may also be practiced
on multiple packages with the singulation into individual packages
occurring at several suitable places in the process after the
encapsulating step described below.
[0019] Frame portion 26 has a plurality of support fingers 28
extending inwardly from it and supporting bond pads 16 with their
proximal portion. Both frame portion 26 and support fingers 28
comprise support members for bond pads 16 prior to their
encapsulation in interstitial material 22. As shown in FIG. 2,
according to one embodiment of the invention, bond pads 16 are
arranged in multiple staggered courses or rows such as the two
staggered separate courses or rows 29a or 29b surrounding die pad
14 to provide an array of staggered bond pads. It will be
appreciated by those skilled in the art that a number of other
staggered and aligned bond pad configuration geometries are
possible and indeed, are facilitated by the flexibility of
application of embodiments of the present invention.
[0020] Each of the support fingers 28 between the frame portion 26
and bond pad 16 has a width which may be substantially narrower
than the width or length dimensions of generally rectilinearly
shaped bond pads 16 or a diameter or chord of either oval,
octagonal or curvilinearly shaped bond pads. When two or more
staggered multiple courses 29 of bond pads 16 are arrayed adjacent
a die pad 14, the width dimension of the supporting fingers 28,
viewed in the plane of the leadframe 24, are substantially less
that the surface dimensions of bond pad 16.
[0021] In preparing the leadframe 24 for carrying out the package
forming methods according to an embodiment of the invention,
adhesive strips 30 are applied to secure fingers 28 to a supporting
substrate 32 during the assembly process. The use of adhesive
strips 30 is optional and can be directly beneath bond pad 16 or
nearby to provide support during the assembly process. Securing
fingers 28 to substrate 32 using tape strips 30 strengthens them
during the wire bonding operation used for connecting jumper wires
18 between terminals on die 12 and bond pads 16.
[0022] In FIG. 3 there is shown a detail elevation view of a bond
pad 16 which is supported at the end of a finger 28 extending
inwardly from leadframe frame portion 26. In one embodiment an
etching process is carried out to selectively reduce the thickness
of a portion of the leadframe finger or support member 28. In FIG.
3, the portion of the finger or support member 28 distal of the
bond pad 16 is etched away to lower the top surface 33 of finger 28
so that the entirety of that portion of the length of finger 28 is
lowered below a reference plane 37 which passes through bond pad 16
at a distance below the upper surface of bond pad 16 which is
suitable for the finished height h of bond pad 16.
[0023] Once the subassembly is completed and encapsulated as
discussed below, the portions of leadframe 24 which are located
below reference plane 37 are removed by grinding, or some other
material removing operation, to leave the upper portion of bond
pads 16 exposed on the lower surface of package 10. Because the
grinding removes of the material below the reference plane 37, the
portions of fingers 28 distal of the bond pads is removed, leaving
the remaining portion of the bond pad supported by the interstitial
material 22 with the lower face of the bond pad 16 exposed for
receiving solder balls 20 or solder for connection the terminals of
the package 1--to conductors on a some printed circuit board to
allow the package to become part of an electronic system.
[0024] In FIG. 4 there is shown a detail elevation view of a bond
pad 16 which is at the end of a support finger 28 extending
inwardly from the perimeter portion 26 of the leadframe. The
fingers 28 are mechanically formed so as to separate the reference
plane 37 defined by the lower surface 38 of bond pads 16 away from
the surface of substrate 32 before fingers 28 are secured to
substrate 32 with tape 30.
[0025] FIG. 5 shows an elevation view of the package with die 12
attached to die pad 14 and elevated above the taped portions of
fingers 28 which are secured to substrate 32. In FIG. 5, bond pad
16a is shown extending from and therefore, electrically connected
to die pad 14 to provide a connection to exterior circuits for the
ground plane provided by die pad 14. Other bond pads 16 are
generally not connected to die pad 14 by fingers 28 of leadframe
24.
[0026] FIG. 6 also shows the jumper wires or conductors 18 which
have their ends wirebonded respectively to bond pads 16 and to
terminals on the active surface of die 12. In one embodiment, the
wirebonding process is preferably carried out while portions of the
length of fingers 28 remain taped to substrate 32 to increase the
resistance to bending and damage of the thin leadframe during the
wirebonding process.
[0027] FIG. 6 illustrates package 10 following molding of the
subassembly into an oversized molded structure by encapsulating the
subassembly in a suitable interstitial material 22 which may be a
thermosetting plastic or other readily moldable material as is
commonly used in the art. The oversized molded structure contains
the taped portions of fingers 28. Once the intyerstitial material
22 has cured ior otherwise solidified, the package may then be
singulated to reduce it to an oversized single die package that is
then ground and further singulated to the final sized package 10
shown in cross section in FIG. 7. The grinding may be performed by
backgrinding or surface grinding machines as are presently used for
the surface grinding of semiconductor wafers.
[0028] In the package of FIG. 7, the lower surfaces 72 of bond pads
16 are exposed as a part of the backgrinding process and the
portions of fingers 28 distal of the bond pads 16 were removed
along with tape 30 and the remainder of the surrounding support
frame portion 26 of leadframe 24. Addition of solder balls 20 to
the freshly exposed, recently ground, lower faces of bond pads 16
completes the manufacture of the package 10 to the configuration
shown in FIG. 1.
[0029] FIG. 9 is a flow chart of the manufacturing operations that
may be followed in manufacturing a die package according to an
embodiment of the present invention. In the portion of the process
of block 91 the leadframe is formed with a lower surface thereof
defining a reference plane. The leadframe support members are
positioned below the reference plane in a further operation 92. In
a further operation 93 the die is mounted on the die pad with the
body of the die positioned above the die pad. In a further
operation 94 some of the bond pads are connected to terminals on
the die. The die and leadframe are then encapsulated with
interstitial material in operation 95. In the final block 96 the
distal support members and interstitial material lying below the
reference plane are removed by grinding, etching or some other
material removal process.
[0030] It is to be understood that the above description is
intended to be illustrative, and not restrictive. Many other
embodiments will be apparent to those of skill in the art after
reviewing the above description. The scope of the invention should,
therefore, be determined with reference to the appended claims,
along with the full scope of equivalents to which such claims are
entitled.
* * * * *