U.S. patent application number 11/595970 was filed with the patent office on 2007-03-15 for fan out type wafer level package structure and method of the same.
This patent application is currently assigned to ADVANCED CHIP ENGINEERING TECHNOLOGY INC.. Invention is credited to Shih-Li Chen, Wen-Kun Yang, Wen-Pin Yang.
Application Number | 20070059866 11/595970 |
Document ID | / |
Family ID | 34633314 |
Filed Date | 2007-03-15 |
United States Patent
Application |
20070059866 |
Kind Code |
A1 |
Yang; Wen-Kun ; et
al. |
March 15, 2007 |
Fan out type wafer level package structure and method of the
same
Abstract
To pick and place standard dies on a new base for obtaining an
appropriate and wider distance between dies than the original
distance of dies on a wafer. The package structure has a larger
size of balls array than the size of the die by fan out type
package. Moreover, the die may be packaged with passive components
or other dies with a side by side structure or a stacking
structure.
Inventors: |
Yang; Wen-Kun; (Hsinchu,
TW) ; Yang; Wen-Pin; (Hsinchu, TW) ; Chen;
Shih-Li; (Jhudong Township, TW) |
Correspondence
Address: |
Gary M. Nath;NATH & ASSOCIATES PLLC
112 South West Street
Alexandria
VA
22314
US
|
Assignee: |
ADVANCED CHIP ENGINEERING
TECHNOLOGY INC.
Hsinchu
TW
|
Family ID: |
34633314 |
Appl. No.: |
11/595970 |
Filed: |
November 13, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11169722 |
Jun 30, 2005 |
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11595970 |
Nov 13, 2006 |
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10725933 |
Dec 3, 2003 |
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11169722 |
Jun 30, 2005 |
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Current U.S.
Class: |
438/125 ;
257/E25.012 |
Current CPC
Class: |
H01L 2924/09701
20130101; H01L 2224/12105 20130101; H01L 2224/97 20130101; H01L
2924/01033 20130101; H01L 2924/01027 20130101; H01L 2924/01082
20130101; H01L 2924/01074 20130101; H01L 2924/01079 20130101; H01L
2924/15788 20130101; H01L 2924/15788 20130101; H01L 25/0657
20130101; H01L 2924/01076 20130101; H01L 24/19 20130101; H01L
2224/20 20130101; H01L 2924/01078 20130101; H01L 2225/06551
20130101; H01L 2924/14 20130101; H01L 2924/01013 20130101; H01L
23/3128 20130101; H01L 2224/0401 20130101; H01L 2224/73267
20130101; H01L 2924/01019 20130101; H01L 2924/01068 20130101; H01L
2224/211 20130101; H01L 2924/01075 20130101; H01L 2924/01077
20130101; H01L 2224/04105 20130101; H01L 2225/06524 20130101; H01L
2225/06541 20130101; H01L 2924/15311 20130101; H01L 2924/01015
20130101; H01L 2224/97 20130101; H01L 25/0655 20130101; H01L
2224/24195 20130101; H01L 24/20 20130101; H01L 2924/01006 20130101;
H01L 2924/00 20130101; H01L 2924/15311 20130101; H01L 2224/82
20130101; H01L 2924/01029 20130101; H01L 2924/01005 20130101; H01L
2224/24137 20130101; H01L 21/561 20130101; H01L 2224/92244
20130101; H01L 2924/15173 20130101; H01L 23/5389 20130101; H01L
2224/32225 20130101; H01L 24/97 20130101; H01L 2224/97 20130101;
H01L 2924/19041 20130101 |
Class at
Publication: |
438/125 |
International
Class: |
H01L 21/00 20060101
H01L021/00 |
Claims
1. A process of fan out type wafer level package, comprising the
steps of: adhering a first plurality of dies to an isolating base;
forming a first material layer on said isolating base to fill in a
space among said first plurality of dies on said isolating base;
curing said first material layer; forming a second material layer
on said first material layer and said first plurality of dies;
etching a partial region of said second material layer on first
pads of said first plurality of dies to form first openings; curing
said second material layer; forming first contact conductive layer
on said first openings to electrically couple with said first pads,
respectively; forming a first photo resist layer on said second
material layer and said first contact conductive layer; removing a
partial region of said first photo resist layer to form a first fan
out pattern and expose said first contact conductive layer; forming
first conductive lines on said first fan out pattern and said first
conductive lines being coupled with said first contact conductive
layer, respectively; removing remaining said first photo resist
layer; forming a first isolation layer on said first conductive
lines and said second material layer; removing a partial region of
said first isolation layer on said first conductive lines to
forming second openings; curing said first isolation layer; and
welding solder balls on said second openings.
2. The process in claim 1, wherein surfaces of said first material
layer and said first plurality of dies are at same level.
3. The process in claim 1, further comprising a step of sawing said
base to isolate said first plurality of dies after the step of said
welding solder balls.
4. The process in claim 1, further comprising a step of adhering a
plurality of first passive components to said isolating base among
said first plurality of dies onto an isolating base before the step
of forming said first material layer.
5. The process in claim 1, wherein said first plurality of dies
comprises at least two types of dies.
6. The process in claim 1, wherein said first plurality of dies is
formed by sawing a processed silicon wafer.
7. The process in claim 4, wherein said processed silicon wafer is
back lapped to get a thickness of said processed silicon wafer
around 50-300 .mu.m.
8. The process in claim 1, wherein materials of said first material
layer and said second material layer comprise UV curing type
material, heat curing type material, and the combination
thereof.
9. The process in claim 1, further comprising a step of cleaning
each surface of said first pads by using plasma etching after the
step of etching a partial region of said second material layer.
10. The process in claim 1, further comprising a step of forming an
epoxy layer on back surface of the base.
11. The process in claim 1, wherein said first contact conductive
layer comprises Ti, Cu, and the combination thereof.
12. The process in claim 1, wherein said first conductive lines
comprise Ni, Cu, Au, and the combination thereof.
13. The process in claim 1, wherein said isolation layer comprises
epoxy, resin, and the combination thereof.
14. The process in claim 1, wherein a material of said isolating
base is glass, silicon, ceramic, or crystal material.
15. The process in claim 1, wherein said isolating base is a round
type or a rectangular type.
16. The process in claim 1, wherein said first contact conductive
layer and said first conductive lines are formed by a forming
method comprising physical method, chemical method, and the
combination thereof.
17. The process in claim 16, wherein said forming method comprising
CVD, PVD, sputter, and electroplating.
18. The process in claim l, wherein the step of welding said solder
balls comprises placing said solder balls on said second openings
by a screen printing method and joining said solder balls together
with surfaces of said first conductive lines by a IR reflow
method.
19. The process in claim 1 further comprising further steps before
the step of removing a partial region of said first isolation
layer, said further steps being: adhering a second plurality of
dies to said first isolation layer in the vertical direction of
said first plurality of dies; forming a third material layer on
said first isolation layer to fill in a space among said second
plurality of dies on said first isolation layer; curing said third
material layer; forming a fourth material layer on said third
material layer and said second plurality of dies; etching a partial
region of said fourth material layer on second pads of said second
plurality of dies to form third openings; curing said fourth
material layer; forming second contact conductive layer on said
third openings to electrically coupling with said second pads,
respectively; removing a partial region of said fourth material
layer, said third material layer, and said second material layer on
said first conductive lines to forming second openings; filling up
said openings with conductive material and surfaces of said
conductive material and said fourth material layer are at same
level; forming a second photo resist layer on said fourth material
layer, said conductive material, and said second contact conductive
layer; removing a partial region of said second photo resist layer
to form a second fan out pattern and expose said second contact
conductive layer and said conductive material; forming second
conductive lines on said second fan out pattern and said second
conductive lines being coupled with corresponding said second
contact conductive layer and corresponding said conductive
material; removing remaining said second photo resist layer;
forming a second isolation layer on said second conductive lines
and said fourth material layer; removing a partial region of said
second isolation layer on said second conductive lines to forming
third openings; curing said second isolation layer; and welding
solder balls on said third openings.
20. The process in claim 19, wherein surfaces of said third
material layer and said second plurality of dies are at same
level
21. The process in claim 19, further comprising a step of sawing
said base to isolate packaged dies having one of said first
plurality of dies and one of said second plurality of dies.
22. The process in claim 19, further comprising a step of adhering
a second plurality of first passive components to said isolating
base among said second plurality of dies onto said first isolation
layer before the step of forming said third material layer.
23. The process in claim 19, wherein said second plurality of dies
comprises at least two types of dies.
24. The process in claim 19, wherein materials of said third
material layer and said fourth material layer comprises UV curing
type material, heat curing type material, and the combination
thereof.
25. The process in claim 19, further comprising a step of cleaning
each surface of said second pads by using plasma etching after the
step of etching a partial region of said fourth material layer.
26. The process in claim 19, wherein said second contact conductive
layer comprises Ti, Cu, and the combination thereof.
27. The process in claim 19, wherein said second conductive lines
comprises Ni, Cu, Au, and the combination thereof.
28. The process in claim 19, wherein said second contact conductive
layer and said second conductive lines are formed by a forming
method comprising physical method, chemical method, and the
combination thereof.
29. The process in claim 19, wherein the step of welding said
solder balls comprises placing said solder balls on said third
openings by a screen printing method and joining said solder balls
together with surfaces of said second conductive lines by a IR
reflow method.
Description
[0001] This is a divisional of U.S. patent application Ser. No.
11/169,722, filed Jun. 30, 2005, currently pending, which is a
divisional of U.S. patent application Ser. No. 10/725,933, filed
Dec. 3, 2003, currently pending.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] This invention relates to a package for semiconductors, and
more particularly to a fan out type wafer level package.
[0004] 2. Description of the Prior Art
[0005] The semiconductor technologies are developing very fast, and
especially semiconductor dies have a tendency toward
miniaturization. However, the requirements for the functions of the
semiconductor dies have an opposite tendency to variety. Namely,
the semiconductor dies must have more I/O pads into a smaller area,
so the density of the pins is raised quickly. It causes the
packaging for the semiconductor dies to become more difficult and
decrease the yield.
[0006] The main purpose of the package structure is to protect the
dies from outside damages. Furthermore, the heat generated by the
dies must be diffused efficiently through the package structure to
ensure the operation the dies.
[0007] The earlier lead frame package technology is already not
suitable thereof is too high. Hence, a new package technology of
BGA (Ball Grid Array) has been developed to satisfy the packaging
requirement for the advanced semiconductor dies. The BGA package
has an advantage of that the spherical pins has a shorter pitch
than that of the lead frame package and the pins is hard to damage
and deform. In addition, the shorter signal transmitting distance
benefits to raise the operating frequency to conform to the
requirement of faster efficiency. For example, the U.S. Pat. No.
5,629,835 discloses a BGA package, by Mahulikar et al; the U.S.
Pat. No. 5,239,198 discloses another package that the FR4
substrates having a pattern of conductive traces thereon are
mounted on a PCB; the Taiwan patent No. 177,766 discloses a fan out
type WLP, by the inventor of the present invention.
[0008] Most of the package technologies divide dies on a wafer into
respective dies and then to package and test the die respectively.
Another package technology, called "Wafer Level Package (WLP)", can
package the dies on a wafer before dividing the dies into
respective dies. The WLP technology has some advantages, such as a
shorter producing cycle time, lower cost, and no need to under-fill
or molding. The U.S. Pat. No. 5,323,051, "Semiconductor wafer level
package", is disclosed a WLP technology by Adams et al. The
technology is described as follow. As shown in FIG. 1, a die 4 is
formed on a surface of a semiconductor wafer 2, and a cap wafer 6
with a predetermined pattern of frit glass walls 8 as a bonding
agent is deposited on a surface of the semiconductor wafer 2, such
that the die 4 is completely surrounded by the frit glass walls 8.
Then, a surface of the semiconductor wafer 2 without the die 4 is
polished to reduce the height of the semiconductor wafer 2; the
process is generally called "Back Grinding". The die 4 is
hermetically sealed in a cavity of predetermined dimensions formed
by a combination of the semiconductor wafer 2, the cap wafer 6, and
the frit glass walls 8. A plurality of metal traces 10 forms a
plurality of electrodes on semiconductor substrate wafer 2 which
provide electrical coupling to die 4. A plurality of wires 12 is
bonded to a plurality of pads formed on exterior portions of metal
traces 10, and extends through hole 14 and is coupled to external
electrical dies (not shown).
[0009] As aforementioned, the size of the die is very small, and
the I/O pads are formed on a surface of a die in the conventional
arts. Therefore, number of the pads is limited and a too short
pitch among pads results in a problem of signal coupling or signal
interface. The solder is also to form a solder bridge easily due to
the too short pitch among pads. Moreover, the size of die gradually
become smaller and the packaged IC of the die does not have
standard size by some package technologies (such as chip size
package), but test equipment, package equipment, etc. for some
fixed sizes die or packages can not be kept on using
SUMMARY OF THE INVENTION
[0010] Therefore, the present invention has been made in view of
the above problems in the prior arts, and it is an objective of the
present invention to provide a fan out type wafer level package
structure and a method for manufacturing the same.
[0011] Another objective of the present invention is to provide a
fan out type wafer level package structure to maintain an
appropriate pitch between two adjacent pads of the package
structure.
[0012] Still another objective of the present invention is to avoid
problems of signal coupling and signal interface.
[0013] Another objective of the present invention is to lower the
cost of the package structure.
[0014] Still another objective of the present invention is to raise
the yield of the package structure.
[0015] Another objective of the present invention is to provide
package structure with a adjustable size to keep on using of test
equipment, package equipment, etc. having for some fixed sizes die
or packages.
[0016] As aforementioned, the present invention provides a process
of fan out type wafer level package. First, a plurality of dies is
adhered to an isolating base. A first material layer is formed on
the isolating base, wherein a space among the plurality of dies on
the isolating base is filled up with the first material layer, and
surfaces of the first material layer and the plurality of dies are
at same level. Then, the first material layer is cured. A second
material layer is formed on the first material layer and the
plurality of dies. A partial region of the second material layer on
pads of the plurality of dies is etched to form first openings.
Next, the second material layer is cured. Contact conductive layer
are formed on the first openings to electrically coupling with the
pads, respectively. A photo resist layer is formed on the second
material layer and the contact conductive layer. A partial region
of the photo resist layer is removed to form a fan out pattern and
expose the contact conductive layer. After that, conductive lines
are formed on the fan out pattern and the conductive lines are
coupled with the contact conductive layer, respectively. The
remaining photo resist layer is removed. Following that, an
isolation layer is formed on the conductive lines and the second
material layer. A partial region of the isolation layer on the
conductive lines is removed to forming second openings. The
isolation layer is cured. Finally, solder balls are welded on the
second openings and the base is sawed to isolate the plurality of
dies.
[0017] The present invention also provides a fan out type package
structure. The package structure comprises an isolating base, a
die, a first dielectric layer, a second dielectric layer, a contact
conductive layer, conductive lines, an isolation layer, and solder
balls. The die is adhered to the isolating base. The first
dielectric layer is formed on the isolating base and filled in a
space except the die on the isolating base, wherein surfaces of the
first dielectric layer and the die are at same level. The second
dielectric layer is formed on the first dielectric layer and the
die, and the second dielectric layer has first openings on pads of
the die. The contact conductive layer is formed on the first
openings to electrically coupling with the pads, respectively. The
conductive lines are formed on the second dielectric layer and
corresponding the contact conductive layer, and the conductive
lines are extended out from corresponding the contact conductive
layer to corresponding end points, wherein the corresponding end
points are inside a surface of the second dielectric layer. The
isolation layer is formed on the conductive lines and the second
dielectric layer, and the isolation layer has second openings on
the conductive lines. The solder balls are welded on the second
openings and electrical coupling with the conductive lines,
respectively.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a schematic diagram of a semiconductor wafer level
package in the conventional arts;
[0019] FIG. 2A to FIG. 2C are schematic diagrams of using pick
& place to replace standard dies onto a new base;
[0020] FIG. 3 is a schematic diagram of forming a first material
layer on the base;
[0021] FIG. 4 is a schematic diagram of forming a second material
layer on the first material layer and the die;
[0022] FIG. 5 is a schematic diagram of etching a partial region of
the second material layer on pads of the die to form first
openings;
[0023] FIG. 6 is a schematic diagram of forming contact conductive
layer on the first openings;
[0024] FIG. 7 is a schematic vertical view diagram of forming
conductive lines on fan out pattern formed by a photo resist
layer;
[0025] FIG. 8 is a schematic lateral view diagram of forming
conductive lines on fan out pattern formed by a photo resist layer
along a-a' in FIG. 7;
[0026] FIG. 9 is a schematic diagram of forming an isolation layer
on the conductive lines and the second material layer;
[0027] FIG. 10 is a schematic diagram of one packaged structure
according to the present invention;
[0028] FIG. 11 is a schematic diagram of one packaged structure
having a die and a passive component according to the present
invention;
[0029] FIG. 12 is a schematic diagram of one packaged structure
having two dies according to the present invention; and
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0030] Some sample embodiments of the invention will now be
described in greater detail. Nevertheless, it should be recognized
that the present invention can be practiced in a wide range of
other embodiments besides those explicitly described, and the scope
of the present invention is expressly not limited expect as
specified in the accompanying claims.
[0031] Then, the components of the different elements are not shown
to scale. Some dimensions of the related components are exaggerated
and meaningless portions are not drawn to provide a more clear
description and comprehension of the present invention.
[0032] The essence of the present invention is to pick and place
standard dies on a new base for obtaining an appropriate and wider
distance between dies than the original distance of dies on a
wafer. Therefore, the package structure has a larger size of balls
array than the size of the die to avoid the problem of having too
close ball pitch. Moreover, the die may be packaged with passive
components (ex. capacitors) or other dies with a side by side
structure or a stacking structure. The detailed process of the
present invention will be described below.
[0033] A processed silicon wafer with dies is put on a tray and
then the thickness of the processed silicon wafer is decreased by
back lapping to get a thickness range of 50-300 .mu.m . The
processed silicon wafer with the aforementioned thickness is easily
sawed to divide the dies on the wafer into respective dies. The
back lapping step may be omitted if the processed silicon wafer is
not hard to saw without back lapping. A dielectric layer
(protection layer) is optionally formed on the processed silicon
wafer before sawing to protect dies form damages.
[0034] The divided dies are tested to choose standard good dies 110
there from. The standard good dies 110 are picked and replaced onto
a new base 100 with a wider distance between two adjacent dies and
adhered to the base 100 with an UV curing type and/or heat curing
type adhesion material with good thermal conductivity (not shown),
as shown in FIG. 2A. The adhesion material is coating on the base
100, and the thickness of the adhesion material is preferably 20-60
.mu.m. When the dies 110 are placed on the adhesion material, the
adhesion material is cured by UV light or thermal. The distance
between two adjacent dies on the base 100 is arranged wider to have
enough space for forming fan out ball array in later steps. Hence,
the present invention can maintain an ideal ball pitch for avoiding
problems of signal coupling and signal interface and increase the
number of I/O ports (balls), even the size of dies becomes smaller.
The dies 110 have I/O pads 116 on the upper surface (as shown in
FIG. 4). Passive components 114 or dies 112 are also placed on an
adjacent place of the base 100 to obtain a filtering or other
functions, as shown in FIG. 2B and FIG. 2C. The material of the
base 100 can be glass, silicon, ceramic, crystal materials, etc.
and even have a round or a rectangular shape. In the present
invention, the number of dies and passive components packaged
together are not limited. More than three dies and passive
components also can be packaged in the same package structure by
the present invention. The adhesive material of the present
invention is preferably good thermal conductive material, so the
problems (such as stress) resulted from the temperature difference
between the dies 110 and the base 100 can be avoided.
[0035] The illustration and the corresponding figure below are made
through single die to simplify and provide a more clear description
comprehension of the present invention.
[0036] First material layer 120 is formed to fill in the space
among the die 110 and adjacent dies 110, and the surface of the
first material layer 120 and the surface of the die 110 are at same
level. The material of the first material layer 120 can be UV
curing type or heating curing type material. Then, the first
material layer 120 is cured by UV or thermal. The first material
layer 120 may be formed by a screen printing method or a
photolithography method. The first material layer 120 functions as
a buffer layer to reduce a stress due to temperature, etc. The
first material layer 120 can be a UV and/or heat curing material,
such as silicon rubber, epoxy, resin, BCB, and so on. The
aforementioned structure 102, comprising the base 100, the dies
110, and the first material layer 120, looks same as a wafer with
the dies 110 facing above.
[0037] As shown in FIG. 4, a second material layer 122 is coated on
the structure 102. The material of the second material layer 120
can be UV curing type or heating curing type material, such as BCB,
epoxy, SINR3170 (produced by Shin-Etsu Chemical Co.,Ltd.), and so
on. Then, the partial area of the second material layer 122 on the
pads 116 of the die 110 is removed by using a photo mask to form
first openings 124 on the pads 116, and then the second material
layer 120 is cured by UV or heating. Next, the plasma etching (RIE)
can be used optionally to clean the surface of the pads 116 to make
sure no residual materials on the pads 116.
[0038] The contact conductive layer 126 is formed on the pads 116,
as shown in FIG. 6. The preferable material of the contact
conductive layer 126 is Ti, Cu, or the combination thereof. The
contact conductive layer 126 can be formed by a physical method, a
chemical method, or the combination thereof, for example: CVD, PVD,
sputter, and electroplating. A photo resist layer 128 is formed on
the second material layer 122 and the contact conductive layer 126,
and then a fan out pattern of the photo resist layer 128 is
developed by using a photo mask. The fan out pattern has a
plurality of fan out openings starting form the pads 116 to end
points inside a surface of the second dielectric layer 122,
respectively. Namely, the end points of two adjacent fan out
openings can have wider pitches there between than the pitch
between two adjacent pads 116. Then, conductive lines 130 by
electro plating are formed on the contact conductive layer 126, as
shown in FIG. 7 (vertical view) and FIG. 8 (lateral view, along
a-a' in FIG. 7). The material of the conductive lines 130 are
preferably Cu, Ni, Au, or the combination thereof.
[0039] Referring to FIG. 9, the photo resist layer 128 and the
contact conductive layer 126 are etched, and then an isolation
layer 132 is formed on the conductive lines 130 and the second
material layer 122, and the second openings 134 are formed on the
conductive lines 130 by using a photo mask. Next, the first
isolation layer 132 is cured. The first isolation layer 132 may be
formed by spin coating or screen printing. The positions of the
second openings 134 may be formed above the die 110 or the first
material layer 120, preferably formed close to the ending points of
the conductive lines 130 respectively, so a suitable distance
between two adjacent second openings 134 is to form solder balls
136 on second openings 134 without the problem of signal coupling
and signal interface.
[0040] Referring to FIG. 10, an epoxy layer 140 is formed on the
back side of the base 100, i.e. on the surface of the base 100
having no die 110formed thereon. Then, a top mark is formed on the
epoxy layer 140 by using a photo mask and the epoxy layer 140 is
cured. Or using the ink printing with stencil then heat/UV curing
to form a top mark. The top mark is for identified the device name.
The step of forming the epoxy layer 140 may be omitted. Next, the
solder balls 136 are placed onto the solder openings 134 and joined
the solder balls 136 and the surface of the conductive lines 130
with IR re-flow.
[0041] Final, the packaged base 100 with the aforementioned
structure is sawed along the sawing line 138 to isolate respective
packaged IC. As aforementioned, the packaged IC may be included
passive component 142 and the die 110, as shown in FIG. 11. The
packaged IC also may be a multi dies with side by side structure,
as shown in FIG. 12.
[0042] Hence, according to the present invention, the
aforementioned package structure can maintain an appropriate pitch
between two adjacent solder balls of the package structure.
Therefore, the present invention can avoid the problems of signal
coupling and signal interface. Moreover, the present invention also
employs a glass substrate for LCD and the size of the glass
substrate is very larger, so the present invention can lower the
cost of the package structure and raise the yield of the package
structure. Moreover, the package size of the present invention can
be easily adjusted to test equipment, package equipment, etc.
[0043] Although specific embodiments have been illustrated and
described, it will be obvious to those skilled in the art that
various modifications may be made without departing from what is
intended to be limited solely by the appended claims.
* * * * *