U.S. patent application number 11/482124 was filed with the patent office on 2007-01-18 for group iii nitride semiconductor substrate and manufacturing method thereof.
Invention is credited to Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa.
Application Number | 20070012943 11/482124 |
Document ID | / |
Family ID | 36799722 |
Filed Date | 2007-01-18 |
United States Patent
Application |
20070012943 |
Kind Code |
A1 |
Okahisa; Takuji ; et
al. |
January 18, 2007 |
Group III nitride semiconductor substrate and manufacturing method
thereof
Abstract
A method of manufacturing a group III nitride semiconductor
substrate includes the growth step of epitaxially growing a first
group III nitride semiconductor layer on an underlying substrate,
and the process step of forming a first group III nitride
semiconductor substrate by cutting and/or surface-polishing the
first group III nitride semiconductor layer. In the growth step, at
least one element selected from the group consisting of C, Mg, Fe,
Be, Zn, V, and Sb is added as an impurity element by at least
1.times.10.sup.17 cm.sup.-3 to the first group III nitride
semiconductor layer. A group III nitride semiconductor substrate
having controlled resistivity and low dislocation density and a
manufacturing method thereof can thus be provided.
Inventors: |
Okahisa; Takuji; (Itami-shi,
JP) ; Nakahata; Hideaki; (Itami-shi, JP) ;
Nakahata; Seiji; (Itami-shi, JP) |
Correspondence
Address: |
MCDERMOTT WILL & EMERY LLP
600 13TH STREET, N.W.
WASHINGTON
DC
20005-3096
US
|
Family ID: |
36799722 |
Appl. No.: |
11/482124 |
Filed: |
July 7, 2006 |
Current U.S.
Class: |
257/102 ;
257/E21.11; 257/E21.131; 257/E33.029; 438/22 |
Current CPC
Class: |
H01L 21/0237 20130101;
H01L 21/0262 20130101; H01L 21/02433 20130101; H01L 21/02647
20130101; C30B 25/02 20130101; H01L 21/02581 20130101; H01L
21/02573 20130101; C30B 29/406 20130101; H01L 21/0254 20130101 |
Class at
Publication: |
257/102 ;
438/022; 257/E33.029 |
International
Class: |
H01L 33/00 20060101
H01L033/00; H01L 21/00 20060101 H01L021/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 11, 2005 |
JP |
2005-004142 (P) |
Claims
1. A group III nitride semiconductor substrate containing at least
one element selected from the group consisting of C, Mg, Fe, Be,
Zn, V, and Sb as an impurity element in concentration of at least
1.times.10.sup.17 cm.sup.-3; wherein in-plane distribution of the
concentration of said impurity element represented as a ratio of a
maximum concentration to a minimum concentration of said impurity
element in a main surface of the substrate is in a range from at
least 1 to at most 3, and said group III nitride semiconductor
substrate has resistivity of at least 1.times.10.sup.4 .OMEGA.cm
and thickness of at least 70 .mu.m.
2. The group III nitride semiconductor substrate according to claim
1, wherein average dislocation density is at most 1.times.10.sup.7
cm.sup.-2, and surface density of a dislocation-concentrated region
where dislocation density exceeds 1.times.10.sup.8 cm.sup.-2 is at
most 1 cm.sup.2.
3. The group III nitride semiconductor substrate according to claim
1, wherein said group III nitride is GaN.
4. The group III nitride semiconductor substrate according to claim
1, wherein said main surface of said group III nitride
semiconductor substrate is at an angle in a range from at least
-5.degree. to at most 5.degree. with respect to any one of a (0001)
surface, a (1-100) surface and a (11-20) surface.
5. The group III nitride semiconductor substrate according to claim
1, wherein a half-width of a rocking curve in X-ray diffraction is
in a range from at least 10 arcsec to at most 500 arcsec.
6. The group III nitride semiconductor substrate according to claim
1, wherein carrier density is at most 1.times.10.sup.15
cm.sup.-3.
7. The group III nitride semiconductor substrate according to claim
1, wherein absorption coefficient for light having a wavelength of
450 nm is at least 50 cm.sup.-1.
8. A group IIIi nitride semiconductor substrate containing at least
one element selected from the group consisting of O, Si, S, Ge, Se,
and Te as an impurity element in concentration of at least
1.times.10.sup.17 cm.sup.-3; wherein in-plane distribution of
the.concentration of said impurity element represented as a ratio
of a maximum concentration to a minimum concentration of said
impurity element in a main surface of the substrate is in a range
from at least 1 to at most 3, and said group III nitride
semiconductor substrate has resistivity of at most 1 .OMEGA.cm and
thickness of at least 70 .mu.m.
9. The group III nitride semiconductor substrate according to claim
8, wherein average dislocation density is at most 1.times.10.sup.7
cm.sup.-2, and surface density of a dislocation-concentrated region
where dislocation density exceeds 1.times.10.sup.8 cm.sup.-2 is at
most 1 cm.sup.-2.
10. The group III nitride semiconductor substrate according to
claim 8, wherein said group III nitride is GaN.
11. The group III nitride semiconductor substrate according to
claim 8, wherein said main surface of said group III nitride
semiconductor substrate is at an angle in a range from at least
-5.degree. to at most 5.degree. with respect to any one of a (0001)
surface, a (1-100) surface and a (11-20) surface.
12. The group III nitride semiconductor substrate according to
claim 8, wherein a half-width of a rocking curve in X-ray
diffraction is in a range from at least 10 arcsec to at most 500
arcsec.
13. The group III nitride semiconductor substrate according to
claim 8, wherein carrier density is in a range from at least
1.times.10.sup.17 cm.sup.-3 to at most 1.times.10.sup.20
cm.sup.-3.
14. The group III nitride semiconductor substrate according to
claim 8, wherein absorption coefficient for light of a wavelength
of 450 nm is at most 10 cm.sup.-1.
15. A method of manufacturing a group III nitride semiconductor
substrate, comprising: the growth step of epitaxially growing a
first group III nitride semiconductor layer on an underlying
substrate; and the process step of forming a first group III
nitride semiconductor substrate by cutting and/or surface-polishing
said first group III nitride semiconductor layer; wherein in said
growth step, at least one element selected from the group
consisting of C, Mg, Fe, Be, Zn, V, and Sb is added as an impurity
element by at least 1.times.10.sup.17 cm.sup.-3 to said first group
III nitride semiconductor layer.
16. A method of manufacturing a group III nitride semiconductor
substrate, comprising: the growth step of epitaxially growing a
second group III nitride semiconductor layer on said first group
III nitride semiconductor layer epitaxially grown in the
manufacturing method according to claim 15; and the process step of
forming a second group III nitride semiconductor substrate by
cutting and/or surface-polishing said second group III nitride
semiconductor layer; wherein in said growth step, at least one
element selected from the group consisting of O, Si, S, Ge, Se, and
Te is added as an impurity element by at least 1.times.10.sup.17
cm.sup.-3 to said second group III nitride semiconductor layer.
17. A method of manufacturing a group III nitride semiconductor
substrate, comprising: the growth step of epitaxially growing a
third group III nitride semiconductor layer on said second group
III nitride semiconductor substrate formed in the manufacturing
method according to claim 16; and the process step of forming a
third group III nitride semiconductor substrate by cutting and/or
surface-polishing said third group III nitride semiconductor layer;
wherein in said growth step, at least one element selected from the
group consisting of C, Mg, Fe, Be, Zn, V, and Sb is added as an
impurity element by at least 1.times.10.sup.17 cm.sup.-3 to said
third group III nitride semiconductor layer.
18. A method of manufacturing a group III nitride semiconductor
substrate, comprising: the growth step of epitaxially growing a
fourth group III nitride semiconductor layer on said second group
III nitride semiconductor substrate formed in the manufacturing
method according to claim 16; and the process step of forming a
fourth group III nitride semiconductor substrate by cutting and/or
surface-polishing said fourth group III nitride semiconductor
layer; wherein in said growth step, at least one element selected
from the group consisting of O, Si, S, Ge, Se, and Te is added as
an impurity element by at least 1.times.10.sup.17 cm.sup.-3 to said
fourth group III nitride semiconductor layer.
19. The method of manufacturing a group III nitride semiconductor
substrate according to claim 16, wherein at least one raw material
selected from the group consisting of oxygen, water,
dichlorosilane, tetrachlorosilane, hydrogen sulfide, germanium
chloride, selenium chloride, and tellurium chloride is used as a
raw material for said impurity element.
20. A method of manufacturing a group III nitride semiconductor
substrate, comprising: the growth step of epitaxially growing a
third group III nitride semiconductor layer on said first group III
nitride semiconductor substrate formed in the manufacturing method
according to claim 15; and the process step of forming a third
group III nitride semiconductor substrate by cutting and/or
surface-polishing said third group III nitride semiconductor layer;
wherein in said growth step, at least one element selected from the
group consisting of C, Mg, Fe, Be, Zn, V, and Sb is added as an
impurity element by at least 1.times.10.sup.17 cm.sup.-3 to said
third group III nitride semiconductor layer.
21. The method of manufacturing a group III nitride semiconductor
substrate according to claim 20, wherein at least one raw material
selected from the group consisting of methane, magnesium chloride,
iron chloride, beryllium chloride, zinc chloride, vanadium
chloride, and antimony chloride is used as a raw material for said
impurity element.
22. A method of manufacturing a group III nitride semiconductor
substrate, comprising: the growth step of epitaxially growing a
fourth group III nitride semiconductor layer on said first group
III nitride semiconductor substrate formed in the manufacturing
method according to claim 15; and the process step of forming a
fourth group III nitride semiconductor substrate by cutting and/or
surface-polishing said fourth group III nitride semiconductor
layer; wherein in said growth step, at least one element selected
from the group consisting of O, Si, S, Ge, Se, and Te is added as
an impurity element by at least 1.times.10.sup.17 cm.sup.-3 to said
fourth group III nitride semiconductor layer.
23. The method of manufacturing a group III nitride semiconductor
substrate according to claim 22, wherein at least one raw material
selected from the group consisting of oxygen, water,
dichlorosilane, tetrachlorosilane, hydrogen sulfide, germanium
chloride, selenium chloride, and tellurium chloride is used as a
raw material for said impurity element.
24. The method of manufacturing a group III nitride semiconductor
substrate according to claim 15, wherein any one of a GaAs
substrate, a sapphire substrate, an Si substrate, and an SiC
substrate is employed as said underlying substrate.
25. The method of manufacturing a group III nitride semiconductor
substrate according to claim 24, wherein said growth step is
performed after a mask layer having openings is formed on at least
a part of said underlying substrate.
26. The method of manufacturing a group III nitride semiconductor
substrate according to claim 15, wherein a group III nitride
substrate obtained in a facet growth method is employed as said
underlying substrate.
27. The method of manufacturing a group III nitride semiconductor
substrate according to claim 26, wherein said growth step is
performed after a mask layer having openings is formed on at least
a part of said underlying substrate.
28. The method of manufacturing a group III nitride semiconductor
substrate according to claim 15, wherein a main surface of said
underlying substrate is at an angle in a range from at least
-5.degree. to at most 5.degree. with respect to any one of a (0001)
surface, a (1-100) surface and a (11-20) surface.
29. The method of manufacturing a group III nitride semiconductor
substrate according to claim 15, wherein in said growth step, said
group III nitride semiconductor layer is grown while a growth
surface of said group III nitride semiconductor layer maintains a
flat uniform surface.
30. The method of manufacturing a group III nitride semiconductor
substrate according to claim 15, wherein at least one raw material
selected from the group consisting of methane, magnesium chloride,
iron chloride, beryllium chloride, zinc chloride, vanadium
chloride, and antimony chloride is used as a raw material for said
impurity element.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a group III nitride
semiconductor substrate having controlled resistivity and low
dislocation density and a manufacturing method thereof.
[0003] 2. Description of the Background Art
[0004] In recent years, development of a group III nitride
semiconductor substrate suitable as a substrate of various
semiconductor devices such as an optical device and an electronic
device, that has controlled resistivity, low dislocation density,
and stable electric characteristic and/or optical characteristic,
has been demanded.
[0005] As a method of significantly lowering dislocation density of
a group III nitride semiconductor substrate, for example, Japanese
Patent Laying-Open No. 2001-102307 (hereinafter, referred to as
Patent Document 1) proposes a method of lowering dislocation
density in a region other than a dislocation-concentrated region
(referred to as low dislocation region here and hereinafter), by
concentrating dislocations within crystals in the
dislocation-concentrated region in the center portion of a pit by
forming and maintaining facets inclosing the pit while crystals of
a group III nitride semiconductor are grown on an underlying
substrate.
[0006] In a GaN substrate obtained with the method according to
Patent Document 1, however, the dislocation-concentrated region and
the low dislocation region have been present in a mixed manner. In
addition, in the low dislocation region as well, a region resulted
from growth using the GaN facet as a growth surface (facet growth
region) has become a region having low resistivity (low resistivity
region), while a region resulted from growth using a GaN C face as
a growth surface (C face growth region) has become a region having
high resistivity (high resistivity region), and therefore, the low
resistivity region and the high resistivity region have been
present in a mixed manner. Therefore, in-plane distribution of
dislocation density and resistivity of the GaN substrate obtained
with the method according to Patent Document 1 has been great.
[0007] In addition, Japanese Patent Laying-Open No. 2000-068498
(hereinafter, referred to as Patent Document 2) proposes forming a
group III nitride semiconductor layer having high resistivity by
adding C (carbon) in high concentration during growth of crystals
of a group III nitride semiconductor, while Japanese Patent
Laying-Open No. 10-112438 (hereinafter, referred to as Patent
Document 3) proposes growth of a p-type group III nitride
semiconductor with fewer crystal defects. Moreover, Japanese Patent
Laying-Open No. 11-026383 (hereinafter, referred to as Patent
Document 4) proposes forming a buffer layer on a substrate, to
which C has been added in advance in high concentration, in order
to grow a group III nitride semiconductor with fewer crystal
defects.
[0008] In any of Patent Documents 2 to 4 above, however, control of
the resistivity has been difficult, and in-plane distribution of
the resistivity has been great. In addition, in the group III
nitride semiconductor layer or the group III nitride semiconductor
layer substrate in any of Patent Documents 2 to 4 above, the
dislocation density thereof cannot be as low as that of the GaN
substrate obtained with the method according to Patent Document 1
above, and stability of the electric characteristic and/or optical
characteristic has been insufficient.
SUMMARY OF THE INVENTION
[0009] An object of the present invention is to provide a group III
nitride semiconductor substrate having controlled resistivity and
low dislocation density and a manufacturing method thereof.
[0010] The present invention is directed to a group III nitride
semiconductor substrate containing at least one element selected
from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb as an
impurity element in concentration of at least 1.times.10.sup.17
cm.sup.-3. In the group III nitride semiconductor substrate,
in-plane distribution of the concentration of the impurity element
represented as a ratio of a maximum concentration to a minimum
concentration of the impurity element in a main surface of the
substrate is in a range from at least 1 to at most 3. The group III
nitride semiconductor substrate has resistivity of at least
1.times.10.sup.4 .OMEGA.cm and thickness of at least 70 .mu.m.
[0011] In addition, the present invention is directed to a group
III nitride semiconductor substrate containing at least one element
selected from the group consisting of O, Si, S, Ge, Se, and Te as
an impurity element in concentration of at least 1.times.10.sup.17
cm.sup.-3. In the group III nitride semiconductor substrate,
in-plane distribution of the concentration of the impurity element
represented as a ratio of a maximum concentration to a minimum
concentration of the impurity element in a main surface of the
substrate is in a range from at least 1 to at most 3. The group III
nitride semiconductor substrate has resistivity of at most 1
.OMEGA.cm and thickness of at least 70 .mu.m.
[0012] In the group III nitride semiconductor substrate according
to the present invention, average dislocation density thereof may
be not higher than 1.times.10.sup.7 cm.sup.-2, and surface density
of a dislocation-concentrated region where dislocation density
exceeds 1.times.10.sup.8 cm.sup.-2 may be not higher than 1
cm.sup.-2; GaN may be employed as the group III nitride; the main
surface thereof may be set at an angle in a range from at least
-5.degree. to at most 5.degree. with respect to any one of a (0001)
surface, a (1-100) surface and a (11-20) surface; a half-width of a
rocking curve in X-ray diffraction may be in a range from at least
10 arcsec to at most 500 arcsec; carrier density may be not higher
than 1.times.10.sup.15 cm.sup.-3, or in a range from at least
1.times.10.sup.17 cm.sup.-3 to at most 1.times.10.sup.20 cm.sup.-3;
and absorption coefficient for light of a wavelength of 450 nm may
be not smaller than 50 cm.sup.-1 or not larger than 10
cm.sup.-1.
[0013] The present invention is directed to a method of
manufacturing a group III nitride semiconductor substrate
including: the growth step of epitaxially growing a first group III
nitride semiconductor layer on an underlying substrate; and the
process step of forming a first group III nitride semiconductor
substrate by cutting and/or surface-polishing the first group III
nitride semiconductor layer. In the growth step, at least one
element selected from the group consisting of C, Mg, Fe, Be, Zn, V,
and Sb is added as an impurity element by at least
1.times.10.sup.17 cm.sup.-3 to the first group III nitride
semiconductor layer.
[0014] The present invention is directed to a method of
manufacturing a group III nitride semiconductor substrate
including: the growth step of epitaxially growing a second group
III nitride semiconductor layer on the first group III nitride
semiconductor layer described above; and the process step of
forming a second group III nitride semiconductor substrate by
cutting and/or surface-polishing the second group III nitride
semiconductor layer. In the growth step, at least one element
selected from the group consisting of O, Si, S, Ge, Se, and Te is
added as an impurity element by at least 1.times.10.sup.17
cm.sup.-3 to the second group III nitride semiconductor layer.
[0015] The method of manufacturing a group III nitride
semiconductor substrate according to the present invention
includes: the growth step of epitaxially growing a third group III
nitride semiconductor layer on the first or second group III
nitride semiconductor substrate described above; and the process
step of forming a third group III nitride semiconductor substrate
by cutting and/or surface-polishing the third group III nitride
semiconductor layer. In the growth step, at least one element
selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb
may be added as an impurity element by at least 1.times.10.sup.17
cm.sup.-3 to the third group III nitride semiconductor layer.
[0016] In addition, the method of manufacturing a group III nitride
semiconductor substrate according to the present invention
includes: the growth step of epitaxially growing a fourth group III
nitride semiconductor layer on the first or second group III
nitride semiconductor substrate described above; and the process
step of forming a fourth group III nitride semiconductor substrate
by cutting and/or surface-polishing the fourth group Ill nitride
semiconductor layer. In the growth step, at least one element
selected from the group consisting of O, Si, S, Ge, Se, and Te may
be added as an impurity element by at least 1.times.10.sup.17
cm.sup.-3 to the fourth group III nitride semiconductor layer.
[0017] Moreover, in the method of manufacturing a group III nitride
semiconductor substrate according to the present invention, any one
of a GaAs substrate, a sapphire substrate, an Si substrate, and an
SiC substrate, or a group III nitride substrate obtained in a facet
growth method may be employed as the underlying substrate. In
addition, in the method of manufacturing a group III nitride
semiconductor substrate according to the present invention, the
growth step may be performed after a mask layer having openings is
formed on at least a part of the underlying substrate.
[0018] As described above, according to the present invention, a
group III nitride semiconductor substrate having controlled
resistivity and low dislocation density and a manufacturing method
thereof can be provided.
[0019] The foregoing and other objects, features, aspects and
advantages of the present invention will become more apparent from
the following detailed description of the present invention when
taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1 is a schematic cross-sectional view showing a method
of manufacturing a group III nitride semiconductor substrate
according to the present invention, and (a) shows the step of
growing a group III nitride semiconductor layer and (b) shows the
step of processing the group III nitride semiconductor layer.
[0021] FIG. 2 is a schematic cross-sectional view showing another
method of manufacturing a group III nitride semiconductor substrate
according to the present invention, and (a) shows the step of
growing a group III nitride semiconductor layer and (b) shows the
step of processing the group III nitride semiconductor layer.
[0022] FIGS. 3 to 5 are schematic cross-sectional views showing yet
other methods of manufacturing a group III nitride semiconductor
substrate according to the present invention, and (a) shows the
step of growing a group III nitride semiconductor layer and (b)
shows the step of processing the group III nitride semiconductor
layer.
[0023] FIG. 6 is a schematic cross-sectional view showing a method
of manufacturing a group III nitride semiconductor substrate using
a facet growth method, and (a) shows the step of forming a mask
layer, (b) shows the step of growing a group III nitride
semiconductor layer, and (c) shows the step of processing the group
III nitride semiconductor layer.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0024] (Embodiment 1)
[0025] A group III nitride semiconductor substrate according to the
present invention contains at least one impurity element selected
from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb as an
impurity element in concentration not lower than 1.times.10.sup.17
cm.sup.-3. In the group III nitride semiconductor substrate,
in-plane distribution of the concentration of the impurity element
represented as a ratio of the maximum concentration to the minimum
concentration of the impurity element in the main surface of the
substrate is in a range from at least 1 to at most 3. The group III
nitride semiconductor substrate has resistivity of at least
1.times.10.sup.4 .OMEGA.cm and thickness of at least 70 .mu.m.
[0026] The group III nitride semiconductor substrate contains at
least one element from among C, Mg, Fe, Be, Zn, V, and Sb as an
impurity element by at least 1.times.10.sup.17 cm.sup.-3, so that
in-plane distribution of the concentration of the impurity element
(ratio of the maximum concentration to the minimum concentration)
in the main surface of the substrate is reduced to a value in a
range from at least 1 to at most 3, and a deep acceptor level
because of these elements is formed. Therefore, resistivity of the
substrate can be controlled to high, that is, at least
1.times.10.sup.4 .OMEGA.cm.
[0027] Preferably, in the group III nitride semiconductor substrate
in the present embodiment, average dislocation density is at most
1.times.10.sup.7 cm.sup.-2, and surface density of a
dislocation-concentrated region where dislocation density exceeds
1.times.10.sup.8 cm.sup.-2 is at most 1 cm.sup.-2. Uniform in-plane
distribution of the dislocation density is achieved, so that the
electric characteristic and/or optical characteristic stable as the
substrate of a semiconductor device can be obtained. The present
inventors found that at least one element from among C, Mg, Fe, Be,
Zn, V, and Sb added to the group III nitride semiconductor
substrate in the present embodiment effectively has a
characteristic to suppress generation of dislocation and to
mitigate concentration of dislocation during crystal growth, and
the present inventors could obtain a group III nitride
semiconductor substrate attaining average dislocation density of at
most 1.times.10.sup.7 cm.sup.-2 and surface density of the
dislocation-concentrated region where dislocation density exceeds
1.times.10.sup.8 cm.sup.-2 of at most 1 cm.sup.-2, by adding at
least one element from among C, Mg, Fe, Be, Zn, V, and Sb by at
least 1.times.10.sup.17 cm.sup.-3 in growing the group III nitride
semiconductor.
[0028] Preferably, the group III nitride semiconductor substrate in
the present embodiment is implemented by a GaN substrate. The GaN
substrate having the resistivity controlled to at least
1.times.10.sup.4 .OMEGA.cm and a thickness not smaller than 70
.mu.m can widely be used as the substrate of the semiconductor
device.
[0029] The group III nitride semiconductor substrate in the present
embodiment preferably has the main surface at an angle in a range
from at least -5.degree. to at most 5.degree. with respect to any
one of a (0001) surface, a (1-100) surface and a (11-20) surface.
On the group III nitride semiconductor substrate having such a main
surface, the group III nitride semiconductor layer having excellent
crystallinity can be formed, and the semiconductor device having
stable electric characteristic and/or optical characteristic can be
obtained.
[0030] Preferably, the group III nitride semiconductor substrate in
the present embodiment has a half-width of a rocking curve in X-ray
diffraction in a range from at least 10 arcsec to at most 500
arcsec. On such a group III nitride semiconductor substrate
attaining excellent crystallinity, the group Hi nitride
semiconductor layer having excellent crystallinity can be formed,
and the semiconductor device having stable electric characteristic
and/or optical characteristic can be obtained. In the present
embodiment, by adding at least one element from among C, Mg, Fe,
Be, Zn, V, and Sb by at least 1.times.10.sup.17 cm.sup.-3 to the
group III nitride semiconductor substrate, the group III nitride
semiconductor substrate attaining a half-width of a rocking curve
in X-ray diffraction in a range from at least 10 arcsec to at most
500 arcsec and excellent crystallinity can be obtained.
[0031] Preferably, the group III nitride semiconductor substrate in
the present embodiment attains the carrier density not higher than
1.times.10.sup.15 cm.sup.-3. In the present embodiment, by adding
at least one element from among C, Mg, Fe, Be, Zn, V, and Sb by at
least 1.times.10.sup.17 cm.sup.-3 to the group III nitride
semiconductor substrate, the group III nitride semiconductor
substrate attaining the carrier density not higher than
1.times.10.sup.15 cm.sup.-3 can be obtained, and the resistivity
thereof can readily be controlled to at least 1.times.10.sup.4
.OMEGA.cm.
[0032] Preferably, in the group III nitride semiconductor substrate
in the present embodiment, the absorption coefficient for light of
a wavelength of 450 nm is at least 50 cm.sup.-1. In the present
embodiment, by adding at least one element from among C, Mg, Fe,
Be, Zn, V, and Sb by at least 1.times.10.sup.17 cm.sup.-3 to the
group III nitride semiconductor substrate, the group III nitride
semiconductor substrate attaining the resistivity controlled to at
least 1.times.10.sup.4 .OMEGA.cm and the absorption coefficient for
light of a wavelength of 450 nm of at least 50 cm.sup.-1 can be
obtained.
[0033] (Embodiment 2)
[0034] Another group III nitride semiconductor substrate according
to the present invention contains at least one element selected
from the group consisting of O, Si, S, Ge, Se, and Te as an
impurity element in concentration not lower than 1.times.10.sup.17
cm.sup.-3. In the group III nitride semiconductor substrate,
in-plane distribution of the concentration of the impurity element
represented as a ratio of the maximum concentration to the minimum
concentration of the impurity element in the main surface of the
substrate is in a range from at least 1 to at most 3. The group III
nitride semiconductor substrate has resistivity of at most 1
.OMEGA.cm and thickness of at least 70 .mu.m.
[0035] The group III nitride semiconductor substrate contains at
least one element from among O, Si, S, Ge, Se, and Te as an
impurity element by at least 1.times.10.sup.17 cm.sup.-3, so that
in-plane distribution of the concentration of the impurity element
(ratio of the maximum concentration to the minimum concentration)
in the main surface of the substrate is reduced to a value in a
range from at least 1 to at most 3, and a shallow donor level
because of these elements is formed. Therefore, resistivity of the
substrate can be controlled to low, that is, at most 1
.OMEGA.cm.
[0036] Preferably, as in the case of the group III nitride
semiconductor substrate in Embodiment 1, in the group III nitride
semiconductor substrate in the present embodiment, average
dislocation density is at most 1.times.10.sup.7 cm.sup.-2 and
surface density of a dislocation-concentrated region where
dislocation density exceeds 1.times.10.sup.8 cm.sup.-2 is at most 1
cm.sup.-2; the GaN substrate is employed; the main surface thereof
is at an angle in a range from at least -5.degree. to at most
5.degree. with respect to any one of a (0001) surface, a (1-100)
surface and a (11-20) surface; and a half-width of a rocking curve
in X-ray diffraction is in a range from at least 10 arcsec to at
most 500 arcsec.
[0037] Preferably, the group III nitride semiconductor substrate in
the present embodiment attains the carrier density in a range from
at least 1.times.10.sup.17 cm.sup.-3 to at most 1.times.10.sup.20
cm.sup.-3. In the present embodiment, by adding at least one
element from among O, Si, S, Ge, Se, and Te by at least
1.times.10.sup.17 cm.sup.-3 to the group III nitride semiconductor
substrate, the group III nitride semiconductor substrate attaining
the carrier density in a range from at least 1.times.10.sup.17
cm.sup.-3 to at most 1.times.10.sup.20 cm.sup.-3 can be obtained,
and the resistivity thereof can readily be controlled to at most 1
.OMEGA.cm.
[0038] Preferably, the group III nitride semiconductor substrate in
the present embodiment attains the absorption coefficient for light
of a wavelength of 450 nm of at most 10 cm.sup.--1. In the present
embodiment, by adding at least one element from among O, Si, S, Ge,
Se, and Te by at least 1.times.10.sup.17 cm.sup.-3 to the group III
nitride semiconductor substrate, the group III nitride
semiconductor substrate attaining the resistivity controlled to at
most 1 .OMEGA.cm and the absorption coefficient for light of a
wavelength of 450 nm of at most 10 cm.sup.-1 can be obtained.
[0039] (Embodiment 3)
[0040] Referring to FIG. 1, a method of manufacturing a group III
nitride semiconductor substrate according to the present invention
includes: the growth step of epitaxially growing a first group III
nitride semiconductor layer 11 on an underlying substrate 1 as
shown in FIG. 1(a); and the process step of forming first group III
nitride semiconductor substrates 11a, 11b, 11c, and 11d by cutting
and/or surface-polishing first group III nitride semiconductor
layer 11 as shown in FIG. 1(b). In the growth step, at least one
element from among C, Mg, Fe, Be, Zn, V, and Sb is added as an
impurity element by at least 1.times.10.sup.17 cm.sup.-3 to first
group III nitride semiconductor layer 11.
[0041] By adding at least one element from among C, Mg, Fe, Be, Zn,
V, and Sb as an impurity element by at least 1.times.10.sup.17
cm.sup.-3 in epitaxially growing first group III nitride
semiconductor layer 11, high-resistivity first group Ill nitride
semiconductor layer 11 and first group III nitride semiconductor
substrates 11a, 11b, 11c, and 11d having the resistivity controlled
to at least 1.times.10.sup.4 .OMEGA.cm can be obtained. In
addition, as the impurity element suppresses generation of
dislocation and mitigates concentration of dislocation during
growth of the first group III nitride semiconductor layer, the
group III nitride semiconductor substrate having low dislocation
density (for example, the average dislocation density is not higher
than 1.times.10.sup.7 cm.sup.-2, and surface density of the
dislocation-concentrated region where dislocation density exceeds
1.times.10.sup.8 cm.sup.-2 is not higher than 1 cm.sup.-2) can be
obtained.
[0042] Here, the method of growing the group III nitride
semiconductor layer is not particularly limited, so long as the
method is capable of epitaxially growing the group III nitride
semiconductor layer on the underlying substrate. Various vapor
deposition methods such as HVPE (hydride vapor phase epitaxy)
method, MOCVD (metal-organic chemical vapor deposition) method, and
MBE (molecular beam epitaxy) method may be used. From a viewpoint
of more efficiently obtaining a thick group III nitride
semiconductor substrate (for example, thickness of 70 .mu.m or
greater), the HVPE method attaining higher growth rate is more
preferred.
[0043] The underlying substrate used in the method of manufacturing
the group III nitride semiconductor substrate of the present
embodiment is not particularly limited, so long as the group III
nitride semiconductor layer can epitaxially be grown on the
underlying substrate. Here, a GaAs substrate, a sapphire substrate,
an Si substrate, or an SiC substrate (particularly, a hexagonal
system SiC substrate) is preferably employed. This is because
mismatch of the crystal lattice between these substrates and the
group III nitride semiconductor is less likely.
[0044] From a viewpoint of lower dislocation density of the group
III nitride semiconductor layer, the group III nitride substrate
obtained in a facet growth method is more preferably employed as
the underlying substrate. The reason why the dislocation density of
the group III nitride semiconductor layer is lowered will be
described in detail below.
[0045] Here, characteristics of the method of manufacturing the
group III nitride semiconductor substrate using the facet growth
method and group III nitride substrates 31a, 31b, 31c, and 31d
obtained with that method will be described with reference to FIG.
6. Initially, as shown in FIG. 6(a), a mask layer 2 having openings
is formed on at least a part of underlying substrate 1, and a group
III nitride semiconductor layer 31 is epitaxially grown on
underlying substrate 1 through the openings of mask layer 2, as
shown in FIG. 6(b). Here, a sapphire substrate, an Si substrate, an
SiC substrate, or the like is used as underlying substrate 1, and
an SiO.sub.2 layer or the like is used as the mask layer. The HVPE
method or the like is used as the method of epitaxial growth.
[0046] Referring to FIG. 6(b), the facet growth method of the group
III nitride semiconductor layer is a method of forming a facet 31f,
which is a surface other than a surface (average growth surface
31h) perpendicular to an average growth direction of the group III
nitride semiconductor layer, and growing a group III nitride
semiconductor layer while maintaining the facet. As a result of
crystal growth on facet 31f, dislocation within the group III
nitride semiconductor layer is concentrated in a central portion of
a pit 31p formed by a plurality of facets 31f, thus forming a
dislocation-concentrated region 31t. As the dislocations within the
group III nitride semiconductor layer are concentrated in
dislocation-concentrated region 31t, the dislocation density in a
region (low dislocation region 31u) other than the
dislocation-concentrated region is significantly lowered.
[0047] Referring next to FIG. 6(c), epitaxially grown group III
nitride semiconductor layer 31 is cut to a prescribed thickness and
its surface is polished, so as to manufacture group III nitride
semiconductor substrates 31a, 31b, 31c, and 31d. Here,
dislocation-concentrated region 31t and low dislocation region 31u
formed in group III nitride semiconductor layer 31 remain also in
group III nitride semiconductor substrates 31a, 31b, 31c, and 31d.
In addition, due to the difference in an amount of incorporation of
the impurity element, in low dislocation region 31u as well, a
region resulted from growth using facet 31f as a growth surface
(facet growth region) has become a region having low resistivity
(low resistivity region), while a region resulted from growth using
average growth surface 31h as a growth surface (average growth
surface growth region) has become a region having high resistivity
(high resistivity region), and therefore, the low resistivity
region and the high resistivity region have been present in a mixed
manner. Therefore, it is difficult to control the resistivity of
the group III nitride semiconductor substrate obtained with the
facet growth method.
[0048] Therefore, in order to manufacture the group III nitride
semiconductor substrate having controlled resistivity, the group
III nitride semiconductor is desirably grown, using as the growth
surface, a uniform surface where there is no difference in the
amount of incorporation of the impurity element. In other words, in
the growth step, the group III nitride semiconductor layer is
preferably grown while the average growth surface of the group III
nitride semiconductor layer maintains a flat uniform surface. In
the present embodiment, it is considered that, by adding at least
one element from among C, Mg, Fe, Be, Zn, V, and Sb as the impurity
element by at least 1.times.10.sup.17 cm.sup.-3 to the first group
III nitride semiconductor layer during epitaxial growth of the
first group III semiconductor layer, the group III nitride
semiconductor layer can be. grown while the average growth surface
of the group III nitride semiconductor layer maintains a flat
uniform surface, and that lowering in the in-plane distribution of
the resistivity in the main surface of the substrate, suppression
of generation of the dislocation and/or mitigation of concentration
of the dislocation are achieved during epitaxial growth of the
first group III nitride semiconductor layer.
[0049] Here, paying attention to the fact that the dislocation
density of the group III nitride semiconductor substrate obtained
with the facet growth method is lower in a portion except for
dislocation-concentrated region 31t and the fact that generation of
dislocation is suppressed and concentration of the dislocation is
mitigated during the growth of the group III nitride semiconductor
layer by adding at least one element from among C, Mg, Fe, Be, Zn,
V, and Sb as the impurity element by at least 1.times.10.sup.17
cm.sup.-3 in growing the group III nitride semiconductor layer, the
present inventors have achieved manufacture of the group III
nitride semiconductor substrate having controlled high resistivity
and low dislocation density, by using the group III nitride
semiconductor substrate obtained with the facet growth method as
the underlying substrate and by growing the group III nitride
semiconductor layer while adding at least one element from among C,
Mg, Fe, Be, Zn, V, and Sb as the impurity element by at least
1.times.10.sup.17 cm.sup.-3 to the group III nitride semiconductor
layer.
[0050] In other words, even when the group III nitride
semiconductor layer is epitaxially grown on the group III nitride
semiconductor substrate obtained in the facet growth method and
employed as the underlying substrate under the conventional general
condition, the group III nitride semiconductor layer takes over the
dislocation in the dislocation-concentrated region in the group III
nitride semiconductor substrate obtained in facet growth.
Therefore, it has been difficult to lower the dislocation density
of the group III nitride semiconductor layer.
[0051] In contrast, by growing the group III nitride semiconductor
layer on the group III nitride semiconductor substrate obtained
with the facet growth method and employed as the underlying
substrate while adding the impurity element having a characteristic
to suppress generation of dislocation and to mitigate concentration
of dislocation by at least 1.times.10.sup.17 cm.sup.-3, the group
III nitride semiconductor substrate having controlled high
resistivity and low dislocation density can be manufactured.
[0052] If the underlying substrate used in the method of
manufacturing the group III nitride semiconductor substrate of the
present embodiment is implemented by hexagonal system crystals, the
main surface of the underlying substrate is preferably at an angle
in a range from at least -5.degree. to at most 5.degree. with
respect to any one of a (0001) surface, a (1-100) surface and a
(11-20) surface. If the main surface is implemented as such, the
group III nitride semiconductor layer and the group III nitride
semiconductor substrate attaining low dislocation density and
excellent crystallinity are more likely to be obtained.
[0053] In the method of manufacturing the group III nitride
semiconductor substrate of the present embodiment, the material for
the impurity element is not particularly limited, however, from a
viewpoint of easy crystal growth, at least one raw material from
among methane (CH.sub.4), magnesium chloride (MgCl.sub.2 and the
like), iron chloride (FeCl.sub.2 and the like), beryllium chloride
(BeCl.sub.2 and the like), zinc chloride (ZnCl.sub.2 and the like),
vanadium chloride (VCl.sub.2 and the like), and antimony chloride
(SbCl and the like) is preferably employed. As to magnesium, iron,
beryllium, zinc, vanadium, antimony, and the like, a metal of these
elements and a hydrochloric gas may be caused to react, so that the
resultant gas is used as a raw material.
[0054] (Embodiment 4)
[0055] Referring to FIG. 2, in another method of manufacturing the
group III nitride semiconductor substrate according to the present
invention, after mask layer 2 having openings is formed on at least
a part of underlying substrate 1, the growth step (FIG. 2(a)) and
the process step (FIG. 2(b)) the same as in Embodiment 3 are
performed. By growing first nitride semiconductor layer 11 on
underlying substrate 1 through the openings of mask layer 2, what
is called lateral growth is carried out. Accordingly, the
dislocation density of first group III nitride semiconductor layer
11 can further be lowered. Here, an SiO.sub.2 layer, an
Si.sub.xN.sub.y layer or the like is used as the mask layer having
openings, and it is formed with sputtering, thermal CVD, or the
like.
[0056] (Embodiment 5)
[0057] Referring to FIG. 3, yet another method of manufacturing a
group III nitride semiconductor substrate according to the present
invention includes: the growth step of epitaxially growing a second
group III nitride semiconductor layer 12 on first group III nitride
semiconductor layer 11 that has grown on underlying substrate 1 in
Embodiment 3 or 4, as shown in FIG. 3(a); and the process step of
forming second group III nitride semiconductor substrates 12a, 12b,
and 12c by cutting and/or surface-polishing second group III
nitride semiconductor layer 12 as shown in FIG. 3(b). In the growth
step, at least one element selected from the group consisting of O,
Si, S, Ge, Se, and Te is added as an impurity element by at least
1.times.10.sup.17 cm.sup.-3 to second group III nitride
semiconductor layer 12.
[0058] By adding at least one element from among O, Si, S, Ge, Se,
and Te as an impurity element by at least 1.times.10.sup.17
cm.sup.-3 in epitaxially growing second group III nitride
semiconductor layer 12, low-resistivity second group III nitride
semiconductor layer 12 and second group III nitride semiconductor
substrates 12a, 12b and 12c having the resistivity controlled to at
most 1 .OMEGA.cm can be obtained. In addition, as second group III
nitride semiconductor layer 12 and second group III nitride
semiconductor substrates 12a, 12b and 12c are epitaxially grown on
first group III nitride semiconductor layer 11 attaining low
dislocation density, the dislocation density thereof is low (for
example, the average dislocation density can be not higher than
1.times.10.sup.7 cm.sup.-2, and surface density of the
dislocation-concentrated region where dislocation density exceeds
1.times.10.sup.8 cm.sup.-2 can be not higher than 1 cm.sup.-2).
[0059] The raw material for the impurity element is not
particularly limited in the method of manufacturing the group III
nitride semiconductor substrate of the present embodiment, however,
from a viewpoint of easy crystal growth, at least one raw material
from among oxygen (O.sub.2), water (H.sub.2O), dichlorosilane
(SiH.sub.2Cl.sub.2), tetrachlorosilane (SiCl.sub.4), hydrogen
sulfide (H.sub.2S), germanium chloride (GeCl.sub.4), selenium
chloride (SeCl.sub.4), and tellurium chloride (TeCl.sub.4) is
preferably employed. As to germanium, selenium, tellurium, and the
like, a metal of these elements and a hydrochloric gas may be
caused to react, so that the resultant gas is used as a raw
material.
[0060] (Embodiment 6)
[0061] Referring to FIG. 4, yet another method of manufacturing a
group III nitride semiconductor substrate according to the present
invention includes: the growth step of epitaxially growing a third
group III nitride semiconductor layer 21 on a first or second group
III nitride semiconductor substrate 10 formed in the manufacturing
method in any one of Embodiments 3 to 5, as shown in FIG. 4(a); and
the process step of forming third group III nitride semiconductor
substrates 21a, 21b, 21c, and 21d by cutting and/or
surface-polishing third group III nitride semiconductor layer 21 as
shown in FIG. 4(b). In the growth step, at least one element
selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb
is added as an impurity element by at least 1.times.10.sup.17
cm.sup.-3 to third group III nitride semiconductor layer 21.
[0062] By adding at least one element from among C, Mg, Fe, Be, Zn,
V, and Sb as an impurity element by at least 1.times.10.sup.17
cm.sup.-3 in epitaxially growing third group III nitride
semiconductor layer 21, high-resistivity third group III nitride
semiconductor layer 21 and third group III nitride semiconductor
substrates 21a, 21b, 21c, and 21d having the resistivity controlled
to at least 1.times.10.sup.4 .OMEGA.cm can be obtained. In
addition, as third group III nitride semiconductor layer 21 and
third group III nitride semiconductor substrates 21a, 21b, 21c, and
21d are epitaxially grown on first or second group III nitride
semiconductor substrate 10 attaining low dislocation density and as
the impurity element having a characteristic to suppress generation
of dislocation and to mitigate concentration of dislocation is
added by at least 1.times.10.sup.17 cm.sup.-3, the dislocation
density thereof is further lowered.
[0063] (Embodiment 7)
[0064] Referring to FIG. 5, yet another method of manufacturing a
group III nitride semiconductor substrate according to the present
invention includes: the growth step of epitaxially growing a fourth
group III nitride semiconductor layer 22 on first or second group
III nitride semiconductor substrate 10 formed in the method of
manufacturing the group III nitride semiconductor substrate in any
one of Embodiments 3 to 5 as shown in FIG. 5(a); and the process
step of forming fourth group III nitride semiconductor substrates
22a, 22b, 22c, and 22d by cutting and/or surface-polishing fourth
group III nitride semiconductor layer 22 as shown in FIG. 5(b). In
the growth step, at least one element selected from the group
consisting of O, Si, S, Ge, Se, and Te is added as an impurity
element by at least 1.times.10.sup.17 cm.sup.-3 to fourth group III
nitride semiconductor layer 22.
[0065] By adding at least one element from among O, Si, S, Ge, Se,
and Te as an impurity element by at least 1.times.10.sup.17
cm.sup.-3 in epitaxially growing fourth group III nitride
semiconductor layer 22, low-resistivity fourth group III nitride
semiconductor layer 22 and fourth group III nitride semiconductor
substrates 22a, 22b, 22c, and 22d having the resistivity controlled
to at most 1 .OMEGA.cm can be obtained. In addition, as fourth
group III nitride semiconductor layer 22 and fourth group III
nitride semiconductor substrates 22a, 22b, 22c, and 22d are
epitaxially grown on first or second group III nitride
semiconductor substrate 10 attaining low dislocation density, the
dislocation density thereof is low.
EXAMPLE 1
[0066] Referring to FIG. 1(a), the GaN substrate (the main surface
of the substrate is at an angle of 1.degree. in a direction of
{1-100} surface with respect to (0001) surface) grown with the
facet growth method (the method described in Patent Document 1) in
the HVPE method was used as underlying substrate 1, and the
high-resistivity GaN layer was grown as first group III nitride
semiconductor layer 11 to a thickness of 2000 .mu.m, using the HVPE
method. A GaCl gas obtained by bringing an HCl gas in contact to
gallium metal at 800.degree. C. was used as the Ga source, and an
NH.sub.3 gas was used as the N source. In addition, a methane gas
was used as the impurity element raw material for adding C
representing the impurity element. Moreover, an H.sub.2 gas was
used as the carrier gas.
[0067] Here, the condition for epitaxial growth of the GaN layer
using the HVPE method was set as follows: growth temperature
(temperature of the underlying substrate) of 1050.degree. C.; total
pressure of 100 kPa (1.0 atmospheric pressure); partial pressure of
NH.sub.3 of 20 kPa (0.2 atmospheric pressure); partial pressure of
GaCl of 0.5 kPa (5.times.10.sup.-3 atmospheric pressure); partial
pressure of the impurity element raw material in a range from
0.0001 kPa (1.times.10.sup.-6 atmospheric pressure) to 1.0 kPa
(1.times.10.sup.-2 atmospheric pressure); and the growth time
period of 10 hours.
[0068] Referring next to FIG. 1(b), the obtained GaN layer was cut
in parallel to the main surface of the substrate, and the surface
thereof was polished, thus obtaining the high-resistivity GaN
substrate having a thickness of 300 .mu.m.
[0069] The content of impurity element C in the obtained GaN
substrate was measured using SIMS (secondary ion mass
spectrometry). The ninimum concentration of C was 10.sup.18
cm.sup.-3, and the in-plane distribution of the concentration of C
(maximum concentration/minimum concentration) was 1.5. When the
resistivity of the GaN substrate was measured, the resistivity was
controlled to at least 1.times.10.sup.7 .OMEGA.cm. When the average
dislocation density of the GaN substrate was measured with TEM
(transmission electron microscope), the average dislocation density
was 1.times.10.sup.6 cm.sup.-2. When the surface density of the
dislocation-concentrated region (the region where dislocation
density exceeds 1.times.10.sup.8 cm.sup.-2; to be understood
similarly hereinafter) in the GaN substrate was measured using CL
(cathode luminescence), the surface density was not higher than 1
cm.sup.-2. The half-width of the rocking curve in X-ray diffraction
of the GaN substrate was 60 arcsec. When the carrier density of the
GaN.substrate was evaluated using C (charge)-V (voltage)
measurement, the carrier density was not higher than
1.times.10.sup.15 cm.sup.-3, and measurement thereof was
impossible. When the absorption coefficient for light of a
wavelength of 450 nm of the GaN substrate was measured with a
spectrophotometer, the absorption coefficient for light was not
smaller than 50 cm.sup.-1. Table 1 summarizes the result.
EXAMPLE 2
[0070] The high-resistivity GaN substrate was obtained in a manner
the same as in Example 1, except for using magnesium chloride
(MgCl.sub.2) as the impurity element raw material. The minimum
concentration of impurity element Mg in the obtained GaN substrate
was 1.times.10.sup.18 cm.sup.-3, the in-plane distribution of the
concentration of Mg 5 (maximum concentration/minimum concentration)
was 2.5, the resistivity was not lower than 1.times.10.sup.5
.OMEGA.cm, the average dislocation density was 1.times.10.sup.6
cm.sup.-2, the surface density of the dislocation-concentrated
region was not higher than 1 cm.sup.-2, the half-width of the
rocking curve in X-ray diffraction was 80 arcsec, the carrier
density was not higher than 1.times.10.sup.15 cm.sup.-3, and the
absorption coefficient for light of a wavelength of 450 nm was not
smaller than 50 cm.sup.-1. Table 1 summarizes the result.
EXAMPLE 3
[0071] The high-resistivity GaN substrate was obtained in a manner
the same as in Example 1, except for using an iron chloride
(FeCl.sub.2) gas generated as a result-of reaction of iron and
hydrochloric gas as the impurity element raw material. The 15
minimum concentration of impurity element Fe in the obtained GaN
substrate was 1.times.10.sup.18 cm.sup.-3, the in-plane
distribution of the concentration of Fe (maximum
concentration/minimum concentration) was 2.0, the resistivity was
not lower than 1.times.10.sup.7 .OMEGA.cm, the average dislocation
density was 1.times.10.sup.6 cm.sup.-2, the surface density of the
dislocation-concentrated region was not higher than 1 cm.sup.-2,
the half-width of the rocking curve in X-ray diffraction was 80
arcsec, the carrier density was not higher than b 1.times.10.sup.15
cm.sup.-3, and the absorption coefficient for light of a wavelength
of 450 nm was not smaller than 50 cm.sup.-3. Table 1 summarizes the
result.
EXAMPLE 4
[0072] Referring to FIG. 2(a), the GaN substrate (the main surface
of the substrate is at an angle of 1.degree. in a direction of
{1100} surface with respect to (0001) surface) grown with the facet
growth method (the method described in Patent Document 1) in the
HVPE method was used as underlying substrate 1. The
high-resistivity GaN substrate was obtained in a manner the same as
in Example 1 after the SiO.sub.2 layer having a thickness of 0.1
.mu.m, in which openings each having a size of 2 .mu.m.times.2
.mu.m were uniformly distributed in a shape like a close-packed
structure, was formed as mask layer 2 having openings, on at least
a part of the GaN substrate serving as underlying substrate 1.
Here, mask layer 2 was obtained by forming the SiO.sub.2 layer to a
thickness of 0.1 .mu.m using sputtering, and thereafter forming
openings each having a size of 2 .mu.m.times.2 .mu.m with
photolithography such that they are uniformly distributed in a
shape like a close-packed structure. The minimum concentration of
impurity element C in the obtained GaN substrate was
1.times.10.sup.18 cm.sup.-3, the in-plane distribution of the
concentration of C (maximum concentration/minimum concentration)
was 1.5, the resistivity was not lower than 1.times.10.sup.7
.OMEGA.cm, the average dislocation density was 1.times.10.sup.5
cm.sup.-2, the surface density of the dislocation-concentrated
region was not higher than 1 cm.sup.-2, the half-width of the
rocking curve in X-ray diffraction was 50 arcsec, the carrier
density was not higher than 1.times.10.sup.15 cm.sup.-3, and the
absorption coefficient for light of a wavelength of 450 nm was not
smaller than 50 cm.sup.-1. Table 1 summarizes the result.
EXAMPLE 5
[0073] The high-resistivity GaN substrate was obtained in a manner
the same as in Example 4, except for employing a sapphire substrate
(the main surface of the substrate is at an angle of 1.degree. in a
direction of {1100} surface with respect to (0001) surface) as
underlying substrate 1. The minimum concentration of impurity
element C in the obtained GaN substrate was 1.times.10.sup.18
cm.sup.-3, the in-plane distribution of the concentration of C
(maximum concentration/minimum concentration) was 1.5, the
resistivity was not lower than 1.times.10.sup.7 .OMEGA.cm, the
average dislocation density was 1.times.10.sup.7 cm.sup.-2, the
surface density of the dislocation-concentrated region was not
higher than 1 cm.sup.-2, the half-width of the rocking curve in
X-ray diffraction was 100 arcsec, the carrier density was not
higher than 1.times.10.sup.15 cm.sup.-3, and the absorption
coefficient for light of a wavelength of 450 nm was not smaller
than 50 cm.sup.-1. Table 1 summarizes the result.
EXAMPLE 6
[0074] The high-resistivity GaN substrate was obtained in a manner
the same as in Example 4, except for employing a GaAs substrate
(the main surface of the substrate is at an angle of 1.degree. in a
direction of {011} surface with respect to (111) Ga surface) as
underlying substrate 1. The minimum concentration of impurity
element C in the obtained GaN substrate was 1.times.10.sup.18
cm.sup.-3, the in-plane distribution of the concentration of C
(maximum concentration/minimum concentration) was 1. 5, the
resistivity was not lower than 1.times.10.sup.7 .OMEGA.cm, the
average dislocation density was 2.times.10.sup.7 cm.sup.-2, the
surface density of the dislocation-concentrated region was not
higher than 1 cm.sup.-2, the half-width of the rocking curve in
X-ray diffraction was 110 arcsec, the carrier density was not
higher than 1 .times.10.sup.15 cm.sup.-3, and the absorption
coefficient for light of a wavelength of 450 nm was not smaller
than 50 cm.sup.-1. Table 1 summarizes the result.
EXAMPLE 7
[0075] The high-resistivity GaN substrate was obtained in a manner
the same as in Example 4, except for employing a 6H-SiC substrate
(the main surface of the substrate is at an angle of 1.degree. in a
direction of {1-100} surface with respect to (0001) surface). as
underlying substrate 1. The minimum concentration of impurity
element C in the obtained GaN substrate was 1.times.10.sup.18
cm.sup.-3, the in-plane distribution of the concentration of C
(maximum concentration/minimum concentration) was 1. 5, the
resistivity was not lower than 1.times.10.sup.7 .OMEGA.cm, the
average dislocation density was 4.times.10.sup.7 cm.sup.-2, the
surface density of the dislocation-concentrated region was not
higher than 1 cm.sup.-2, the half-width of the rocking curve in
X-ray diffraction was 130 arcsec, the carrier density was not
higher than 1.times.10.sup.15 cm.sup.-3, and the absorption
coefficient for light of a wavelength of 450 nm was not smaller
than 50 cm.sup.-1. Table 1 summarizes the result.
Comparative Example 1
[0076] In the GaN substrate grown with the facet growth method (the
method described in Patent Document 1) in the HVPE method and used
as underlying substrate 1 in Example 1 (the main surface of the
substrate is at an angle of 1.degree. in a direction of {1-100}
surface with respect to (0001) surface), the minimum concentration
of the impurity element was 1.times.10.sup.16 cm.sup.-3, the
in-plane distribution of the concentration of the impurity element
(maximum concentration/minimum concentration) was 30, the
resistivity was 0.01 .OMEGA.cm, the average dislocation density was
1.times.10.sup.6 cm.sup.-2, the surface density of the
dislocation-concentrated region was 500 cm.sup.-2, the half-width
of the rocking curve in X-ray diffraction was 60 arcsec, the
carrier. density was not higher than 1.times.10.sup.18 cm.sup.-3,
and the absorption coefficient for light of a wavelength of 450 nm
was not larger than 30 cm.sup.-1. Table 1 summarizes the result.
TABLE-US-00001 TABLE 1 Comparative Example 1 Example 2 Example 3
Example 4 Example 5 Example 6 Example 7 Example 1 Under-
Composition GaN GaN GaN GaN sapphire GaAs 6H--SiC lying Angle of
main surface 1.degree. in 1.degree. in 1.degree. in 1.degree. in
1.degree. in 1.degree. in 1.degree. in substrate direction of
direction of direction of direction of direction of direction of
direction of {1-100} {1-100} {1-100} {1100} {1100} {011} from
{1-100} from (0001) from (0001) from (0001) from (0001) from (0001)
(111) Ga from (0001) surface surface surface surface surface
surface surface Presence/absence of mask layer absent absent absent
present present present present Doping material CH.sub.4 MgCl.sub.2
FeCl.sub.2 CH.sub.4 CH.sub.4 CH.sub.4 CH.sub.4 Group III Im- Type C
Mg Fe C C C C various nitride purity Minimum 1 .times. 10.sup.18 1
.times. 10.sup.18 1 .times. 10.sup.18 1 .times. 10.sup.18 1 .times.
10.sup.18 1 .times. 10.sup.18 1 .times. 10.sup.18 1 .times.
10.sup.16 semi- element concen- conductor tration substrate
(cm.sup.-3) In-plane 1.5 2.5 2.0 1.5 1.5 1.5 1.5 30 distribution
(maximum concen- tration/ minimum concen- tration) Resistivity 1
.times. 10.sup.7 or 1 .times. 10.sup.5 or 1 .times. 10.sup.7 or 1
.times. 10.sup.7 or 1 .times. 10.sup.7 or 1 .times. 10.sup.7 or 1
.times. 10.sup.7 or 0.01 (.OMEGA. cm) higher higher higher higher
higher higher higher Average dislocation 1 .times. 10.sup.6 1
.times. 10.sup.6 1 .times. 10.sup.6 1 .times. 10.sup.5 1 .times.
10.sup.7 2 .times. 10.sup.7 4 .times. 10.sup.7 1 .times. 10.sup.6
density (cm.sup.-2) Surface density of 1 or lower 1 or lower 1 or
lower 1 or lower 1 or lower 1 or lower 1 or lower 500 dislocation-
concentrated region (cm.sup.-2) Half-width of rocking 60 80 80 50
100 110 130 60 curve (arcsec) Carrier density 1 .times. 10.sup.15
or 1 .times. 10.sup.15 or 1 .times. 10.sup.15 or 1 .times.
10.sup.15 or 1 .times. 10.sup.15 or 1 .times. 10.sup.15 or 1
.times. 10.sup.15 or 1 .times. 10.sup.18 (cm.sup.-3) lower lower
lower lower lower lower lower Absorption 50 or 50 or 50 or 50 or 50
or 50 or 50 or 30 or smaller coefficient for light larger larger
larger larger larger larger larger (cm.sup.-1)
[0077] As can clearly be seen from Table 1, by adding at least one
element from among C, Mg, Fe, Be, Zn, V, and Sb as the impurity
element by at least 1.times.10.sup.17 cm.sup.-3 to the group III
nitride semiconductor layer in epitaxially growing the group III
nitride semiconductor layer on the underlying substrate, the GaN
substrate attaining the resistivity controlled to at least
1.times.10.sup.4 .OMEGA.cm (preferably, 1.times.10.sup.7
.OMEGA.cm), the average dislocation density not higher than
1.times.10.sup.7 cm.sup.-2, the surface density of the
dislocation-concentrated region where dislocation density exceeds
1.times.10.sup.8 cm.sup.-2 of at most 1 cm.sup.-2, the half-width
of the rocking curve in X-ray diffraction in a range from at least
10 arcsec to at most 500 arcsec, and the carrier density not higher
than 1.times.10.sup.15 cm.sup.-3 was obtained.
EXAMPLE 8
[0078] The low-resistivity GaN substrate was obtained in a manner
the same as in Example 1, except for employing the high-resistivity
GaN substrate (the main surface of the substrate matches with
(0001) surface (angle of 0.degree.)) manufactured in Example 1 as
underlying substrate 1, employing an oxygen (O.sub.2) gas as the
impurity element raw material, and setting the partial pressure of
the impurity element raw material to 0.001 kPa (1.times.10.sup.-5
atmospheric pressure).
[0079] The minimum concentration of impurity element O in the
obtained GaN substrate was 1.times.10.sup.18 cm.sup.-3, the
in-plane distribution of the concentration of O (maximum
concentration/minimum concentration) was 1.5, the resistivity was
0.01 .OMEGA.cm, the average dislocation density was
1.times.10.sup.6 cm.sup.-2, the surface density of the
dislocation-concentrated region was not higher than 1 cm.sup.-2,
the half-width of the rocking curve in X-ray diffraction was 60
arcsec, the carrier density was 1.times.10.sup.18 cm.sup.-3, and
the absorption coefficient for light of a wavelength of 450 nm was
not larger than 5 cm.sup.-1. Table 2 summarizes the result.
EXAMPLE 9
[0080] The low-resistivity GaN substrate was obtained in a manner
the same as in Example 8, except for employing a tetrachlorosilane
(SiCl.sub.4) gas as the impurity element raw material. The minimum
concentration of impurity element Si in the obtained GaN substrate
was 1.times.10.sup.18 cm.sup.-3, the in-plane distribution of the
concentration of Si (maximum concentration/minimum concentration)
was 2.5, the resistivity was 0.01 .OMEGA.cm, the average
dislocation density was 1.times.10.sup.6 cm.sup.-2, the surface
density of the dislocation-concentrated region was not higher than
1 cm.sup.-2, the half-width of the rocking curve in X-ray
diffraction was 60 arcsec, the carrier density was
1.times.10.sup.18 cm.sup.-3, and the absorption coefficient for
light of a wavelength of 450 nm was not larger than 5 cm.sup.-1.
Table 2 summarizes the result.
EXAMPLE 10
[0081] The low-resistivity GaN substrate was obtained in a manner
the same as in Example 8, except for employing a hydrogen sulfide
(H.sub.2S) gas as the impurity element raw material. The minimum
concentration of impurity element S in the obtained GaN substrate
was 1.times.10.sup.18 cm.sup.-3, the in-plane distribution of the
concentration of S (maximum concentration/minimum concentration)
was 2.0, the resistivity was 0.02 .OMEGA.cm, the average
dislocation density was 1.times.10.sup.7 cm.sup.-2, the surface
density of the dislocation-concentrated region was not higher than
1 cm.sup.-2, the half-width of the rocking curve in X-ray
diffraction was 60 arcsec, the carrier density was
7.times.10.sup.17 cm.sup.-3, and the absorption coefficient for
light of a wavelength of 450 nm was not larger than 10 cm.sup.-1.
Table 2 summarizes the result. TABLE-US-00002 TABLE 2 Example 8
Example 9 Example 10 Underlying Composition GaN GaN GaN substrate
Angle of main surface 0.degree. from 0.degree. from 0.degree. from
(0001) (0001) (0001) surface surface surface Presence/absence of
mask layer absent absent absent Doping material O.sub.2 SiCl.sub.4
H.sub.2S Group III Impurity Type O Si S nitride element Minimum
concentration 1 .times. 10.sup.18 1 .times. 10.sup.18 1 .times.
10.sup.18 semiconductor (cm.sup.-3) substrate In-plane distribution
1.5 2.5 2.0 (maximum concentration/ minimum concentration)
Resistivity (.OMEGA. cm) 0.01 0.01 0.02 Average dislocation density
(cm.sup.-2) 1 .times. 10.sup.6 1 .times. 10.sup.6 1 .times.
10.sup.7 Surface density of 1 or lower 1 or lower 1 or lower
dislocation-concentrated region (cm.sup.-2) Half-width of rocking
curve 60 60 60 (arcsec) Carrier density (cm.sup.-3) 1 .times.
10.sup.18 1 .times. 10.sup.18 7 .times. 10.sup.17 Absorption
coefficient for light 5 or smaller 5 or smaller 10 or (cm.sup.-1)
smaller
[0082] As can clearly be seen from Table 2, by adding at least one
element from among O, Si, S, Ge, Se, and Te as the impurity element
by at least 1.times.10.sup.17 cm.sup.-3 to the group III nitride
semiconductor layer in epitaxially growing the group III nitride
semiconductor layer on the underlying substrate, the-GaN substrate
attaining the resistivity controlled to at most 1 .OMEGA.cm, the
average dislocation density not higher than 1.times.10.sup.7
cm.sup.-2, the surface density of the dislocation-concentrated
region where dislocation density exceeds 1.times.10.sup.8 cm.sup.-2
of at most 1 cm.sup.-2, the half-width of the rocking curve in
X-ray diffraction in a range from at least 10 arcsec to at most 500
arcsec, and the carrier density in a range from at least
1.times.10.sup.17 cm.sup.-3 to at most 1.times.10.sup.20 cm.sup.-3
was obtained.
[0083] Although the present invention has been described and
illustrated in detail, it is clearly understood that the same is by
way of illustration and example only and is not to be taken by way
of limitation, the spirit and scope of the present invention being
limited only by the terms of the appended claims.
* * * * *