U.S. patent application number 11/155208 was filed with the patent office on 2006-12-21 for breakable interconnects and structures formed thereby.
Invention is credited to Henning Braunisch, Daoqiang Lu.
Application Number | 20060286721 11/155208 |
Document ID | / |
Family ID | 37573906 |
Filed Date | 2006-12-21 |
United States Patent
Application |
20060286721 |
Kind Code |
A1 |
Lu; Daoqiang ; et
al. |
December 21, 2006 |
Breakable interconnects and structures formed thereby
Abstract
Methods of forming a microelectronic structure are described.
Embodiments of those methods include placing an anisotropic
conductive layer comprising at least one compliant conductive
sphere on at least one interconnect structure disposed on a first
substrate, applying pressure to contact the compliant conductive
spheres to the at least one interconnect structure, removing a
portion of the anisotropic conductive layer to expose at least one
of the compliant conductive spheres; and then attaching a second
substrate to the anisotropic conductive layer.
Inventors: |
Lu; Daoqiang; (Chnadler,
AZ) ; Braunisch; Henning; (Chandler, AZ) |
Correspondence
Address: |
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
12400 WILSHIRE BOULEVARD
SEVENTH FLOOR
LOS ANGELES
CA
90025-1030
US
|
Family ID: |
37573906 |
Appl. No.: |
11/155208 |
Filed: |
June 16, 2005 |
Current U.S.
Class: |
438/119 ;
257/E21.514; 257/E23.067; 257/E23.171 |
Current CPC
Class: |
H01L 23/49827 20130101;
H01L 2924/01013 20130101; H01L 2924/01078 20130101; H01L 2924/0665
20130101; H01L 2924/014 20130101; H01L 24/28 20130101; H01L
2224/838 20130101; H01L 2924/14 20130101; H05K 2201/0233 20130101;
H01L 24/83 20130101; H01L 2224/2919 20130101; H01L 2924/00
20130101; H01L 2924/00 20130101; H01L 2924/0665 20130101; H01L
2924/01079 20130101; H01L 23/5382 20130101; H01L 2924/01047
20130101; H05K 2201/0221 20130101; H01L 21/485 20130101; H05K
2201/0314 20130101; H05K 3/365 20130101; H05K 3/323 20130101; H01L
2224/2919 20130101; H01L 2924/01029 20130101; H01L 2924/0665
20130101; H01L 2924/0781 20130101 |
Class at
Publication: |
438/119 |
International
Class: |
H01L 21/50 20060101
H01L021/50; H01L 21/48 20060101 H01L021/48; H01L 21/44 20060101
H01L021/44; H01G 7/00 20060101 H01G007/00 |
Claims
1. A method comprising; placing an anisotropic conductive layer
comprising at least one compliant conductive sphere on at least one
interconnect structure disposed on a first substrate; applying
pressure to contact the at least one compliant conductive sphere to
the at least one interconnect structure; removing a portion of the
anisotropic conductive layer to expose at least one of the
compliant conductive spheres; and attaching a second substrate to
the anisotropic conductive layer.
2. The method of claim 1 wherein applying pressure to contact the
at least one compliant conductive sphere to the at least one
interconnect structure further comprises applying heat to melt the
anisotropic conductive layer.
3. The method of claim 2 further comprising solidifying the
anisotropic conductive layer by at least one of thermal cooling and
curing.
4. The method of claim 1 wherein the at least one compliant
conductive sphere comprises a coating selected from the group
consisting of nickel, gold, platinum and paladium and combinations
thereof.
5. The method of claim 1 wherein the at least one compliant
conductive sphere comprises a matrix comprising at least one of
epoxy, silicone, polyurethane and combinations thereof.
6. The method of claim 1 wherein the anisotropic conductive layer
comprises the at least one compliant conductive sphere dispersed
within a polymeric matrix.
7. The method of claim 6 wherein the polymeric matrix comprises at
least one of polyurethane, polystyrene copolymer, and polyolefins,
silicone, polyurethane, epoxy silicone and combinations
thereof.
8. The method of claim 1 wherein attaching a second substrate to
the anisotropic conductive layer comprises contacting at least one
interconnect structure disposed on the second substrate to at least
one of the exposed compliant conductive spheres.
9. The method of claim 1 further comprising attaching a clamp
structure on the first substrate and the second substrate that is
capable of applying pressure to clamp the first substrate and the
second substrate together.
10. The method of claim 9 wherein the clamp structure is capable of
providing a breakable interconnection between the first substrate
and the second substrate.
11. The method of claim 1 wherein at least one of the first
substrate and the second substrate comprises a flexible
circuit.
12. A structure comprising: an anisotropic conductive layer
comprising at least one compliant conductive sphere disposed
between a first substrate and a second substrate, wherein the at
least one compliant conductive sphere contacts a first interconnect
structure disposed on the first substrate and a second interconnect
structure disposed on the second substrate; and a clamp structure
disposed on the first substrate and the second substrate that is
capable of applying pressure to clamp the first substrate and the
second substrate together.
13. The structure of claim 12 wherein the at least one compliant
conductive sphere comprises a coating selected from the group
consisting of nickel, gold, platinum and paladium and combinations
thereof.
14. The structure of claim 12 wherein the at least one compliant
conductive sphere comprises a matrix comprising at least one of
epoxy, silicone, polyurethane and combinations thereof.
15. The structure of claim 12 wherein the anisotropic conductive
layer comprises the at least one compliant conductive sphere
dispersed within a polymeric matrix.
16. The structure of claim 15 wherein the polymeric matrix
comprises at least one of polyurethane, polystyrene copolymer, and
polyolefins, silicone, polyurethane, epoxy silicone and
combinations thereof.
17. The structure of claim 12 wherein the clamp structure is
capable of providing a breakable interconnection between the first
substrate and the second substrate.
18. The structure of claim 12 wherein at least one of the first
substrate and the second substrate comprises a flexible
circuit.
19. The structure of claim 12 wherein the at least one compliant
conductive sphere comprises a diameter between about 10 to about
300 microns.
20. A system comprising: a breakable interconnect structure
comprising: an anisotropic conductive layer, wherein the
anisotropic conductive layer comprises at least one compliant
conductive sphere disposed between a first substrate and a second
substrate, and wherein the at least one compliant conductive sphere
contacts a first interconnect structure disposed on the first
substrate and a second interconnect structure disposed on the
second substrate; a clamp structure disposed on the first substrate
and the second substrate that is capable of applying pressure to
clamp the first substrate and the second substrate together; a
computing device communicatively coupled to the breakable
interconnect structure; and a DRAM communicatively coupled to the
computing device.
21. The system of claim 20 wherein the anisotropic conductive layer
comprises the at least one compliant conductive sphere dispersed
within a polymeric matrix.
22. The system of claim 20 wherein the clamp structure is capable
of providing a breakable interconnection between the first
substrate and the second substrate.
23. The system of claim 20 wherein at least one of the first
substrate and the second substrate comprises a flexible circuit.
Description
BACKGROUND OF THE INVENTION
[0001] System performance may be improved by increasing the quality
of I/O (input/output) signals transmitted between an integrated
circuit die and associated receivers and/or between die on adjacent
substrates. In some instances, such I/O interconnects may require
breakable connections at various locations between the die and
substrates, for example. Conductive films may be used to provide
such breakable connections.
BRIEF DESCRIPTION OF THE DRAWINGS
[0002] While the specification concludes with claims particularly
pointing out and distinctly claiming certain embodiments of the
present invention, the advantages of this invention can be more
readily ascertained from the following description of the invention
when read in conjunction with the accompanying drawings in
which:
[0003] FIGS. 1a-1h represent methods of forming structures
according to an embodiment of the present invention.
[0004] FIG. 2 represents a system according to another embodiment
of the present invention.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
[0005] In the following detailed description, reference is made to
the accompanying drawings that show, by way of illustration,
specific embodiments in which the invention may be practiced. These
embodiments are described in sufficient detail to enable those
skilled in the art to practice the invention. It is to be
understood that the various embodiments of the invention, although
different, are not necessarily mutually exclusive. For example, a
particular feature, structure, or characteristic described herein,
in connection with one embodiment, may be implemented within other
embodiments without departing from the spirit and scope of the
invention. In addition, it is to be understood that the location or
arrangement of individual elements within each disclosed embodiment
may be modified without departing from the spirit and scope of the
invention. The following detailed description is, therefore, not to
be taken in a limiting sense, and the scope of the present
invention is defined only by the appended claims, appropriately
interpreted, along with the full range of equivalents to which the
claims are entitled. In the drawings, like numerals refer to the
same or similar functionality throughout the several views.
[0006] Methods and associated structures of forming and utilizing a
microelectronic structure, such as a breakable interconnect
structure, are described. Those methods may comprise placing an
anisotropic conductive layer comprising at least one compliant
conductive sphere on at least one interconnect structure disposed
on a first substrate, applying pressure to contact the at least one
compliant conductive sphere to the at least one interconnect
structure, removing a portion of the anisotropic conductive layer
to expose at least one of the compliant conductive spheres; and
then attaching a second substrate to the anisotropic conductive
layer.
[0007] FIGS. 1a-1h illustrate an embodiment of a method of forming
a microelectronic structure, such as a breakable interconnect
structure, for example. FIG. 1a illustrates a first substrate 100.
In one embodiment, the first substrate 100 may comprise at least
one of a power delivery substrate, an interposer, a motherboard, a
package, a flexible circuit, and may be any portion of a
microelectronic device that may be coupled and/or contacted to
another portion of a microelectronic device, for example.
[0008] The substrate 100 may comprise at least one interconnect
structure 102, that may serve to electrically connect the first
substrate 100 to other structures within a microelectronic device,
for example. The at least one interconnect structure 102 may
comprise any conductive material, such as but not limited to
copper, aluminum, gold, silver and/or nickel and combinations
thereof, and in some embodiments may comprise a metal pad or solder
balls, for example.
[0009] In one embodiment, an anisotropic conductive layer 104 may
be formed and/or placed on the first substrate 100 utilizing any
well known method of placement and/or formation, such as but not
limited to laminating the anisotropic conductive layer 104 onto the
substrate 100, for example (FIG. 1b). In one embodiment, the
anisotropic conductive layer 104 may comprise any layer that may
conduct in the thickness direction of the layer (perpendicular to
the substrate 100 in this embodiment), as is well known in the
art.
[0010] In one embodiment, the anisotropic conductive layer 104 may
comprise a polymer matrix 110 and at least one compliant conductive
sphere 107. In one embodiment, the polymer matrix 110 may comprise
at least one of polyurethane, polystyrene copolymer, polyolefins,
silicone, polyurethane, epoxy silicone and combinations thereof. In
one embodiment, the polymer matrix 110 may comprise monomers and/or
a thermoplastic polymer, as are well known in the art.
[0011] In one embodiment, the at least one compliant conductive
sphere 107 may comprise a matrix 106 and a coating 108. In one
embodiment, the matrix 106 may comprise at least one of epoxy,
silicone, polyurethane and combinations thereof. In some
embodiments the matrix 106 may provide the at least one compliant
conductive sphere 107 with flexibility and compliance. In one
embodiment, the coating 108 may comprise a conductive material,
such as but not limited to nickel, gold, platinum and paladium and
combinations thereof. In one embodiment, the at least one compliant
conductive sphere 107 may comprise a diameter 109 of between about
10 to about 300 microns.
[0012] In one embodiment, the anisotropic conductive layer 104 may
be compressed between two interconnect structures, and may be
trapped and make intimate contact between both of the interconnect
structures, and thus the two interconnect structures may become
electrically connected through the conductive spheres 107 of the
anisotropic conductive layer 104. However, due to the low volume
loading of the compliant conductive spheres 107, the compliant
conductive spheres 107 will rarely if ever contact each other and
thus may not provide significant electrical connection
laterally.
[0013] A chuck 112 that in some embodiments may be pre-heated and
comprise a non-sticking surface, may be pressed down by applying
sufficient pressure 114 onto the anisotropic conductive layer 104
(FIG. 1c). The amount of pressure 114 and heat applied will depend
upon the particular application, but the pressure 114 applied may
be sufficient enough to cause the at least one compliant conductive
sphere 107 to make contact with the at least one interconnect
structure 102 of the first substrate 100. In one embodiment, the at
least one conductive sphere 107 may be electrically coupled to the
at least one interconnect structure 102.
[0014] In one embodiment, the amount of heat applied to the
anisotropic conductive layer 104 may be sufficient to substantially
soften and/or melt the anisotropic conductive layer 104. In one
embodiment, the anisotropic conductive layer 104 may soften and/or
melt such that the anisotropic conductive layer 104 may fill in a
region 113 between the anisotropic conductive layer 104 and the
first substrate 100 that may be separated by a height 115 of the at
least one interconnect structure 102 (refer back to FIG. 1b).
[0015] In one embodiment, when the anisotropic conductive layer 104
may comprise monomers, the anisotropic conductive layer 104 may be
solidified by thermal curing. In one embodiment, the anisotropic
conductive layer 104 may be thermally cured by utilizing the heat
that may be supplied by the chuck 112. In one embodiment, when the
anisotropic conductive layer 104 may comprise a thermoplastic
polymer, the anisotropic conductive layer 104 may be solidified by
cooling. In one embodiment, the anisotropic conductive layer 104
may be bonded to the first substrate 100 by cooling and/or thermal
curing. In one embodiment, the anisotropic conductive layer 104 may
maintain compliance and flexibility due to the compliant nature of
the polymeric matrix 110 as well as the compliant nature of the
matrix 106 of the at least one compliant conductive sphere 107.
[0016] Once the anisotropic conductive layer 104 has solidified the
chuck 112 may be released (FIG. 1d). In one embodiment, a portion
of the anisotropic conductive layer 104 may be removed to expose a
portion of the at least one compliant conductive spheres 107 (FIG.
1e). In one embodiment, a portion of the polymer matrix 110 of the
anisotropic conductive layer 104 may be removed by utilizing a
plasma etch process 116 (FIG. 1d), as is well known in the art. In
one embodiment, the coating 108 of at least one of the compliant
conductive spheres 107 may be exposed (FIG. 1e).
[0017] In one embodiment, a second substrate 118 may be attached
and disposed on the anisotropic conductive layer 104, such that at
least one interconnect structure 120 that may be disposed on the
second substrate 118 may be coupled with and/or disposed on an
exposed one of the at least one compliant conductive sphere 107
(FIG. 1f). In one embodiment, the second substrate 118 may comprise
at least one of a power delivery substrate, an interposer, a
motherboard, a package, a flexible circuit, and may be any portion
of a microelectronic device that may be coupled and/or contacted to
another portion of a microelectronic device, for example. In one
embodiment, the at least one interconnect structure 120 may
comprise any conductive material, and in some embodiments may
comprise a metal pad or solder balls, for example.
[0018] In one embodiment, the first substrate 100 and the second
substrate 118 may be clamped together by the utilization of a
clamping structure 122 (FIG. 1g). By mechanically clamping the
first and the second substrates 100, 118 together, the first and
the second substrates 100, 118 may be electrically connected and/or
coupled together through the at least one compliant conductive
sphere 107. In this manner, a breakable interconnect structure 124
may be formed, wherein the interconnection and/or coupling between
the first and the second substrates 100, 118 may be broken
depending upon the particular application requirements. In one
embodiment, the interconnection between the first and the second
substrates 100, 118 may be broken by removing the clamping
structure 122. Clamping structure 122 may be part of a socket or a
connector retention structure, as are well known in the art.
[0019] Due to the compliance of the at least one compliant
conductive sphere 107 and the polymer matrix 110, reliable contact
between the first and the second substrates 100, 118 may be made,
wherein the breakable interconnect structure 124 may exhibit small
to negligible electrical parasitic characteristics. The breakable
interconnect structure 124 may also exhibit a small profile height
128 that may greatly enhance performance while operating at high
speeds, for example. Additionally, the breakable interconnect
structure 124 may be manufactured in a high volume environment, and
may be extremely economical since the anisotropic conductive layer
104 may be commercially available at a relatively low cost.
[0020] In another embodiment, the second substrate 118 of the
breakable interconnect structure 124 may comprise a flexible
input/output signal routing substrate (FIG. 1h), such as a high
speed flexible circuit as is well known in the art. In one
embodiment, the flexible substrate may include a support structure
126, such as a stiffener, for example, that may provide mechanical
support for the flexible circuit, and may in some embodiments
enhance the reliability of the connection between the first and the
second substrates 100, 118.
[0021] FIG. 2 is a diagram illustrating an exemplary system 232
capable of being operated with methods for fabricating a
microelectronic structure, such as the breakable interconnect
structure 124 of FIG. 1g for example. It will be understood that
the present embodiment is but one of many possible systems in which
the breakable interconnect structures of the present invention may
be used.
[0022] In the system 232 a breakable interconnect structure 230 may
be communicatively coupled to a computing device 238, such as a
processor, and a cache memory 240 may be communicatively coupled to
the breakable interconnect structure 230 through a processor bus
242, for example. The processor bus 242 and an I/O bus 236 may be
bridged by a host bridge 244. Communicatively coupled to the I/O
bus 236 and also to the breakable interconnect structure 230 may be
a main memory 246. Examples of the main memory 246 may include, but
are not limited to, static random access memory (SRAM) and/or
dynamic random access memory (DRAM), and/or some other state
preserving media. The system 232 may also include a graphics
coprocessor 248, however incorporation of the graphics coprocessor
248 into the system 232 is not necessary to the operation of the
system 232. Coupled to the I/O bus 236 may also, for example, be a
display device 250, a mass storage device 252, and keyboard and
pointing devices 254.
[0023] Alternatively, the breakable interconnect structure 230 may
be communicatively coupled (not shown) to a printed circuit board
(PCB) 234 by way of the I/O bus 236. The communicative coupling of
the breakable interconnect structure 230 may be established by
physical means, such as through the use of a package and/or a
socket connection to mount the breakable interconnect structure 230
to the PCB 234 (for example by the use of a chip package,
interposer and/or a land grid array socket). The breakable
interconnect structure 230 may also be communicatively coupled to
the PCB 234 through various wireless means (for example, without
the use of a physical connection to the PCB), as are well known in
the art.
[0024] These elements perform their conventional functions well
known in the art. In particular, mass storage 252 may be used to
provide long-term storage for executable instructions for a method
for forming breakable interconnect structures in accordance with
embodiments of the present invention, whereas main memory 246 may
be used to store on a shorter term basis the executable
instructions of a method for forming breakable interconnect
structures in accordance with embodiments of the present invention
during execution by computing device 238. In addition, the
instructions may be stored, or otherwise associated with, machine
accessible media communicatively coupled with the system, such as
compact disk read only memories (CD-ROMs), digital versatile disks
(DVDs), and floppy disks, carrier waves, and/or other propagated
signals, for example. In one embodiment, main memory 246 may supply
the computing device 238 (which may be a processor, for example)
with the executable instructions for execution.
[0025] Although the foregoing description has specified certain
steps and materials that may be used in the method of the present
invention, those skilled in the art will appreciate that many
modifications and substitutions may be made. Accordingly, it is
intended that all such modifications, alterations, substitutions
and additions be considered to fall within the spirit and scope of
the invention as defined by the appended claims. In addition, it is
appreciated that various microelectronic structures are well known
in the art. Therefore, the Figures provided herein illustrate only
portions of an exemplary microelectronic structure that pertains to
the practice of the present invention. Thus the present invention
is not limited to the structures described herein.
* * * * *