U.S. patent application number 11/147944 was filed with the patent office on 2006-12-14 for fast magnetic memory devices utilizing spin transfer and magnetic elements used therein.
Invention is credited to Zhitao Diao, Yiming Huai, Mahendra Pakala, Zhenghong Qian.
Application Number | 20060279981 11/147944 |
Document ID | / |
Family ID | 37499111 |
Filed Date | 2006-12-14 |
United States Patent
Application |
20060279981 |
Kind Code |
A1 |
Diao; Zhitao ; et
al. |
December 14, 2006 |
Fast magnetic memory devices utilizing spin transfer and magnetic
elements used therein
Abstract
A method and system for providing a magnetic memory is
described. The method and system include providing a plurality of
magnetic storage cells, a plurality of word lines, and a plurality
of bit lines. Each of the plurality of magnetic storage cells
includes a plurality of magnetic elements and at least one
selection transistor. Each of the plurality of magnetic elements is
capable of being programmed using spin transfer induced switching
by a write current driven through the magnetic element. Each of the
plurality of magnetic elements has a first end and a second end.
The at least one selection transistor is coupled to the first end
of each of the plurality of magnetic elements. The plurality of
word lines is coupled with the plurality of selection transistors
and selectively enables a portion of the plurality of selection
transistors.
Inventors: |
Diao; Zhitao; (Fremont,
CA) ; Huai; Yiming; (Pleasanton, CA) ; Pakala;
Mahendra; (Fremont, CA) ; Qian; Zhenghong;
(Fremont, CA) |
Correspondence
Address: |
SAWYER LAW GROUP LLP
P O BOX 51418
PALO ALTO
CA
94303
US
|
Family ID: |
37499111 |
Appl. No.: |
11/147944 |
Filed: |
June 8, 2005 |
Current U.S.
Class: |
365/158 |
Current CPC
Class: |
G11C 11/16 20130101 |
Class at
Publication: |
365/158 |
International
Class: |
G11C 11/00 20060101
G11C011/00 |
Claims
1. A magnetic memory comprising: a plurality of magnetic storage
cells, each of the plurality of magnetic storage cells including a
plurality of magnetic elements capable of being programmed using
spin transfer induced switching by a write current driven through
the magnetic element, each of the plurality of magnetic elements
having a first end and a second end, and at least one selection
transistor coupled to the first end of each of the plurality of
magnetic elements; and a plurality of word lines coupled with the
plurality of selection transistors and for selectively enabling a
portion of the plurality of selection transistors; and a plurality
of bit lines.
2. The magnetic memory of claim 1 wherein the plurality of magnetic
elements include a first magnetic element and a second magnetic
element and wherein the at least one selection transistor includes
a single selection transistor.
3. The magnetic memory of claim 2 further comprising: a plurality
of bit line selection transistors coupled with the plurality of bit
lines, for selectively enabling a portion of the plurality of bit
lines; and a plurality of data lines for each of the plurality of
magnetic storage cells, a first data line of the plurality of data
lines coupled with the second end of the first magnetic element and
a second data line of the plurality of data lines coupled with the
second end of the second magnetic element, the plurality of data
lines for providing a write current during writing and a sense
current during reading of the plurality of magnetic storage
cells.
4. The magnetic memory of claim 3 wherein the plurality of magnetic
storage cells are organized into pairs including a first magnetic
storage cell and a second magnetic storage cell, wherein the
selection transistor of the first magnetic storage cell and the
selection transistor of the second magnetic storage cell share a
drain.
5. The magnetic memory of claim 3 wherein the plurality of bit
lines include a plurality of subsidiary bit lines, each of the
subsidiary bit lines coupled with a portion of the plurality of
magnetic elements, the plurality of bit line selection transistors
corresponding to the plurality of subsidiary bit lines.
6. The magnetic memory of claim 5 wherein the plurality of data
lines include a plurality of subsidiary data lines, the plurality
of subsidiary data lines including the first data line and the
second data line for a portion of the plurality of magnetic storage
cells.
7. The magnetic memory of claim 3 wherein the first data line is
coupled to ground.
8. The magnetic memory of claim 7 wherein the plurality of bit
lines are coupled to a plurality of differential sense
amplifiers.
9. The magnetic memory of claim 7 wherein each of the plurality of
bit lines are coupled to each of a plurality of differential sense
amplifiers.
10. The magnetic memory of claim 3 wherein the plurality of bit
lines are coupled with at least one current converting circuit.
11. The magnetic element of claim 3 wherein the first data line is
a separate data line for each of the plurality of magnetic storage
cells and wherein the second data line is a common data line for a
portion of the plurality of magnetic storage cells.
12. The magnetic memory of claim 2 wherein the first magnetic
element includes a first storage layer having a first magnetization
and the second magnetic element includes a second storage layer
having a second storage layer, the first magnetization aligned
substantially antiparallel with the second magnetization.
13. The magnetic memory of claim 2 wherein the first magnetic
element has a first magnetoresistance and the second magnetic
element has a second magnetoresistance, the first magnetoresistance
and the second magnetoresistance being substantially equal in
magnitude.
14. The magnetic memory of claim 2 wherein the first magnetic
element has a first resistance and the second magnetic element has
a second resistance, the first resistance and the second resistance
being different.
15. The magnetic memory of claim 1 wherein a first magnetic element
of the plurality of magnetic elements is disposed substantially
directly above a second magnetic element of the plurality of
magnetic elements.
16. The magnetic memory of claim 15 wherein each of the first
magnetic element and the second magnetic element includes a
tunneling magnetoresistive junction.
17. The magnetic memory of claim 16 wherein the tunneling
magnetoresistive junctions includes a pinned layer, a tunneling
barrier layer, and a free layer, the tunneling barrier layer
residing between the pinned layer and the free layer.
18. The magnetic memory of claim 17 wherein the pinned layer is a
synthetic pinned layer including a first magnetic layer, a second
magnetic layer, and a nonmagnetic layer between the first magnetic
layer and the second magnetic layer.
19. The magnetic memory of claim 17 wherein the pinned layer of the
first magnetoresistive storage element resides above the free layer
of the first magnetoresistive storage element and wherein the
pinned layer of the second magnetoresistive storage element resides
below the free layer of the second magnetoresistive storage
element.
20. The magnetic memory of claim 15 wherein the first
magnetoresistive storage element and the second magnetoresistive
storage element each include a separate cell plate and are
separated by an insulating layer.
21. The magnetic memory of claim 15 wherein the first
magnetoresistive storage element and the second magnetoresistive
storage element each share a cell plate.
22. The magnetic memory of claim 1 wherein the plurality of
magnetic elements include a plurality of dual tunneling
magnetoresistive junctions.
23. The magnetic memory of claim 22 wherein each of the plurality
of dual tunneling magnetoresistive junctions includes a synthetic
pinned layer including a first magnetic layer, a second magnetic
layer, and a nonmagnetic spacer layer between the first magnetic
layer and the second magnetic layer.
24. The magnetic memory of claim 1 wherein each of the plurality of
magnetic elements includes a first pinned layer, a tunneling
barrier layer, a free layer, a nonmagnetic spacer layer, and a
second pinned layer, the tunneling barrier layer residing between
the free layer and the first pinned layer, the nonmagnetic spacer
layer residing between the second pinned layer and the free
layer.
25. The magnetic memory of claim 24 wherein the first pinned layer
is a synthetic pinned layer including a first magnetic layer, a
second magnetic layer, and a nonmagnetic layer between the first
magnetic layer and the second magnetic layer.
26. The magnetic memory of claim 1 wherein each of the plurality of
magnetic elements include a plurality of tunneling magnetoresistive
junctions, each of the plurality of tunneling magnetoresistive
junctions being separated by a nonmagnetic layer.
27. The magnetic memory of claim 1 wherein each of the plurality of
magnetic elements include at least one tunneling magnetoresistive
junction and at least one spin valve, each of the at least one
tunneling magnetoresistive junction and the at least one spin valve
being separated by a nonmagnetic spacer layer.
28. The magnetic memory of claim 1 wherein each of the plurality of
magnetic elements includes a free layer, the free layer including
at least one of Co, Fe, and Ni.
29. The magnetic memory of claim 28 wherein the free layer includes
at least one amorphous forming element.
30. The magnetic memory of claim 29 wherein the at least one
amorphous forming element has a concentration of not more than
thirty atomic percent.
31. The magnetic memory of claim 29 wherein the amorphous forming
element includes boron.
32. The magnetic memory of claim 29 wherein the free layer has a
saturation magnetization of between four hundred and one thousand
five hundred emu/cm.sup.3.
33. The magnetic memory of claim 28 wherein the free layer is a
single layer including a ferromagnetic material or a ferrimagnetic
material.
34. The magnetic memory of claim 33 wherein the ferromagnetic
material includes at least one of Co, CoFe with 5-40 atomic percent
Fe, CoFeB with 5-40 atomic percent Fe and 5-30 atomic percent B,
CoFeTa with 5-40 atomic percent Fe and 5-30 atomic percent Ta, NiFe
with approximately 20 atomic percent Fe, CoPt with 5-40 atomic
percent Pt, CoPd with 5-40 atomic percent Pd, FePt with 5-40 atomic
percent Pt, Co.sub.2MnAl, Co.sub.2MnSi, or Co.sub.2CrAl,
Co.sub.2CrSi, Co.sub.2FeAl and Co.sub.2FeSi.
35. The magnetic memory of claim 33 wherein the ferrimagnetic
material includes at least one of CoGd with 15-30 atomic percent Gd
and FeGd with 10-40 atomic percent Gd.
36. The magnetic memory of claim 28 wherein the free layer is a
multilayer including a plurality of layers.
37. The magnetic memory of claim 36 wherein the plurality of layers
include a plurality of ferromagnetic layers.
38. The magnetic memory of claim 37 wherein the plurality of
ferromagnetic layers includes at least one of Co, CoFe with 5-40
atomic percent Fe, CoFeB with 5-40 atomic percent Fe and 5-30
atomic percent B, CoFeTa with 5-40 atomic percent Fe and 5-30atomic
percent Ta, NiFe with approximately 20 atomic percent Fe, CoPt with
5-40 atomic percent Pt, CoPd with 5-40 atomic percent Pd, FePt with
5-40 atomic percent Pt, Co.sub.2MnAl, Co.sub.2MnSi, or
Co.sub.2CrAl, Co.sub.2CrSi, Co.sub.2FeAl and Co.sub.2FeSi.
39. The magnetic memory of claim 37 wherein the plurality of layers
include at least one nonmagnetic layer separating a portion of the
plurality of ferromagnetic layers.
40. The magnetic memory of claim 39 wherein the ferromagnetic
material includes at least one of Co, CoFe with 5-40 atomic percent
Fe, CoFeB with 5-40 atomic percent Fe and 5-30 atomic percent B,
CoFeTa with 5-40 atomic percent Fe and 5-30 atomic percent Ta, NiFe
with approximately 20 atomic percent Fe, CoPt with 5-40 atomic
percent Pt, CoPd with 5-40 atomic percent Pd, FePt with 5-40 atomic
percent Pt, Co.sub.2MnAl, Co.sub.2MnSi, or Co.sub.2CrAl,
Co.sub.2CrSi, Co.sub.2FeAl and Co.sub.2FeSi.
41. The magnetic memory of claim 39 wherein the nonmagnetic layer
includes at least one of Ru, Rh, Re, Cr and Cu.
42. The magnetic memory of claim 28 wherein each of the plurality
of magnetic elements includes a pinned layer including at least one
of Co, Fi, and Ni.
43. The magnetic memory of claim 42 wherein the pinned layer is a
single layer including a ferromagnetic material or a ferrimagnetic
material.
44. The magnetic memory of claim 43 wherein the ferromagnetic
material includes at least one of Co, CoFe with 5-40 atomic percent
Fe, CoFeB with 5-40 atomic percent Fe and 5-30 atomic percent B,
CoFeTa with 5-40 atomic percent Fe and 5-30 atomic percent Ta, NiFe
with approximately 20 atomic percent Fe, CoPt with 5-40 atomic
percent Pt, CoPd with 5-40 atomic percent Pd, FePt with 5-40 atomic
percent Pt, Co.sub.2MnAl, Co.sub.2MnSi, or Co.sub.2CrAl,
Co.sub.2CrSi, Co.sub.2FeAl and Co.sub.2FeSi.
45. The magnetic memory of claim 43 wherein the ferrimagnetic
material includes at least one of CoGd with 15-30 atomic percent Gd
and FeGd with 10-40 atomic percent Gd.
46. The magnetic memory of claim 42 wherein the pinned layer is a
multilayer including a plurality of layers.
47. The magnetic memory of claim 46 wherein the plurality of layers
include a plurality of ferromagnetic layers.
48. The magnetic memory of claim 47 wherein the plurality of
ferromagnetic layers includes at least one of Co, CoFe with 5-40
atomic percent Fe, CoFeB with 5-40 atomic percent Fe and 5-30
atomic percent B, CoFeTa with 5-40 atomic percent Fe and 5-30atomic
percent Ta, NiFe with approximately 20 atomic percent Fe, CoPt with
5-40atomic percent Pt, CoPd with 5-40 atomic percent Pd, FePt with
5-40 atomic percent Pt, Co.sub.2MnAl, Co.sub.2MnSi, or
Co.sub.2CrAl, Co.sub.2CrSi, Co.sub.2FeAl and Co.sub.2FeSi.
49. The magnetic memory of claim 47 wherein the plurality of layers
include at least one nonmagnetic layer separating a portion of the
plurality of ferromagnetic layers.
50. The magnetic memory of claim 49 wherein the ferromagnetic
material includes at least one of Co, CoFe with 5-40 atomic percent
Fe, CoFeB with 5-40 atomic percent Fe and 5-30 atomic percent B,
CoFeTa with 5-40 atomic percent Fe and 5-30 atomic percent Ta, NiFe
with approximately 20 atomic percent Fe, CoPt with 5-40 atomic
percent Pt, CoPd with 5-40 atomic percent Pd, FePt with 5-40 atomic
percent Pt, Co.sub.2MnAl, Co.sub.2MnSi, or Co.sub.2CrAl,
Co.sub.2CrSi, Co.sub.2FeAl and Co.sub.2FeSi.
51. The magnetic memory of claim 49 wherein the nonmagnetic layer
includes at least one of Ru, Re, and Cu.
52. The magnetic memory of claim 42 wherein each of the plurality
of magnetic elements includes at least one tunneling barrier
layer.
53. The magnetic memory of claim 52 wherein the at least one
tunneling barrier layer includes at least one of AlO with 40-70
atomic percent O, MgO with 30-60 atomic percent O, and AlN with
40-70 atomic percent O and 2-30 atomic percent N, AlN with 30-60
atomic percent N, AlZrO, AlHfO, AlTiO, and AlTaO.
54. The magnetic memory of claim 52 wherein the at least one
tunneling barrier layer includes a plurality of layers.
55. The magnetic memory of claim 52 wherein the at least one
tunneling barrier layer has a thickness of at least five Angstroms
and not more than forty Angstroms.
56. The magnetic memory of claim 52 wherein the at least one
tunneling barrier layer has a resistance-area product between ten
and one hundred .OMEGA.-.mu.m.sup.2.
57. The magnetic memory of claim 42 wherein each of the plurality
of magnetic elements includes at least one nonmagnetic spacer
layer.
58. The magnetic memory of claim 57 wherein the at least one
nonmagnetic spacer layer includes at least one of Cu, Ag, Pt, Al,
Ru, Re, Rh, Ta, and Ti.
59. The magnetic memory of claim 57 wherein the at least one
nonmagnetic spacer layer includes at least one nano-oxide
layer.
60. A method for providing a magnetic memory comprising: providing
a plurality of magnetic storage cells, each of the plurality of
magnetic storage cells including a plurality of magnetic elements
capable of being programmed using spin transfer induced switching
by a write current driven through the magnetic element, each of the
plurality of magnetic elements having a first end and a second end,
and at least one selection transistor coupled to the first end of
each of the plurality of magnetic elements; and providing a
plurality of word lines coupled with the plurality of selection
transistors and for selectively enabling a portion of the plurality
of selection transistors; and providing a plurality of bit
lines.
61. The method of claim 60 wherein providing plurality of magnetic
elements includes: providing a first magnetic element and a second
magnetic element and wherein the at least one selection transistor
includes a single selection transistor.
62. The method of claim 61 further comprising: providing a
plurality of bit line selection transistors coupled with the
plurality of bit lines, for selectively enabling a portion of the
plurality of bit lines; and providing a plurality of data lines for
each of the plurality of magnetic storage cells, a first data line
of the plurality of data lines coupled with the second end of the
first magnetic element and a second data line of the plurality of
data lines coupled with the second end of the second magnetic
element, the plurality of data lines for providing a write current
during writing and a sense current during reading of the plurality
of magnetic storage cells.
63. The method of claim 62 wherein providing the plurality of
magnetic storage cells includes: organizing the plurality of
magnetic storage cells into pairs including a first magnetic
storage cell and a second magnetic storage cell, the selection
transistor of the first magnetic storage cell and the selection
transistor of the second magnetic storage cell sharing a drain.
64. The method of claim 62 wherein providing the plurality of bit
lines includes: providing a plurality of subsidiary bit lines, each
of the subsidiary bit lines coupled with a portion of the plurality
of magnetic elements, the plurality of bit line selection
transistors corresponding to the plurality of subsidiary bit
lines.
65. The method of claim 62 wherein providing the plurality of data
lines further includes: providing a plurality of subsidiary data
lines, the plurality of subsidiary data lines including the first
data line and the second data line for a portion of the plurality
of magnetic storage cells.
66. The method of claim 2 wherein providing plurality of data lines
includes: coupling the first data line to ground.
67. The method of claim 66 wherein providing the plurality of bit
lines further includes: coupling the plurality of bit lines to a
plurality of differential sense amplifiers.
68. The method of claim 66 wherein each of the plurality of bit
lines are coupled to each of a plurality of differential sense
amplifiers.
69. The method of claim 62 further comprising: coupling the
plurality of bit lines with at least one current converting
circuit.
70. The method element of claim 62 wherein the first data line is a
separate data line for each of the plurality of magnetic storage
cells and wherein the second data line is a common data line for a
portion of the plurality of magnetic storage cells.
71. The method of claim 61 wherein providing the plurality of
magnetic storage cells further includes: providing the first
magnetic element including a first storage layer having a first
magnetization; and providing the second magnetic element including
a second storage layer having a second storage layer, the first
magnetization aligned substantially antiparallel with the second
magnetization.
72. The method of claim 61 wherein the first magnetic element has a
first magnetoresistance and the second magnetic element has a
second magnetoresistance, the first magnetoresistance and the
second magnetoresistance being substantially equal in
magnitude.
73. The method of claim 61 wherein the first magnetic element has a
first resistance and the second magnetic element has a second
resistance, the first resistance and the second resistance being
different.
74. The method of claim 60 wherein providing the plurality of
magnetic storage cells includes: providing a first magnetic element
of the plurality of magnetic elements is disposed substantially
directly above a second magnetic element of the plurality of
magnetic elements.
75. The method of claim 74 wherein each of the first magnetic
element and the second magnetic element includes a tunneling
magnetoresistive junctions.
76. The method of claim 75 wherein the tunneling magnetoresistive
junctions includes a pinned layer, a tunneling barrier layer, and a
free layer, the tunneling barrier layer residing between the pinned
layer and the free layer.
77. The method of claim 76 wherein the pinned layer is a synthetic
pinned layer including a first magnetic layer, a second magnetic
layer, and a nonmagnetic layer between the first magnetic layer and
the second magnetic layer.
78. The method of claim 77 wherein the pinned layer of the first
magnetoresistive storage element resides above the free layer of
the first magnetoresistive storage element and wherein the pinned
layer of the second magnetoresistive storage element resides below
the free layer of the second magnetoresistive storage element.
79. The method of claim 74 wherein the first magnetoresistive
storage element and the second magnetoresistive storage element
each include a separate cell plate and are separated by an
insulating layer.
80. The method of claim 74 wherein the first magnetoresistive
storage element and the second magnetoresistive storage element
each share a cell plate.
81. The method of claim 60 wherein providing the plurality of
magnetic elements includes: providing a plurality of dual tunneling
magnetoresistive junctions.
82. The method of claim 60 wherein providing the plurality of
magnetic elements includes: providing a first pinned layer, a
tunneling barrier layer, a free layer, a nonmagnetic spacer layer,
and a second pinned layer for each of the plurality of magnetic
elements, the tunneling barrier layer residing between the free
layer and the first pinned layer, the nonmagnetic spacer layer
residing between the second pinned layer and the free layer.
83. The method of claim 60 wherein providing the plurality of
magnetic elements includes: providing a plurality of tunneling
magnetoresistive junctions for each or the plurality of magnetic
storage cells, each of the plurality of tunneling magnetoresistive
junctions being separated by a nonmagnetic layer.
84. The method of claim 60 wherein each of the plurality of
magnetic elements include at least one tunneling magnetoresistive
junction and at least one spin valve, each of the at least one
tunneling magnetoresistive junction and the at least one spin valve
being separated by a nonmagnetic spacer layer.
85. A method for utilizing a magnetic memory, the magnetic memory
including a plurality of magnetic storage cells, the method
comprising: driving a write current through a portion of the
plurality of magnetic storage cells, each of the plurality of
magnetic storage cells including a plurality of magnetic elements
capable of being programmed using spin transfer induced switching
by a write current driven through the magnetic element, each of the
plurality of magnetic elements having a first end and a second end,
and at least one selection transistor coupled to the first end of
each of the plurality of magnetic elements; and reading at least
one of the plurality of magnetic storage cells by driving a read
current through the plurality of magnetic elements and determining
a differential signal based upon the read signal or comparing the
read signal to a reference signal.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to magnetic memory systems,
and more particularly to a method and system for providing memory
cells and accompanying circuitry for use in a magnetic memory
having cells that can be switched using a spin transfer effect.
BACKGROUND OF THE INVENTION
[0002] FIG. 1 depicts a portion of a conventional magnetic random
access memory (MRAM) 10. The conventional MRAM 10 includes
conventional magnetic storage cells 20, conventional word lines
30-1 through 30-n, conventional word selection lines 40 and 42,
conventional data lines 50 and 52, conventional word selection
transistors 54 and 56, conventional data selection line 60,
conventional data selection transistor 62, and conventional sense
amplifier 70. The conventional magnetic storage cells 20 each
include a single conventional selection transistor 22 and a single
conventional magnetic element 24. The conventional magnetic element
24 may be a conventional spin valve or a conventional tunneling
magnetoresistive (TMR) junction. The word selection line 42 carries
a signal that is the inverse of the signal carried by the word
selection line 40. Similarly, the data line 50 carries a signal
that is the inverse of a signal carried on the data line 52. The
conventional MRAM 10 is programmed using the spin-transfer
effect.
[0003] The spin-transfer effect arises from the spin-dependent
electron transport properties of ferromagnetic-normal metal
multilayers. When a spin-polarized current traverses a magnetic
multiplayer, such as the conventional magnetic element 24, in a CPP
configuration, the spin angular momentum of electrons incident on a
ferromagnetic layer interacts with magnetic moments of the
ferromagnetic layer near the interface between the ferromagnetic
and normal-metal layers. Through this interaction, the electrons
transfer a portion of their angular momentum to the ferromagnetic
layer. As a result, a spin-polarized current can switch the
magnetization direction of the ferromagnetic layer if the current
density is sufficiently high (approximately 10.sup.6-10.sup.8
A/cm.sup.2).
[0004] The phenomenon of spin transfer can be used in the CPP
configuration as an alternative to or in addition to using an
external switching field to switch the direction of magnetization
of the free layer of a magnetic element, such as a the conventional
spin valve or TMR junction 24.
[0005] To program the conventional magnetic element 24 to a first
state, such as a logical "1", current is driven through the
conventional magnetic element 24 in a first direction. To program
the conventional magnetic element 24 to a second state, such as a
logical "0", current is driven through the conventional magnetic
element 24 in the opposite direction. For example, in order to
program the conventional magnetic element 24, the conventional
selection transistor 22 is activated by activating the conventional
word line 30-1. In addition, word selection transistors 54 and 56
are activated by providing the appropriate voltages on the word
selection lines 40 and 42, respectively. The conventional data
selection transistor 62 is disabled by providing the appropriate
voltage on the data selection line 60. Depending upon the voltage
biasing the data lines 50 and 52, current flows through the
conventional magnetic element 24 in the first direction or the
second direction. Consequently, the state of the conventional
magnetic element 24 is switched to a logical "1" or a logical "0",
respectively.
[0006] To read the conventional magnetic element 24, the
conventional selection transistor 22 and the conventional data
selection transistor 62 are activated using the lines 30-1 and 60,
respectively. In addition, one of the word selection transistors 56
is activated using the word selection line 42, while the remaining
word selection transistor 54 is disabled using the word selection
line 40. A sense current can thus be driven through the
conventional magnetic element 24 to the sense amplifier 70.
Depending upon the magnitude of the output voltage, it can be
determined by comparing the sense current with to a reference
current whether a logical "0" or a logical "1" is stored in the
conventional magnetic element 24 and thus the conventional magnetic
storage cell 20.
[0007] Although magnetic elements utilizing spin transfer as a
programming mechanism can be used in principle, one of ordinary
skill in the art will readily recognize that there may be
drawbacks. In particular, noise from the transistors 22, 54, 56,
and 62, from the data lines 50 and 52, and the remaining peripheral
circuitry may reduce the signal-to-noise ratio. Consequently, it
may be difficult to accurately read the conventional MRAM 10,
particularly at higher device densities.
[0008] Accordingly, what is needed is a magnetic memory having
improved performance and utilizing a localized phenomenon for
writing, such as spin transfer, and accompanying circuitry for
reading with enhanced signal-to-noise ratio and fast speed. The
present invention addresses such a need.
BRIEF SUMMARY OF THE INVENTION
[0009] The present invention provides a method and system for
providing a magnetic memory. The method and system comprise
providing a plurality of magnetic storage cells, a plurality of
word lines, and a plurality of bit lines. Each of the plurality of
magnetic storage cells includes a plurality of magnetic elements
and at least one selection transistor. Each of the plurality of
magnetic elements is capable of being programmed using spin
transfer induced switching by a write current driven through the
magnetic element. Each of the plurality of magnetic elements has a
first end and a second end. The at least one selection transistor
is coupled to the first end of each of the plurality of magnetic
elements. The plurality of word lines is coupled with the plurality
of selection transistors and selectively enables a portion of the
plurality of selection transistors.
[0010] According to the method and system disclosed herein, the
present invention provides a mechanism for programming and reading
a magnetic memory including magnetic elements that are programmable
by a write current driven through the magnetic elements, for
example through the phenomenon of spin transfer.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
[0011] FIG. 1 is a diagram of a conventional magnetic random access
memory.
[0012] FIG. 2 is a diagram of a portion of one embodiment of a
magnetic storage cell in accordance with the present invention.
[0013] FIG. 3 is a diagram of a portion of one embodiment of a
magnetic memory in accordance with the present invention.
[0014] FIG. 4 is a diagram of a portion of another embodiment of a
magnetic memory in accordance with the present invention.
[0015] FIG. 5 is a diagram of a portion of another embodiment of a
magnetic memory in accordance with the present invention.
[0016] FIG. 6 is a diagram of a portion of another embodiment of a
magnetic memory in accordance with the present invention.
[0017] FIG. 7 is a diagram of a portion of another embodiment of a
magnetic memory in accordance with the present invention.
[0018] FIG. 8 is a diagram of a portion of another embodiment of a
magnetic memory in accordance with the present invention.
[0019] FIG. 9 is a diagram of a portion of one embodiment of a
magnetic storage cell in accordance with the present invention.
[0020] FIG. 10 is a cross-sectional view of a portion of one
embodiment of a magnetic storage cell in accordance with the
present invention.
[0021] FIG. 11 is a cross-sectional view of a portion of one
embodiment of a magnetic storage cell in accordance with the
present invention.
[0022] FIG. 12 is a cross-sectional view of a portion of another
embodiment of a magnetic storage cell in accordance with the
present invention.
[0023] FIG. 13 is a cross-sectional view of a portion of another
embodiment of a magnetic storage cell in accordance with the
present invention.
[0024] FIG. 14 is a more detailed cross-sectional view of a portion
of one embodiment of a magnetic storage cell in accordance with the
present invention.
[0025] FIG. 15 is a cross-sectional view of a portion of another
embodiment of a magnetic element in accordance with the present
invention.
[0026] FIG. 16 is a cross-sectional view of a portion of another
embodiment of a magnetic element in accordance with the present
invention.
[0027] FIG. 17 is a flow chart depicting on embodiment of a method
in accordance with the present invention for providing a magnetic
memory.
[0028] FIG. 18 is a flow chart depicting on embodiment of a method
in accordance with the present invention for utilizing a magnetic
memory.
DETAILED DESCRIPTION OF THE INVENTION
[0029] The present invention relates to a magnetic memory. The
following description is presented to enable one of ordinary skill
in the art to make and use the invention and is provided in the
context of a patent application and its requirements. Various
modifications to the preferred embodiments and the generic
principles and features described herein will be readily apparent
to those skilled in the art. Thus, the present invention is not
intended to be limited to the embodiments shown, but is to be
accorded the widest scope consistent with the principles and
features described herein.
[0030] The present invention provides a method and system for
providing a magnetic memory. The method and system comprise
providing a plurality of magnetic storage cells, a plurality of
word lines, and a plurality of bit lines. Each of the plurality of
magnetic storage cells includes a plurality of magnetic elements
and at least one selection transistor. Each of the plurality of
magnetic elements is capable of being programmed using spin
transfer induced switching by a write current driven through the
magnetic element. Each of the plurality of magnetic elements has a
first end and a second end. The at least one selection transistor
is coupled to the first end of each of the plurality of magnetic
elements. The plurality of word lines is coupled with the plurality
of selection transistors and selectively enables a portion of the
plurality of selection transistors.
[0031] The present invention is described in the context of
particular magnetic memories having certain components. One of
ordinary skill in the art will readily recognize that the present
invention is consistent with the use of magnetic memories having
other and/or additional components. Furthermore, the present
invention is described in the context of components corresponding
to certain portions of the memory. For example, subsidiary lines
are described as corresponding to a certain number of magnetic
storage cells. However, one of ordinary skill in the art will
readily recognize that the components could correspond to another
number of elements, for example subsidiary lines corresponding to
another number of magnetic storage cells. The method and system in
accordance with the present invention are also described in the
context of reading from or writing to a single magnetic storage
cell. However, one of ordinary skill in the art will readily
recognize that the method and system can be extended to read from
and/or write to multiple magnetic storage cells substantially in
parallel. The present invention is described in the context of
certain memories. However, one of ordinary skill in the art will
readily recognize that the present invention is compatible with
memories not inconsistent with the present invention.
[0032] The present invention is also described in the context of
current understanding of the spin transfer phenomenon.
Consequently, one of ordinary skill in the art will readily
recognize that theoretical explanations of the behavior of the
method and system are made based upon this current understanding of
spin transfer. One of ordinary skill in the art will also readily
recognize that the method and system are described in the context
of a structure having a particular relationship to the substrate.
For example, as depicted in the drawings, the bottoms of the
structures are typically closer to an underlying substrate than the
tops of the structures. However, one of ordinary skill in the art
will readily recognize that the method and system are consistent
with other structures having different relationships to the
substrate. In addition, the method and system are described in the
context of certain layers being synthetic and/or simple. However,
one of ordinary skill in the art will readily recognize that the
layers could have another structure. Furthermore, the present
invention is described in the context of magnetic elements having
particular layers. However, one of ordinary skill in the art will
readily recognize that magnetic elements having additional and/or
different layers not inconsistent with the present invention could
also be used. Moreover, certain components are described as being
ferromagnetic. However, as used herein, the term ferromagnetic
could include ferrimagnetic or like structures. Thus, as used
herein, the term "ferromagnetic" includes, but is not limited to
ferromagnets and ferrimagnets.
[0033] FIG. 2 is a diagram of a portion of one embodiment of a
magnetic storage cell 100 in accordance with the present invention.
The magnetic storage cell 100 includes magnetic elements 102 and
104 as well as selection transistor 106 that is shared by the
magnetic elements 102 and 104. The selection transistor 106 is
enabled in order to select the magnetic storage cell 100. The
magnetic elements 102 and 104 are programmed by driving a write
current through the magnetic elements 102 and 104. Thus, the
magnetic elements 102 and 104 are programmed using spin transfer.
The magnetic elements 102 and 104 provide a signal via
magnetoresistance. In a preferred embodiment, the magnitudes of the
magnetoresistances of the magnetic elements 102 and 104 are
substantially equal. In addition, the data storage layer
(preferably at least one free layer) of the magnetic elements 102
and 104 preferably have their magnetizations aligned antiparallel.
In one embodiment, the magnetic elements 102 and 104 may be TMR
junctions, dual TMR junctions, or other magnetic element, such as
those described below, which can be programmed using spin transfer
and which provide a read signal using magnetoresistance. The
selection transistor 106 is preferably a CMOS transistor.
[0034] As discussed above, the magnetizations of the data storage
layers for the magnetic elements 102 and 104 are aligned
antiparallel. Suppose that the magnetic elements 102 and 104 have
at least one data storage layer (e.g. free layer) and at least one
reference (e.g. pinned) layer. Based on the writing operation, the
magnetization of the recording layer of the magnetic element 102 is
directed parallel to that of the reference (pinned) layer. In
addition, the magnetization of the data storage layer (e.g. free
layer) of the magnetic element 104 is directed anti-parallel to
that of the reference layer (e.g. pinned layer) in a direction of
the switching current. This magnetization configuration represents
a logical "1". If the switching current is driven in the opposite
direction, the magnetizations of the storage layers of the magnetic
elements 102 and 104 are reversed. Consequently, the magnetization
of the data storage layer of the TMR element 102 is directed
anti-parallel to that of the reference (pinned) layer, while the
magnetization of the recording layer of the magnetic element 104 is
directed parallel to that of the reference layer. This
configuration represents a logical "0".
[0035] During reading, a potential difference is applied between
the ends of each of the magnetic elements 102 and 104. The output
is a differential signal. The magnitude of the difference in the
currents flowing through the lines coupled to the ends of the
magnetic elements 102 and 104 is indicative of the data stored in
the magnetic storage cell 100. In a preferred embodiment, the
resistances of the magnetic elements 102 and 104 are R(1-MR/2) and
R(1+MR/2), respectively, for a logical "1" described above. Thus,
although the resistances differ, the magnetoresistances are
preferably the same. Currents I.sub.102 and I.sub.104 flowing
through magnetic elements 102 and 104, respectively, for a
particular bias voltage, V.sub.bias. Thus, I.sub.102 is
V.sub.bias/[R(1-MR/2)] while I.sub.104 is V.sub.bias[R(1+MR/2)] for
a logical "1". Thus, I.sub.102 is larger than I.sub.104 for a
logical "1". Similarly, when a logical "0" is stored, I.sub.102 is
smaller than I.sub.104. In a preferred embodiment, where the
magnetoresistances of the magnetic elements 102 and 104 are the
same, the difference in the currents I.sub.102 and I.sub.104 is
V.sub.bias/R.times.MR. Thus, the magnetic storage cell may provide
a larger signal than for a conventional magnetic memory. In
addition, because the magnetic elements 102 and 104 share one
selection transistor 106, the noise from the fluctuation in the
characteristics of the transistor 106 can be reduced or eliminated.
Consequently, performance may be improved.
[0036] FIG. 3 is a diagram of a portion of one embodiment of a
magnetic memory 110 in accordance with the present invention. The
magnetic memory 110 utilizes magnetic storage cells 100. The
magnetic memory 110 includes word lines 112-1 through 112-n, bit
line 114, bit select line 116, bit select transistor 118, data line
120, data line 122 that carries a signal that is the inverse of the
signal carried on the data line 120, word select line 124, word
select transistors 126 and 128, data select line 130, data select
transistors 132 and 134, sense amplifier 136, and bit line segments
138-1 through 138-n. The bit line segments 138-1 through 138-n
couple the storage cells 100 to the bit line 114. The word select
line 124 is used to enable word select transistors 126 and 128. The
data select line 130 is used to enable data select transistors 132
and 134. One end of each of the magnetic elements 102 and 104 is
connected to the selection transistor 106. The other end of the
magnetic elements 102 and 104 are coupled to the data lines 120 and
122, respectively. Bias voltage clamping circuits (not shown) are
coupled with the data lines 120 and 122 for programming operations
and to the bit line 114 for read operations. The transistors 118,
126, 128, 132, and 134 may be CMOS transistors. In the magnetic
memory 110, the magnetic storage cells 100 operate analogously to
the magnetic storage cell 100 depicted in FIG. 2. In a preferred
embodiment, the resistances are different and the
magnetoresistances are the same for both magnetic elements 102 and
104.
[0037] In operation, the magnetic memory 110 is programmed by
driving a write current through the magnetic elements 102 and 104
to switch the magnetization of the data storage layer using the
spin transfer effect. To program a cell, such as the cell coupled
with the word line 112-1, the cell is activated by activating the
selection transistor 106 using the word line 112-1. In addition,
the bit select transistor 118 and word select transistors 126 and
128 are activated using the bit selection line 116 and the word
select line 124, respectively. The data select transistors 132 and
134 are also disabled using the data select line 130. Data can be
programmed to the magnetic elements 102 and 104 by flowing a
current through the magnetic elements 102 and 104 in the
appropriate direction by setting a high voltage (e.g. V.sub.DD) to
data lines 120 and 122 and a low voltage (e.g. 0) to bit line 114
or vice versa.
[0038] As discussed above, the magnetizations of the data storage
layers for the magnetic elements 102 and 104 are aligned
antiparallel. During the programming operation when the current is
driven in a first direction, the magnetization of the data storage
layers of the magnetic elements 102 and 104 are preferably aligned
parallel and antiparallel, respectively to that of their reference
layers. This configuration represents a logical "1". If the
switching current is reversed and the magnetizations of both of the
storage layers of the magnetic elements 102 and 104 are reversed,
the configuration for a logical "0" is achieved.
[0039] The magnetic storage cell 100 is read by activating the
selection transistor 106 using the word line 112-1. In addition,
data selection transistors 132 and 134 and bit selection transistor
118 are activated using lines 130 and 116, respectively. The word
selection transistors 126 and 128 are turned off. In addition, a
bias voltage is applied between the data lines 120 and 122 and the
bit line 114. As discussed above, if the current through the data
line 120 is larger than the current through the data line 122, then
a logical "1" is stored in the magnetic storage cell 100.
Similarly, if the current through the data line 120 is smaller than
the current through the data line 122, then a logical "0" is stored
in the magnetic storage cell 100. As discussed above, the current
difference for the magnetic elements 102 and 104 having the same
magnetoresistance is V.sub.bias/R.times.MR, where V.sub.bias is the
bias voltage, R(1-MR/2) and R(1+MR/2) are the resistances of the
magnetic elements 102 and 104, and MR is the magnetoresistance of
the magnetic elements 102 and 104.
[0040] Thus, the magnetic memory 110 provides a larger signal,
which is desirable when reading a memory. Because both magnetic
elements 102 and 104 share a single selection transistor 106, all
the noise from the fluctuation in the characteristics of additional
selection transistors (not present) can be reduced or eliminated.
Furthermore, the time delay due to the stray capacitance of the
data line 120 or 122 is preferably on the order of less than one
nano-second. Consequently, the speed of the magnetic memory 110 is
improved. Note, however, that remaining, unselected cells in a
column may act as a shunt between the data lines 120 and 122. In
such a case, the difference in currents and, therefore, the signal,
may be decreased, significantly depending on the wiring resistance
of the data lines. For example, in some embodiments, it is expected
that a few thousand magnetic storage cells 100 may be coupled in a
cell block without unduly affecting performance.
[0041] FIG. 4 is a diagram of a portion of another embodiment of a
magnetic memory 140 in accordance with the present invention. The
magnetic memory 140 utilizes magnetic storage cells 100. The
magnetic memory 140 includes word lines 142-1 through 142-n, bit
line 144, bit select line 146, bit select transistor 148, data line
150, data line 152 that carries a signal that is the inverse of the
signal carried on the data line 150, word select line 154, word
select transistors 156 and 158, data select line 160, data select
transistors 162 and 164, sense amplifier 166, and bit line segments
168-1,2 through 168-n-l,n. The bit line segments 168-1,2 through
168-n-l,n couple the storage cells 100 to the bit line 144. The
word select line 154 is used to enable word select transistors 156
and 158. The data select line 160 is used to enable data select
transistors 162 and 164. One end of each of the magnetic elements
102 and 104 is connected to the selection transistor 106. The other
end of the magnetic elements 102 and 104 are coupled to the data
lines 150 and 152, respectively. Bias voltage clamping circuits
(not shown) are coupled with the data lines 150 and 152 for
programming operations and to the bit line 144 for read operations.
The transistors 148, 156, 158, 162, and 164 may be CMOS
transistors.
[0042] The magnetic memory 140 is analogous to the magnetic memory
110 depicted in FIG. 3. The magnetic memory 140 of FIG. 4 also
operates in an analogous manner to the magnetic memory 110 depicted
in FIG. 3. In the magnetic memory 140, the magnetic storage cells
100 operate analogously to the magnetic storage cell 100 depicted
in FIG. 2. In a preferred embodiment, the resistances differ and
magnetoresistances are the same for both magnetic elements 102 and
104. Consequently, the magnetic memory 140 shares many of the
advantages of the magnetic memory 110. In addition, in the magnetic
memory 140, the magnetic storage cells 100 are grouped into pairs.
A pair of magnetic storage cells 100 is grouped such that the
selection transistors 106 in a pair share a drain as well as a
segment 168-i,j connecting the magnetic storage cells 100 to the
bit line 144. Thus, for example, the segment 168-1,2 is coupled to
the drains of the selection transistors 106 of the first two
magnetic storage cells. The number of segments 168-i,j is,
therefore, n/2. Consequently, the number of segments 168-i,j
coupling the magnetic storage cells to the bit line 144 is reduced
by half. As a result, the density of the magnetic memory 140 can be
significantly increased.
[0043] FIG. 5 is a diagram of a portion of another embodiment of a
magnetic memory 170 in accordance with the present invention. The
magnetic memory 170 utilizes magnetic storage cells 100. The
magnetic memory 170 includes word lines 172-1 through 172-n, bit
line 174, subsidiary bit select line 176, subsidiary bit select
transistor 178, data line 180, data line 182 that carries a signal
that is the inverse of the signal carried on the data line 180,
subsidiary data line 181, subsidiary data line 183 that carries a
signal that is the inverse of the signal carried on the subsidiary
data line 181, word select line 184, word select transistors 186
and 188, data select line 190, data select transistors 192 and 194,
sense amplifier 196, and bit line segments 198-1 through 198-n. The
bit line segments 198-1 through 198-n couple the storage cells 100
to the bit line 174. The word select line 184 is used to enable
word select transistors 186 and 188. The data select line 190 is
used to enable data select transistors 192 and 194. One end of each
of the magnetic elements 102 and 104 is connected to the selection
transistor 106. The other end of the magnetic elements 102 and 104
are coupled to the data lines 180 and 182, respectively. Bias
voltage clamping circuits (not shown) are coupled with the data
lines 180 and 182 for programming operations and to the bit line
174 for read operations. The transistors 178, 186, 188, 192, and
194 may be CMOS transistors. In the magnetic memory 170, the
magnetic storage cells 100 operate analogously to the magnetic
storage cell 100 depicted in FIG. 2. In a preferred embodiment, the
resistances differ, while the magnetoresistances are the same for
both magnetic elements 102 and 104.
[0044] The magnetic memory 170 is analogous to the magnetic memory
110 depicted in FIG. 3. The magnetic memory 170 of FIG. 5 also
operates in an analogous manner to the magnetic memory 110 depicted
in FIG. 3. Consequently, the magnetic memory 170 shares many of the
advantages of the magnetic memory 110. In addition, subsidiary bit
line 176 and subsidiary data lines 181 and 183 are used. The
subsidiary data lines 181 and 183 are connected to data lines 180
and 182 via selection transistors 186 and 188, respectively.
Similarly, the subsidiary bit selection line 176 is coupled to the
bit line 174 through a selection transistor 176. The ends of the
magnetic elements 102 and 104 are coupled to the subsidiary data
lines 181 and 183 instead of data lines. The magnetic elements 102
and 104 are still connected to the selection transistor 106 at the
other end. The subsidiary data lines 181 and 183 are utilized to
form a subsidiary array having a reduced number of magnetic storage
cells 100 without greatly increasing the total area occupied by the
magnetic memory 100. Through the use of the subsidiary array, the
subsidiary data lines 181 and 183, and the subsidiary bit line 176,
as well as the resulting decrease in the number of magnetic storage
cells 100 in the subsidiary array, the decrease in output signal
due to an increased number of memory cells may be avoided.
[0045] FIG. 6 is a diagram of a portion of another embodiment of a
magnetic memory 200 in accordance with the present invention. The
magnetic memory 200 utilizes magnetic storage cells 100. The
magnetic memory 200 includes word lines 202-1 through 202-n, bit
lines 204-1 through 204-n, data line 210, data line 212 that
carries a signal that is the inverse of the signal carried on the
data line 210, word select line 214, word select transistors 216
and 218, data select line 220, data select line 224 that carries a
signal that is the inverse of the signal carried on the data select
line 220, data select transistors 222 and 226, sense amplifiers
228-1 through 228-n, and additional data line 229 that carries a
signal that is the inverse of the signal carried on the data select
line 220. The word select line 214 is used to enable word select
transistors 216 or 218. The data select lines 220 and 224 are used
to enable data select transistors 222 and 226, respectively. One
end of each of the magnetic elements 102 and 104 is connected to
the selection transistor 106. The other end of the magnetic
elements 102 and 104 are coupled to the data lines 210 and 212,
respectively. Bias voltage clamping circuits (not shown) are
coupled with the data lines 210 and 212 for programming operations.
The transistors 216, 218, 222, and 226 may be CMOS transistors.
[0046] The magnetic memory 200 is analogous to the magnetic memory
110 depicted in FIG. 3. For programming, the magnetic memory 200 of
FIG. 6 also operates in an analogous manner to the magnetic memory
110 depicted in FIG. 3. Consequently, the magnetic memory 200
shares many of the advantages of the magnetic memory 110. In
addition, in the magnetic memory 200, the data line 210 is
grounded. Individual bit lines 204-1 through 204-n are individually
coupled with separate differential sense amplifiers 228-1 through
228-n. For reading, the selection transistor 106 is enabled using
the word line 202-1. In addition, the data selection transistors
222 and 226 are enabled using data selection lines 220 and 224,
respectively. Moreover, the word selection transistors 216 and 218
are disabled. A bias voltage is applied to the magnetic storage
cell 100 through the data line 229.
[0047] In the magnetic memory 200, the magnetic storage cells 200
operate analogously to the magnetic storage cell 100 depicted in
FIG. 2. In a preferred embodiment, the resistances are different,
while the magnetoresistances are the same for both magnetic
elements 102 and 104. Referring back to FIG. 6, for a logical "1"
stored in the magnetic storage cell 100, the resistance is
R(1-MR/2) for the magnetic element 102 and R(1+MR/2) for the
magnetic element 104. Consequently, the voltage induced on the bit
line 204-1 is V.sub.bias/2.times.(1-MR/2). For such an embodiment,
the voltage induced to the bit line 204-1 is
V.sub.bias/2.times.(1+MR/2) for a logical "0". In one embodiment, a
reference voltage is set to V.sub.REF=V.sub.bias/2. In such an
embodiment, the logical "0" and the logical "1" can be
differentiated by comparing the signal voltage with the reference
voltage. Thus, in addition to the benefits provided by the magnetic
memory 110, the output signal is not dependent upon the current
through the magnetic elements 102 and 104. The output signal thus
does not depend on a current that would be changed due to the
number of the cells in a cell array. Consequently, the reduction in
magnetoresistance ratio depending on the bias voltage can be
mitigated. Moreover fluctuations in the characteristics of the
selection transistor 106 may not adversely affect performance of
the magnetic memory 200.
[0048] FIG. 7 is a diagram of a portion of another embodiment of a
magnetic memory 240 in accordance with the present invention. The
magnetic memory 240 utilizes magnetic storage cells 100. The
magnetic memory 240 includes word lines 242-1 through 242-n, bit
lines 244-1 through 244-n, current converting circuit 245, bit
select lines 246-1 through 246-n (note that for simplicity only
246-1 and 246-2 are depicted), bit select transistors 248-1 through
248-n (not that for simplicity only 248-1 and 248-2 are shown),
data line 250, data line 252 that carries a signal that is the
inverse of the signal carried on the data line 250, word select
line 254, word select transistors 256 and 258, data select line
260, data select line 264 that carries a signal that is the inverse
of the signal carried on the data select line 260, data select
transistors 262 and 266, additional data line 268 that carries a
signal that is the inverse of the signal carried on the data select
line 250, sense amplifiers 270, and current converting circuit 245.
The current converting circuit 245 includes a resistor 273
transistors 272 and 274, and capacitor 276. The word select line
254 is used to enable word select transistors 256 and 258. The data
select lines 260 and 264 are used to enable data select transistors
262 and 266, respectively. One end of each of the magnetic elements
102 and 104 is connected to the selection transistor 106. The other
end of the magnetic elements 102 and 104 are coupled to the data
line 250 and data lines 252 and 268, respectively. Bias voltage
clamping circuits (not shown) are coupled with the data lines 250
and 252 for programming operations and data line 268 for reading.
The transistors 248-1 through 248-n, 256, 258, 262, 266, 272, and
274 may be CMOS transistors. In a preferred embodiment, the
resistances are different and magnetoresistance are the same for
both magnetic elements 102 and 104.
[0049] The magnetic memory 240 is analogous to the magnetic memory
110 depicted in FIG. 3 as well as the magnetic memory 200 depicted
in FIG. 6. For programming, the magnetic memory 240 of FIG. 7 also
operates in an analogous manner to the magnetic memory 110 depicted
in FIG. 3. For reading, the magnetic memory 240 operates
analogously to the magnetic memory 200 depicted in FIG. 6.
Referring back to FIG. 7, the magnetic memory 240 thus shares many
of the advantages of the magnetic memories 110 and 200. In
addition, the bit lines 244-1 through 244-n are coupled to at least
one current converting circuit 245. A fluctuation of the voltage in
the read operation is converted to a current difference in the
current converting circuit 245 and provided to an amplifier 270 via
the bit line 244-1 through 244-n for the corresponding magnetic
storage cell 100. In addition, the delay due to the bit lines 244-1
through 244-n can be reduced by shortening the bit lines 244-1
through 244-n. As a result, the floating capacity and wiring
resistance are reduced. Consequently, the speed of the magnetic
memory 240 may be improved.
[0050] FIG. 8 is a diagram of a portion of another embodiment of a
magnetic memory 280 in accordance with the present invention. The
magnetic memory 280 utilizes magnetic storage cells 100. The
magnetic memory 280 includes word lines 282-1 through 282-n, bit
line 284, bit select line 286, bit select transistors 288, data
lines 290-1 through 290-n, data line 292 that carries a signal that
is the inverse of the signal carried on the data line 290-1 through
290-n, additional data line 292, data select line 296, and
transistors 294, 298, 300, and 302, etc., which are enabled using
the data select line 296. One end of each of the magnetic elements
102 and 104 is connected to the selection transistor 106. The other
end of the magnetic elements 102 and 104 are coupled to the data
lines 290-1 through 290-n, 292, respectively. Bias voltage clamping
circuits (not shown) are coupled with the data lines 290-1 through
290-n and 292 for programming operations and data line 284 for
reading. The transistors, such as transistors 288, 294, 298, 300,
and 302, may be CMOS transistors. In a preferred embodiment, the
resistances differ, while magnetoresistances are the same for both
magnetic elements 102 and 104.
[0051] The magnetic memory 280 is analogous to the magnetic memory
110 depicted in FIG. 3. Referring back to FIG. 7, the magnetic
memory 280 thus shares many of the advantages of the magnetic
memories 110 and 200. In addition, in the magnetic memory 280, one
end of the magnetic element 102 is connected to separate data line
290-1 through 290-n. The other end of the magnetic element 104 to
the common data line 292. All the data lines 290-1 through 290-n
are connected to corresponding selection transistors such as
selection transistors 298, 300, and 302, that are activated only
during programming of the corresponding. Similarly, the common data
line 292 is connected to the selection transistor 294 that is only
activated during writing information operation. One extra
transistor, such as transistors 298, 300, and 302,for each storage
cell 100 is used for separating the memory cells from each other at
expense of device density. During readout of information, the data
lines 290-1 through 290-n and 292 are not short-circuited by
unselected cells. Thus operation with stability and high power
consumption efficiency can be expected.
[0052] FIGS. 9-16 depict various embodiments of magnetic storage
cells 100 that may be used in the magnetic memories 110, 140, 170,
200, 240, and 280. However, other magnetic storage cells and more
particularly other magnetic elements might be used.
[0053] FIGS. 9-11 are a diagram of a portion of one embodiment of a
magnetic storage cell 100' in accordance with the present
invention. FIG. 9 depicts a plan view of the magnetic storage cell
100'FIG. 10 is a cross-sectional view taken along line A-A' of a
portion of one embodiment of a magnetic storage 100 cell in
accordance with the present invention. FIG. 11 is a cross-sectional
view taken along line B-B' of a portion of one embodiment of a
magnetic storage cell in accordance with the present invention. The
magnetic elements 102' and 104' as well as the selection transistor
106' are depicted. In particular, the source 322, drain 318 and
gate 320 of the selection transistor 106' as well as the
ferromagnetic layers 310 and 312 of the magnetic element 102' and
the ferromagnetic layers 314 and 316 of the magnetic element 104'
are shown. In addition, cell plates 313 and 317 for the magnetic
elements 102' and 104', respectively, are shown. Moreover, it can
be seen from FIGS. 9-11 that the magnetizations of the storage
layers of the magnetic elements 102' and 104' are aligned
antiparallel. For clarity, the magnetic storage cell 100' is
depicted in the context of the magnetic memory 110. Consequently,
data lines 120' and 122' are also shown.
[0054] As can be seen in FIGS. 9-11, the magnetic elements are
preferably formed on the top layer of semiconductor circuitry on a
Si substrate. In addition, a cell plate 313 and 317 resides at the
bottom of each magnetic element 102' and 104', respectively. The
cell plates 313 and 317 are connected to the drain region 318 via a
324 contact. The source region 322 is shared with memory cell of
the adjacent memory cell array, and is connected to a bit line.
Because the two magnetic elements 102' and 104' share one selection
transistor 106', it is possible to reduce a region occupied by the
magnetic storage cell 100' by fabricating one magnetic element
102'/104' on top of the other magnetic element 104'/102'. This
reduction is by approximately a factor of two, in comparison with a
magnetic storage cell (not shown) in which two magnetic elements
might have their own transistors.
[0055] FIG. 12 is a cross-sectional view of a portion of another
embodiment of a magnetic storage cell 100'' in accordance with the
present invention. The magnetic storage cell 100'' includes
magnetic elements 102'' and 104''. The magnetic elements 102'' and
104'' shown are TMR junctions. Thus, the magnetic storage cell
102'' includes a seed layer 350, antiferromagnetic (AFM) layer 352,
a reference (pinned) layer 354, a tunneling barrier layer 362, a
data storage (free) layer 364 and capping layer 366. The reference
layer 354 is a synthetic pinned layer includes ferromagnetic layers
356 and 360 separated by a nonmagnetic spacer layer 358. In the
embodiment shown, the magnetizations of the ferromagnetic layers
356 and 360 are aligned antiparallel. Similarly, the magnetic
storage cell 104'' includes seed layer 368, data storage (free)
layer 370, tunneling barrier layer 372, reference (pinned) layer
374, AFM layer 382, and a capping layer 384. The reference layer
374 is a synthetic pinned layer includes ferromagnetic layers 376
and 380 separated by a nonmagnetic spacer layer 378. In the
embodiment shown, the magnetizations of the ferromagnetic layers
376 and 380 are aligned antiparallel. In addition, although shown
side-by-side in FIG. 12, the magnetic elements 102'' and 104'' may
be disposed vertically, preferably with the magnetic element 102''
residing above the magnetic element 104''.
[0056] As can be seen in FIG. 12, the magnetic element 102'' is
bottom pinned (reference layer 354 residing below/closer to the
substrate) while the magnetic element 104'' is top pinned. As a
result, the magnetizations of the data storage layers 364 and 370
are parallel or anti-parallel to the magnetization of the reference
layers 354 and 374, respectively, during writing operation
utilizing spin transferred current induced switching.
[0057] FIGS. 13 and 14 are cross-sectional views of a portion of
another embodiment of a magnetic storage cell 100''' in accordance
with the present invention. Thus, the magnetic elements 102'' and
104'' as well as transistor 106' and contact 436 are shown. The
magnetic element 104'' includes a seed layer 400, AFM layer 402, a
reference (pinned) layer 404, a tunneling barrier layer 412, a data
storage (free) layer 414 and capping layer 416. The reference layer
404 is a synthetic pinned layer includes ferromagnetic layers 406
and 410 separated by a nonmagnetic spacer layer 408. In the
embodiment shown, the magnetizations of the ferromagnetic layers
406 and 410 are aligned antiparallel. Similarly, the magnetic
storage cell 102'' includes seed layer 418, AFM layer 420,
reference (pinned) layer 422, tunneling barrier layer 430, data
storage (free) layer 432, and a capping layer 434. The reference
layer 422 is a synthetic pinned layer includes ferromagnetic layers
424 and 428 separated by a nonmagnetic spacer layer 426. In the
embodiment shown, the magnetizations of the ferromagnetic layers
424 and 428 are aligned antiparallel. For clarity, the magnetic
storage cell 100''' is depicted in the context of the magnetic
memory 110 such that data lines 120 and 122 are shown.
[0058] In the magnetic storage cell 100''' depicted, the magnetic
elements 102''' and 104''' share a single cell plate, formed by the
layers 416 and 418. As a result, the cell 100'' may be more easily
manufactured. Furthermore, the fluctuations in the characteristics
of the magnetic elements 102' and 104' may be is reduced.
[0059] FIG. 15 is a cross-sectional view of a portion of another
embodiment of a magnetic element 440 in accordance with the present
invention. The magnetic element 440 might be used for the magnetic
element 102 or the magnetic element 104. The magnetic element 440
includes seed layer 442, AFM layer 444, reference layer 446,
tunneling barrier layer 454, data storage (free) layer 456, an
additional spacer layer 458 that is either a tunneling barrier
layer or a nonmagnetic conductive spacer layer, another reference
(pinned) layer 460, AFM layer 462, and a capping layer 464. The
reference layer 446 is a synthetic layer including ferromagnetic
layers 448 and 453 separated by a conductive, nonmagnetic spacer
layer 450.
[0060] The magnetic element 440 can be relatively easily
manufactured. In addition, the spin transfer induced switching
current of the magnetic element 440 is reduced. As a result, the
write current required for writing to the magnetic element 440 is
significantly reduced. Consequently, the density of a magnetic
memory utilizing the magnetic element 440 may be increased due in
part to the reduced size taken up by selection transistors 106.
Moreover, the power consumption of magnetic memories using the
magnetic storage cells 100 may be significantly reduced.
[0061] FIG. 16 is a cross-sectional view of a portion of another
embodiment of a magnetic element 470 in accordance with the present
invention. The magnetic element 470 might be used for the magnetic
element 102 or the magnetic element 104. The magnetic element 470
includes seed layer 472, AFM layer 474, reference layer 476,
tunneling barrier layer 488, data storage (free) layer 490, a
spacer layer 492, an additional free layer 494, a layer 496 that is
either a tunneling barrier layer or a nonmagnetic conductive spacer
layer, another reference (pinned) layer 498, AFM layer 500, and a
capping layer 502. The reference layer 476 is a synthetic layer
including ferromagnetic layers 478, 482, and 486 separated by a
conductive, nonmagnetic spacer layer 450.
[0062] The magnetic element 470 can be relatively easily
manufactured. In addition, spin transfer induced switching current
of the magnetic element 470 is reduced. As a result, the write
current required for writing to the magnetic element 470 is
significantly reduced. Consequently, the density of a magnetic
memory utilizing the magnetic element 470 may be increased due in
part to the reduced size taken up by selection transistors 106 and
the power consumption of the magnetic memories may be significantly
lowered.
[0063] For the magnetic elements 102, 102', 102'', 102''', 104,
104', 104'', and 104''' various materials can be used for various
layers. The data storage layers, or free layers, 414, 432, 456,
490, and/or 494 preferably include at least one of Co, Fe, and Ni.
In some embodiments, the free layer 414, 432, 456, 490, and/or 494
may include at least one amorphous forming element, preferably at a
concentration of not more than thirty atomic percent. In one
embodiment, the amorphous forming element includes boron. Utilizing
the concentrations of the amorphous forming element, the saturation
magnetization of the free layer 414, 432, 456, 490, and/or 494 may
be engineered to reside between four hundred and one thousand five
hundred emu/cm.sup.3. Furthermore, the free layer 414, 432, 456,
490, and/or 494 may be a single layer, for example of ferromagnetic
or ferrimagnetic material. Such a ferromagnetic material may
include at least one of Co, CoFe with five to forty atomic percent
Fe, CoFeB with five to forty atomic percent Fe and five to thirty
atomic percent B, CoFeTa with five to forty atomic percent Fe and
five to thirty atomic percent Ta, NiFe with approximately twenty
atomic percent Fe, CoPt with five to forty atomic percent Pt, CoPd
with five to forty atomic percent Pd, FePt with five to forty
atomic percent Pt, Co.sub.2MnAl, Co.sub.2MnSi, or Co.sub.2CrAl,
Co.sub.2CrSi, Co.sub.2FeAl and Co.sub.2FeSi. The ferrimagnetic
material may include at least one of CoGd with fifteen to thirty
atomic percent Gd and FeGd with ten to forty atomic percent Gd.
[0064] The free layer 414, 432, 456, 490, and/or 494 may also be a
multilayer structure. Such a multilayer may be made out of
ferromagnetic layers only, or a combination of ferromagnetic layers
and nonmagnetic layers. Such a ferromagnetic material may include
at least one of Co, CoFe with five to forty atomic percent Fe,
CoFeB with five to forty atomic percent Fe and five to thirty
atomic percent B, CoFeTa with five to forty atomic percent Fe and
five to thirty atomic percent Ta, NiFe with approximately twenty
atomic percent Fe, CoPt with five to forty atomic percent Pt, CoPd
with five to forty atomic percent Pd, FePt with five to forty
atomic percent Pt, Co.sub.2MnAl, Co.sub.2MnSi, or Co.sub.2CrAl,
Co.sub.2CrSi, Co.sub.2FeAl and Co.sub.2FeSi. In one embodiment, the
free layer 414, 432, 456, 490, and/or 494 is a multilayer structure
including ferromagnetic layers and at least one nonmagnetic layer
separating each of a portion of the plurality of ferromagnetic
layers. In such an embodiment, the nonmagnetic layer includes at
least one of Ru, Rh, Re, Cr, and Cu. Also in such an embodiment,
the magnetizations of alternating ferromagnetic layers are aligned
antiparallel. However, another alignment of magnetizations may be
used.
[0065] The reference layers, or pinned layers 404, 422, 446, 476,
and/or 498 preferably includes at least one of Co, Fe, and Ni. In
some embodiments, the pinned layers 404, 422, 446, 476, and/or 498
may include at least one amorphous forming element, preferably at a
concentration of not more than thirty atomic percent. In one
embodiment, the amorphous forming element includes boron.
Furthermore, the pinned layers 404, 422, 446, 476, and/or 498 may
be a single layer, for example of ferromagnetic or ferrimagnetic
material. Such a ferromagnetic material may include at least one of
Co, CoFe with five to forty atomic percent Fe, CoFeB with five to
forty atomic percent Fe and five to thirty atomic percent B, CoFeTa
with five to forty atomic percent Fe and five to thirty atomic
percent Ta, NiFe with approximately twenty atomic percent Fe, CoPt
with five to forty atomic percent Pt, CoPd with five to forty
atomic percent Pd, FePt with five to forty atomic percent Pt,
Co.sub.2MnAl, Co.sub.2MnSi, or Co.sub.2CrAl, Co.sub.2CrSi,
Co.sub.2FeAl and Co.sub.2FeSi. The ferrimagnetic material may
include at least one of CoGd with fifteen to thirty atomic percent
Gd and FeGd with ten to forty atomic percent Gd.
[0066] The pinned layers 404, 422, 446, 476, and/or 498 may also be
a multilayer structure. Such a multilayer may be made out of
ferromagnetic layers only, or a combination of ferromagnetic layers
and nonmagnetic layers. Such a ferromagnetic material may include
at least one of Co, CoFe with five to forty atomic percent Fe,
CoFeB with five to forty atomic percent Fe and five to thirty
atomic percent B, CoFeTa with five to forty atomic percent Fe and
five to thirty atomic percent Ta, NiFe with approximately twenty
atomic percent Fe, CoPt with five to forty atomic percent Pt, CoPd
with five to forty atomic percent Pd, FePt with five to forty
atomic percent Pt, Co.sub.2MnAl, Co.sub.2MnSi, or Co.sub.2CrAl,
Co.sub.2CrSi, Co.sub.2FeAl and Co.sub.2FeSi. In one embodiment, the
pinned layers 404, 422, 446, 476, and/or 498 is a multilayer
structure including ferromagnetic layers and at least one
nonmagnetic layer separating each of a portion of the plurality of
ferromagnetic layers. In such an embodiment, the nonmagnetic layer
includes at least one of Ru, Rh, Re, Cr, and Cu. Also in such an
embodiment, the magnetizations of alternating ferromagnetic layers
are aligned antiparallel. However, another alignment of
magnetizations may be used.
[0067] The magnetic elements 102, 102', 102'', 102''', 104, 104',
104'', and 104''' may also include one or more tunneling barrier
layer 362, 372, 412, 430, 454, 458, 488, and/or 496. The tunneling
barrier layer 362, 372, 412, 430, 454, 458, 488, and/or 496 may
include at least one of AlO with forty to seventy atomic percent O,
MgO with thirty to sixty atomic percent O, and AlON with forty to
seventy atomic percent O and two to thirty atomic percent N, AlN
with thirty to sixty atomic percent N, AlZrO, AlHfO, AlTiO, and
AlTaO. In some embodiments, the tunneling barrier layer 362, 372,
412, 430, 454, 458, 488, and/or 496 may be made up of a single
layer or multiple layers. The tunneling barrier layer 362, 372,
412, 430, 454, 458, 488, and/or 496 preferably has a thickness of
at least five Angstroms and not more than forty Angstroms. In
addition, the tunneling barrier layer 362, 372, 412, 430, 454, 458,
488, and/or 496 preferably has a low resistance-area product. In a
preferred embodiment, this resistance-area product is between ten
and one hundred .OMEGA.-.mu.m.sup.2. The spacer layer 496 might be
conductive and include at least one of Cu, Ag, Pt, Al, Ru, Re, Rh,
Ta, and Ti or their alloys. The spacer layer 496 may also include a
nano-oxide layer (NOL), described below.
[0068] If a NOL is to be used for the spacer layer 496, the NOL
could be formed by depositing original metal starting material and
then oxidizing the deposited films using natural oxidation and/or
plasma oxidation. In another embodiment, the NOL may be formed
using radio frequency sputtering original oxide starting material.
In another embodiment, the NOL may be either magnetic, at least
partially. The starting metal material could be those similar those
used in the pinned or free layers, such as magnetic material CoFe,
CoFeB, and non magnetic material Al, Ta, Ru, and Ti. NOL might also
be Cu/CoFe, FeSi, Al, Ta, Ru or Ti/NOL/Cu in structure for
instance.
[0069] In some embodiments, the magnetic element 102, 102', 120',
102''', 104, 104', 104'' and/or 104''' also includes at least one
spacer layer 492. The spacer layer 492 preferably includes at least
one of Cu, Ag, Pt, Al, Ru, Re, Rh, Ta, and Ti or their alloys.
[0070] The magnetic elements 102, 102', 102'', 102''', 104, 104',
104'', and 104''' also include AFM layers 352, 382, 402, 420, 444,
462, 474, and 500. In a preferred embodiment, at least one of the
AFM layers 352, 382, 402, 420, 444, 462, 474, and 500 includes
PtMn, IrMn, or the like.
[0071] FIG. 17 is a flow chart depicting on embodiment of a method
550 in accordance with the present invention for providing a
magnetic memory. A plurality of magnetic storage cells 100 are
provided, via step 552. Providing the magnetic storage cells 100
includes providing a plurality of magnetic elements 102 and 104
capable of being programmed using spin transfer induced switching
by a write current driven through the magnetic element. Each of the
magnetic elements 102 and 104 has a first end and a second end. The
at least one selection transistor is also coupled to the first end
of each of the plurality of magnetic elements. A plurality of word
lines is provided such that the word lines are coupled with the
selection transistors and for selectively enabling a portion of the
plurality of selection transistors, via step 554. A plurality of
bit lines is provided, via step 556. The device is then completed,
via step 558.
[0072] Using the method 550, the magnetic memory cell 100, as well
as the memories 110, 140, 170, 200, 240, and 280 may be provided.
Consequently, a magnetic memory that utilizes a localized
phenomenon (spin transfer) for switching may be provided. The write
current required for current induced switching of the magnetization
of the data storage layers has decreased as the device density
grows following the scaling down rule compatible to semiconductor
or CMOS technology evolution. As a result, the magnetic memories
110, 140, 170, 200, 240, and 280 formed using the method 550 may
have lower power consumption and, therefore, smaller dimensions for
the transistor 106. In addition faster write and readout times, as
well as the other advantages described above, may be achieved for
the magnetic memories 110, 140, 170, 200, 240, and 280.
[0073] FIG. 18 is a flow chart depicting on embodiment of a method
560 in accordance with the present invention for utilizing a
magnetic memory, such as the magnetic memory 110, 140, 170, 200,
240, or 280. For a programming operation, a write current is driven
through a portion of the plurality of magnetic storage cells 100,
via step 562. Each magnetic storage cell includes a plurality of
magnetic elements, such as the magnetic elements 102 and 104, and
at least one selection transistor 106. The magnetic elements 102
and 104 are capable of being programmed using spin transfer induced
switching by the write current driven through the magnetic element
102 and 104. In addition, each magnetic element 102 and 104 has a
first end and a second end. The selection transistor 106 is coupled
to the first end of each magnetic element 102 and 104. Note that
the details of step 562 may depend upon the magnetic memory 110,
140, 170, 200, 240, or 280 being programmed. For example, the
combination of the lines and transistors activated or disabled to
drive the write current through the desired magnetic elements 102
and 104 in step 562 may depend upon the memory 110, 140, 170, 200,
240, or 280 being programmed.
[0074] For a read operation, a read current is driven through the
magnetic elements 102 and 104 of at least one magnetic storage cell
100 and data read by determining a differential signal based upon
the read signal or by comparing the read signal to a reference
signal, via step 564. Preferably, a differential signal is obtained
in step 564 for the memories 110, 140, 170, and 280. The
differential signal indicates the difference in the resistances of
the magnetic elements 102 and 104 for given cells. The details of
step 564 may depend upon the magnetic memory 110, 140, 170, or 280
being read. For example, the combination of the lines and
transistors activated or disabled to drive the read current through
the desired magnetic elements 102 and 104 and output the
differential signal in step 564 may depend upon the memory 110,
140, 170 or 280 being read.
[0075] For the magnetic memories 200 and 240 data are read in step
564 by comparing the readout signal to a reference signal. The
voltage signal indicates the difference in the resistances of the
magnetic elements 102 and 104 for given cells. The details of step
564 may depend upon the magnetic memory 200 and 240 being read. For
example, the combination of the lines and transistors activated or
disabled to establish the read voltage through the desired magnetic
elements 102 and 104 and output the voltage signal in step 564 may
depend upon the memory 200 and 240 being read.
[0076] Thus, using the method 560, the memories 110, 140, 170, 200,
240 and 280 may be programmed or read. The method 560 utilizes a
differential scheme for reading data from some memories, and
compares the read signal to a reference signal for other memories.
Because both magnetic elements 102 and 104 share one selection
transistor 106, the noise from the fluctuation in the
characteristics of the transistor may be reduced or eliminated. In
addition, the time delay due to the stray capacitance of the data
line may be less than one nano-second, providing an advantage of
high speed readout characteristics of this memory device.
[0077] A method and system for providing and using a magnetic
memory has been disclosed. The present invention has been described
in accordance with the embodiments shown, and one of ordinary skill
in the art will readily recognize that there could be variations to
the embodiments, and any variations would be within the spirit and
scope of the present invention. Accordingly, many modifications may
be made by one of ordinary skill in the art without departing from
the spirit and scope of the appended claims.
* * * * *