U.S. patent application number 11/152016 was filed with the patent office on 2006-12-14 for etch rate uniformity using the independent movement of electrode pieces.
This patent application is currently assigned to Lam Research Corporation, a Delaware Corporation. Invention is credited to Dae-han Choi, Jisoo Kim, S.M. Reza Sadjadi.
Application Number | 20060278339 11/152016 |
Document ID | / |
Family ID | 37067470 |
Filed Date | 2006-12-14 |
United States Patent
Application |
20060278339 |
Kind Code |
A1 |
Kim; Jisoo ; et al. |
December 14, 2006 |
Etch rate uniformity using the independent movement of electrode
pieces
Abstract
A plasma reactor comprises a chamber, a bottom electrode, a top
electrode, a bottom grounded extension adjacent to and
substantially encircling the bottom electrode. The top grounded
extension adjacent to and substantially parallel to the top
electrode. The top electrode is also grounded. The top grounded
extension is capable of being independently raised or lowered to
extend into a region above the bottom grounded extension.
Inventors: |
Kim; Jisoo; (Pleasanton,
CA) ; Choi; Dae-han; (Fremont, CA) ; Sadjadi;
S.M. Reza; (Saratoga, CA) |
Correspondence
Address: |
David B. Ritchie;THELEN REID & PRIEST LLP
P.O. Box 640640
San Jose
CA
95164-0640
US
|
Assignee: |
Lam Research Corporation, a
Delaware Corporation
|
Family ID: |
37067470 |
Appl. No.: |
11/152016 |
Filed: |
June 13, 2005 |
Current U.S.
Class: |
156/345.47 |
Current CPC
Class: |
H01J 37/32623 20130101;
H01J 37/32568 20130101; H01J 37/32091 20130101; H01J 37/32165
20130101 |
Class at
Publication: |
156/345.47 |
International
Class: |
C23F 1/00 20060101
C23F001/00 |
Claims
1. A plasma reactor comprising: a chamber; a bottom electrode and a
top electrode enclosed within said chamber; a bottom grounded
extension adjacent to and substantially encircling said bottom
electrode; a top grounded extension adjacent to and substantially
parallel to said top electrode; wherein said top grounded extension
is capable of being independently raised and lowered to extend into
a region above said bottom grounded extension.
2. The plasma reactor of claim 1 wherein said top grounded
extension includes a ring.
3. The plasma reactor of claim 1 wherein said bottom grounded
extension includes a ring.
4. The plasma reactor of claim 1 further comprising a power supply
coupled to said bottom electrode, said bottom electrode configured
to receive a workpiece.
5. The plasma reactor of claim 4 wherein said power supply
generates a plurality of frequencies to said bottom electrode.
6. The plasma reactor of claim 5 wherein said top electrode is
grounded.
7. A method for using a plasma reactor having a chamber with a top
electrode, a bottom electrode, a bottom grounded extension adjacent
to and substantially encircling said bottom electrode, a top
grounded extension adjacent to and substantially parallel to said
top electrode, the method comprising: adjusting a position of the
top grounded extension, the top grounded extension capable of being
independently raised and lowered to extend into a region above the
bottom grounded extension.
8. The method of claim 7 further comprising supplying power to the
bottom electrode, the bottom electrode configured to receive a
workpiece.
9. The method of claim 8 further comprising generating a plurality
of frequencies to the bottom electrode.
10. The method of claim 7 further comprising grounding the top
electrode.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to semiconductor fabrication.
More particularly, the present invention relates to a plasma
etching apparatus.
BACKGROUND OF THE INVENTION
[0002] A typical plasma etching apparatus comprises a reactor in
which there is a chamber through which reactive gas or gases flow.
Within the chamber, the gases are ionized into a plasma, typically
by radio frequency energy. The highly reactive ions of the plasma
are able to react with material, such as the dielectric between
interconnects or a polymer mask on a surface of a semiconductor
wafer during it being processed into Integrated Circuits (IC's).
Prior to etching, the wafer is placed in the chamber and held in
proper position by a chuck or holder which exposes a top surface of
the wafer to the plasma.
[0003] In semiconductor processing, the etch or deposition rate
uniformity across the wafer during each process directly affects
the device yield. This has become one of the main qualifying
requirements for a process reactor and hence is considered a very
important parameter during its design and development. With each
increase in the size of wafer diameter, the problem of ensuring
uniformity of each batch of integrated circuits becomes more
difficult. For instance, with the increase from 200 mm to 300 mm in
wafer size and smaller circuit size per wafer, the edge exclusion
shrinks to, for example, 2 mm. Thus maintaining a uniform etch
rate, profile, and critical dimensions all the way out to 2 mm from
the edge of the wafer has become very important.
[0004] In a plasma etch reactor, the uniformity of etch parameters'
(etch rate, profile, CD, etc.) is affected by several parameters.
Maintaining uniform plasma discharge and hence plasma chemistry
above the wafer has become very critical to improve the uniformity.
Many attempts have been-conceived to improve the uniformity of the
wafer by manipulating the gas flow injection through a showerhead,
modifying the design of the showerhead, and placing edge rings
around the wafer.
[0005] One problem in a capacitively-coupled etching reactor is the
lack of uniform RF coupling especially around the edge of a wafer.
FIG. 1 illustrates a conventional capacitively-coupled plasma
processing chamber 100, representing an exemplary plasma processing
chamber of the types typically employed to etch a substrate. The
plasma reactor 100 comprises a chamber 102, a bottom electrode 104,
a top electrode 106. The bottom electrode 104 includes a center
bottom electrode 108 and an edge bottom electrode 110. Top
electrode 106 includes a center top electrode 112 and an edge top
electrode 114. Edge top electrode 114 and edge bottom electrode 110
are in the shape of a ring respectively encircling center top
electrode 112 and center bottom electrode 108 to form a single
plane.
[0006] Center bottom electrode 108 is connected to RF power supply
118 while top electrode 106 and edge bottom electrode 110 are
grounded for draining charge from plasma 116 produced between top
electrode 106 and bottom electrode 104. As illustrated in FIG. 1,
the shape of the glow discharge region (plasma 116) is distorted
near the edge of center bottom electrode 108 because of grounded
edge bottom electrode 110. That distortion causes non-uniform etch
rate on a substrate (not shown) placed on center bottom electrode
108.
[0007] During plasma processing, the positive ions accelerate
across the equipotential field lines to impinge on the surface of
the substrate, thereby providing the desired etch effect, such as
improving etch directionality. Due to the geometry of the upper
electrode 106 and the bottom electrode 104, the field lines may not
be uniform across the wafer surface and may vary significantly at
the edge of the wafer 104. Accordingly, grounded ring 110 is
typically provided to improve process uniformity across the entire
wafer surface.
[0008] Because the parts in top electrode 106 are static, the etch
rate cannot be separately controlled at the center and at the edge
of the wafer. The non-uniformity during the etching process can
lead to different dimensions between the center and the edge
lowering the yield of reliable devices per wafer.
[0009] Accordingly, a need exists for a method and apparatus for
independently controlling the etch rate at the center and the edge
of a wafer. A primary purpose of the present invention is to solve
these needs and provide further, related advantages.
BRIEF DESCRIPTION OF THE INVENTION
[0010] A plasma reactor comprises a chamber, a bottom electrode, a
top electrode, a bottom grounded extension adjacent to and
substantially encircling the bottom electrode. The top grounded
extension adjacent to and substantially parallel to the top
electrode. The top electrode is also grounded. The top grounded
extension is capable of being independently raised or lowered to
extend into a region above the bottom grounded extension.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The accompanying drawings, which are incorporated into and
constitute a part of this specification, illustrate one or more
embodiments of the present invention and, together with the
detailed description, serve to explain the principles and
implementations of the invention.
[0012] In the drawings:
[0013] FIG. 1 is a diagram schematically illustrating a plasma
reactor in accordance with a prior art;
[0014] FIG. 2 is a diagram schematically illustrating a plasma
reactor in accordance with one embodiment.
[0015] FIG. 3 is a flow diagram schematically illustrating a method
for operating the plasma reactor illustrated in FIG. 2.
DETAILED DESCRIPTION
[0016] Embodiments of the present invention are described herein in
the context of plasma reactor. Those of ordinary skill in the art
will realize that the following detailed description of the present
invention is illustrative only and is not intended to be in any way
limiting. Other embodiments of the present invention will readily
suggest themselves to such skilled persons having the benefit of
this disclosure. Reference will now be made in detail to
implementations of the present invention as illustrated in the
accompanying drawings. The same reference indicators will be used
throughout the drawings and the following detailed description to
refer to the same or like parts.
[0017] In the interest of clarity, not all of the routine features
of the implementations described herein are shown and described. It
will, of course, be appreciated that in the development of any such
actual implementation, numerous implementation-specific decisions
must be made in order to achieve the developer's specific goals,
such as compliance with application- and business-related
constraints, and that these specific goals will vary from one
implementation to another and from one developer to another.
Moreover, it will be appreciated that such a development effort
might be complex and time-consuming, but would nevertheless be a
routine undertaking of engineering for those of ordinary skill in
the art having the benefit of this disclosure.
[0018] FIG. 2 illustrates one embodiment of a plasma reactor 200
comprising a chamber 202, a bottom electrode 208, a bottom
electrode extension 210, a top electrode 212, and a top electrode
extension 214. In accordance with one embodiment, bottom electrode
extension 210 includes a grounded ring 210 parallel and adjacent to
the bottom electrode 208 and encircling the bottom electrode 208.
The top electrode extension 214 includes a adjustable grounded ring
214 parallel and adjacent to the top electrode 212 and encircling
top electrode 212.
[0019] Bottom electrode 208 is connected to RF power supply 218
while top electrode 212, top electrode extension 214, and bottom
electrode extension 210 are grounded for draining charge from
plasma 216 produced between top electrode 212 and bottom electrode
208. By way of example, bottom electrode extension 210 and top
electrode extension 212 may be made of a conductive material such
as aluminum. As illustrated in FIG. 2, plasma 216 includes two
regions 220 and 222 having different plasma densities based on the
position (height) of top electrode extension 214.
[0020] Bottom electrode 208 is configured to receive a workpiece
and includes an associated bottom electrode area that is adapted to
receive the workpiece. Bottom electrode 208 is coupled to at least
one power supply 218. Power supply 218 is configured to generate RF
power that is communicated to bottom electrode 208. For
illustrative purposes only, a dual frequency power supply 218 may
be used to generate the high electric potential that is applied to
a gas to produce plasma 216. More particularly, the illustrated
power supply 218 is a dual power frequency power supply operating
at 2 MHz and 27 MHz that is included in etching systems
manufactured by Lam Research. It shall be appreciated by those
skilled in the art that other power supplies capable of generating
plasma in the processing chamber 202 may also be employed. It shall
be appreciated by those skilled in the art that the invention is
not limited to RF frequencies of 2 MHz and 27 MHz but may be
applicable to a wide range of frequencies. The invention is also
not limited to dual frequency power supplies but is also applicable
to systems that have three or more RF power sources with a wide
variety of frequencies.
[0021] Top electrode 212 is disposed at a predetermined distance
above from bottom electrode 208. Top electrode 212, top electrode
extension 214, together with ground extension 210 are configured to
provide a complete electrical circuit for RF power communicated
from bottom electrode 208. Top electrode extension 214 can move up
or down independently from top electrode 212 to manipulate plasma
density at the edge of bottom electrode 208--plasma region 222.
With the plasma density varied at the edge of bottom electrode 208,
the etch rate at that region can be independently controlled
(either faster rate or slower rate) from the etch rate in the
plasma region 220. Those of ordinary skills in the art will
appreciate that there are many ways to lower and raise the top
electrode extension 214. For example, a mechanical or motorized
knob may be used to raise or lower top electrode extension 214
without having to open and access the interior of chamber 202.
[0022] During plasma processing, the positive ions accelerate
across the equipotential field lines to impinge on the surface of
the substrate, thereby providing the desired etch effect, such as
improving etch directionality. Due to the geometry of top electrode
212 and bottom electrode 208, the field lines may not be uniform
across the wafer surface and may vary significantly at the edge of
the wafer. Accordingly, top and bottom electrodes extensions 214
and 210 are provided to improve process uniformity across the
entire wafer surface.
[0023] Plasma reactor 200 is configured to receive a gas (not
shown) that is converted into plasma 216 by plasma reactor 200. By
way of example and not of limitation, the relatively high gas flow
rate that is pumped into chamber is 1500 sccm. Gas flow rates less
than 1500 sccm as well as more than 1500 sccm may also be
applied.
[0024] To generate plasma 216 within chamber 202, power supply 218
is engaged and RF power is communicated between bottom electrode
208 and top electrode 212. Gas is then converted to plasma 216 that
is used for processing workpiece or a semiconductor substrate. By
way of example and not of limitation, RF power levels of 2 W per
cm.sup.3 of plasma volume may be applied. RF power levels of less
than 2 W per cm.sup.3 of plasma volume may also be applied.
[0025] For illustrative purposes, plasma reactor 200 described in
FIG. 2 employs capacitive coupling to generate plasma 216 in
processing chamber 202. It shall be appreciated by those skilled in
the art, that the present apparatus and method may be adapted to be
used with inductively coupled plasma.
[0026] Those of ordinary skill in the art will appreciate that the
above configurations shown in FIG. 2 are not intended to be
limiting and that other configurations can be used without
departing from the inventive concepts herein disclosed. For
example, two or more adjacent top electrode extension 214 may be
positioned to further control the etch rate at the edge of bottom
electrode 208.
[0027] FIG. 3 illustrates a method for using the plasma reactor
illustrated in FIG. 2. At 302, the position (raised or lowered) of
top electrode extension 214 is selected. Top electrode extension
214 is capable of being raised and lowered to extend into a region
above the bottom electrode extension. At 304, plasma reactor 200
processes a wafer supported by bottom electrode 208. At 306, the
wafer is examined to determine the etch uniformity throughout the
surface of the wafer. At 308, the position of top electrode
extension 214 is adjusted based on the analysis at 306 to further
improve the etch rate uniformity throughout the surface of the
wafer.
[0028] While embodiments and applications of this invention have
been shown and described, it would be apparent to those skilled in
the art having the benefit of this disclosure that many more
modifications than mentioned above are possible without departing
from the inventive concepts herein. The invention, therefore, is
not to be restricted except in the spirit of the appended
claims.
* * * * *