U.S. patent application number 11/479712 was filed with the patent office on 2006-11-09 for method for a low profile multi-ic chip package connector.
Invention is credited to Jerry M. Brooks, Jerrold L. King, Walter L. Moden.
Application Number | 20060252180 11/479712 |
Document ID | / |
Family ID | 22481724 |
Filed Date | 2006-11-09 |
United States Patent
Application |
20060252180 |
Kind Code |
A1 |
Moden; Walter L. ; et
al. |
November 9, 2006 |
Method for a low profile multi-IC chip package connector
Abstract
A method for a low profile multi-IC chip package for high-speed
applications comprises a connector for electrically connecting the
equivalent outer leads of a set of stacked primary semiconductor
packages. In one embodiment, the connector comprises a two-part
sheet of flexible insulative polymer with buses formed on one side.
In another embodiment, the connector comprises multiple buses
formed from conductive polymer. In further embodiments, the primary
packages are stacked within a cage and have their outer leads in
unattached contact with buses within the cage or, alternatively,
are directly fixed to leads or pads on the host circuit board.
Inventors: |
Moden; Walter L.; (Meridian,
ID) ; King; Jerrold L.; (Morgan Hill, CA) ;
Brooks; Jerry M.; (Caldwell, ID) |
Correspondence
Address: |
TRASK BRITT
P.O. BOX 2550
SALT LAKE CITY
UT
84110
US
|
Family ID: |
22481724 |
Appl. No.: |
11/479712 |
Filed: |
June 30, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11040967 |
Jan 21, 2005 |
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11479712 |
Jun 30, 2006 |
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10792222 |
Mar 3, 2004 |
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11040967 |
Jan 21, 2005 |
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10200792 |
Jul 22, 2002 |
6773955 |
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10792222 |
Mar 3, 2004 |
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09792771 |
Feb 23, 2001 |
6475831 |
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10200792 |
Jul 22, 2002 |
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09349522 |
Jul 8, 1999 |
6258623 |
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09792771 |
Feb 23, 2001 |
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09138372 |
Aug 21, 1998 |
6153929 |
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09349522 |
Jul 8, 1999 |
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Current U.S.
Class: |
438/106 ;
257/E25.023 |
Current CPC
Class: |
H01L 25/105 20130101;
H05K 2201/10515 20130101; H05K 2201/10689 20130101; H01L 2225/1064
20130101; H01L 2924/3011 20130101; H01L 2225/1094 20130101; Y02P
70/50 20151101; Y10T 29/4913 20150115; H05K 1/145 20130101; Y10T
29/49169 20150115; H01L 2225/1029 20130101; H01L 2225/107 20130101;
Y02P 70/611 20151101; H05K 2201/049 20130101; Y10T 29/49126
20150115; H01L 2924/0002 20130101; H05K 1/181 20130101; H05K 1/147
20130101; H01L 2924/0002 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
438/106 |
International
Class: |
H01L 21/00 20060101
H01L021/00 |
Claims
1. A method for connecting a stacked plurality of integrated
circuit packages on a substrate having a plurality of circuits
thereon using a cage, each integrated circuit package of the
stacked plurality having a plurality of outer leads and having a
plurality of sides, comprising: enclosing at least three sides of
the plurality of sides of each integrated circuit package of the
stacked plurality of integrated circuit packages using the cage;
and attaching the cage to the substrate using one of adhesive and
snap pins fitting in holes in the substrate, the cage connecting at
least one outer lead of the plurality of outer leads of the stacked
plurality of integrated circuit packages to at least one conductive
bus of a plurality of spaced transverse conductive buses, with a
portion of a semi-continuous flexible tape located within the
cage.
2. A stacking method for a plurality of integrated circuit packages
on a substrate having a plurality of circuits thereon using a cage,
each integrated circuit package of the plurality having a plurality
of outer leads and having a plurality of sides, comprising:
enclosing at least three sides of the plurality of sides of each
integrated circuit package of the plurality of integrated circuit
packages using the cage; and attaching the cage to the substrate
using one of adhesive and snap pins fitting in holes in the
substrate, the cage connecting at least one outer lead of the
plurality of outer leads of the plurality of integrated circuit
packages to at least one conductive bus of a plurality of spaced
transverse conductive buses, with a portion of a semi-continuous
flexible tape located within the cage.
3. A stacking method for integrated circuit packages on a substrate
having a plurality of circuits thereon using a cage, each
integrated circuit package having a plurality of outer leads and
having a plurality of sides, comprising: enclosing at least three
sides of the plurality of sides of each integrated circuit package
of the integrated circuit packages using the cage; and attaching
the cage to the substrate using one of adhesive and snap pins
fitting in holes in the substrate, the cage connecting at least one
outer lead of the plurality of outer leads of the integrated
circuit packages to at least one conductive bus of a plurality of
spaced transverse conductive buses, with a portion of a
semi-continuous flexible tape located within the cage.
4. An assembly method for integrated circuit packages on a
substrate having a plurality of circuits thereon using a cage, each
integrated circuit package having a plurality of outer leads and
having a plurality of sides, comprising: enclosing at least three
sides of the plurality of sides of each integrated circuit package
of the integrated circuit packages in the cage; and attaching the
cage to the substrate using one of adhesive and snap pins fitting
in holes in the substrate, the cage connecting at least one outer
lead of the plurality of outer leads of the integrated circuit
packages to at least one conductive bus of a plurality of spaced
transverse conductive buses, with a portion of a semi-continuous
flexible tape located within the cage.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of application Ser. No.
11/040,967, filed Jan. 21, 2005, pending, which is a divisional of
application Ser. No. 10/792,222, filed Mar. 3, 2004, pending, which
is a continuation of application Ser. No. 10/200,792, filed Jul.
22, 2002, now U.S. Pat. No. 6,773,955, issued Aug. 10, 2004, which
is a continuation of application Ser. No. 09/792,771, filed Feb.
23, 2001, now U.S. Pat. No. 6,475,831, issued Nov. 5, 2002, which
is a continuation of application Ser. No. 09/349,522, filed Jul. 8,
1999, now U.S. Pat. No. 6,258,623, issued Jul. 10, 2001, which is a
continuation of application Ser. No. 09/138,372, filed Aug. 21,
1998, now U.S. Pat. No. 6,153,929, issued Nov. 28, 2000.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] This invention relates generally to semiconductor device
assemblies having molded housings. More particularly, the invention
relates to connectors for joining a stack of packaged devices into
a small multi-IC chip assembly package operable at high speeds.
[0004] 2. Description of the Related Art
[0005] The evolution of the computer has resulted in a requirement
for greatly increased memory capacity in much smaller packages.
Another requirement is the capability for reliable operation at
much higher clock speeds, e.g., up to 800 MHZ or more. In addition,
the memory device(s) must be readily produced in high quantity and
at low cost with reduced rates of failure or rejection. One way to
provide a greater memory storage capacity in a smaller space is by
stacking a plurality of memory chips and interconnecting them to
produce a limited number of connections to e.g., a circuit board.
In so doing, a number of factors must be addressed, including heat
dissipation, ease of interconnection, impedance effects, etc.
[0006] Combining two or more semiconductor dice or chips in a
single semiconductor device assembly has been used to reduce the
space required for integrated circuits. Such devices are generally
known as multi-chip modules (MCM). In one form, dice are stacked
vertically on opposite sides of a substrate, for example, or atop
each other with intervening insulative layers, prior to
encapsulation. Examples of such devices are shown in U.S. Pat. No.
5,239,198 to Lin et al., U.S. Pat. No. 5,323,060 to Fogal et al.
and U.S. Pat. No. 5,495,398 to Takiar et al.
[0007] U.S. Pat. No. 5,604,377 discloses a rack with multiple
shelves for holding unpackaged chips. The chips are electrically
connected by lead frames to a wiring interface on a vertical
circuit board which can be connected to a PCB. The entire assembly
is contained in a sealed enclosure.
[0008] In U.S. Pat. No. 5,602,420 to Ogata et al., multiple
unpackaged dice having peripheral bond pads are spacedly stacked,
and corresponding bond pads are soldered with meltable balls to one
of a plurality of metal leads perpendicular to the dice. The active
surfaces of the dice may be coated with an insulative layer after
lead bonding, and/or the entire multi-die device may be
encapsulated.
[0009] U.S. Pat. No. 5,637,912 discloses a multi-chip module in
which chips are stacked in a vertical arrangement, and a
metallization pattern is deposited on a surface formed by the chip
edges.
[0010] MCM devices are also made which combine a number of dice
side-by-side on a substrate. The conventional single in-line
multi-chip module (SIMM) and dual in-line multi-chip modules (DIMM)
are common examples of this MCM configuration. Other examples are
shown in U.S. Pat. No. 5,137,836 to Lam, U.S. Pat. Nos. 4,992,849
and 4,992,850 to Corbett et al., U.S. Pat. No. 5,255,156 to Chang,
U.S. Pat. Nos. 5,239,747 and 5,461,544 to Ewers, U.S. Pat. No.
5,465,470 to Vongfuangfoo et al., and U.S. Pat. No. 5,480,840 to
Barnes et al.
[0011] U.S. Pat. No. 5,592,019 to Ueda et al. shows multiple
single-chip packages connected on end to a substrate by their
leads.
[0012] The y-axis stacking of multiple packaged devices has been
used in an effort toward miniaturization. In U.S. Pat. No.
5,155,067, a multi-chip package is shown wherein packaged devices
are stacked in a housing and sealed with a covering lid. The outer
leads of the devices are connected by, e.g., solder to conductive
pads on the housing, and the pads are attached to, e.g., DIP style
leads for attachment to a circuit board.
[0013] A stackable carrier for chips is shown in U.S. Pat. No.
4,996,587 to Hinrichsmeyer et al. A single chip or die is
adhesively positioned in an underside recess in the carrier and
conductive wires from the die are passed through a hole and bonded
to conductors formed on the upper surface of the carrier. S-shaped
connector clips are soldered to each of the I/O leads on opposed
edges of the carrier and to the clips of other carriers stacked
with it to form a multi-chip package (MCM).
[0014] In U.S. Pat. No. 5,514,907 to Moshayedi, a multi-chip memory
module has a plurality of stacked IC devices between opposing "side
boards," the latter comprising circuit boards with a pattern of
interconnected vias into which the pins of the devices are
soldered. The pins of the lowermost device are also soldered to the
substrate, such as a main circuit board, and comprise the
interconnection between the module and the circuit board.
[0015] U.S. Pat. No. 5,420,751 to Burns discloses a stacked IC
package which has vertical metal rails which pass through a cap
above the packaged devices. Each rail is soldered to corresponding
outer leads of the primary packages and has a lower end connectable
to a PCB. The primary devices are adhesively joined to prevent
movement of the devices in the stack package. Manufacture of the
rails is a complex process, and the manipulation of a large number
of parts to form the multi-IC chip package may be
counterproductive.
[0016] In a later issued patent to Burns, U.S. Pat. No. 5,484,959,
a stack package for thin small outline package (TSOP) devices is
shown with vertical metal rails for each set of corresponding outer
leads of the TSOP devices. A secondary "lead frame" for each TSOP
package has secondary leads which are soldered to the pins of the
TSOP package and to the metal rails. Each secondary lead is
particularly formed with a "flex offset" to provide a stress relief
connection with the rail.
[0017] As disclosed, the Bums apparatus requires a second lead
frame for each packaged primary device. Furthermore, additional
steps are required to form the stress relief offset. Furthermore,
maintaining the rails in parallel non-contact alignment during and
following soldering appears to be a major problem. A large number
of soldering steps is required to join the large number of
parts.
[0018] The aforementioned prior art patents disclose multi-chip
apparatuses which are deficient in one or more of the following (or
other) aspects: [0019] a. The multi-chip module is complex to make,
using a large number of parts which must be formed, aligned and
individually secured in the device. [0020] b. The y-dimension
(perpendicular to the host PCB) of the multi-chip module is
relatively great, and may be excessive for the particular end use.
[0021] c. Removal and replacement of a flawed primary device in the
module is extremely difficult and may exceed the value of the
module. [0022] d. The inability to pre-test each primary device
prior to incorporation into the multi-chip module results in an
increased failure rate in the final multi-chip device. [0023] e.
The leads and connections result in excessive impedance effects at
high clock speeds, i.e., greater than about 400 MHZ, and
particularly at speeds now anticipated, i.e., about 800 MHZ and
higher.
[0024] Among the many considerations in constructing semiconductor
devices is thermal expansion. With multi-chip devices in
particular, elasticity is required in the electrical connections to
accommodate thermal expansion, as well as dimensional variation in
the primary devices.
[0025] U.S. Pat. No. 5,600,183 to Gates, Jr. discloses a conductive
adhesive comprising a mixture of, e.g., silver powder in an epoxy
material.
[0026] U.S. Pat. No. 5,468,655 to Greer discloses a temporary
electrical connection comprising a metal paste applied to contact
pads, then heated to partially melt the metal. A solder bump may
then be placed in contact with the metal paste and heated to join
the bump thereto.
BRIEF SUMMARY OF THE INVENTION
[0027] The present invention comprises a stack package connector by
which a stack of primary packaged semiconductor devices is joined
to provide a secondary package which is joinable to a printed
circuit board or other host apparatus. In the invention, equivalent
outer leads of the primary packages are joined by flexible
conductive buses having low impedance and induction effects. One
end of each bus is directly connectable to contact pads or other
contact means of a host printed circuit board (PCB) or other
electronic apparatus.
[0028] In one aspect of the present invention, a plurality of
encapsulated integrated circuit packages is adhesively joined to
provide a stack to provide one or more planes in which
corresponding outer leads are positioned in vertical alignment. The
outer leads of each IC package are cut close to the package bodies.
Conductive buses are formed to join corresponding outer leads of
the packages and terminate in bus ends joinable to e.g., a PCB
(printed circuit board).
[0029] In one form of conductive bus, an elongate Y-axis conductor
tape is formed of a non-conducting material having parallel linear
conductive elements, i.e., buses, formed to span the tape. On one
side of the tape, the conductor ends are configured to enable ready
connection to bus lines of a circuit board. The width of the tape
may be varied to accommodate different numbers of stacked packages
of differing thicknesses in the stack package. The buses of the
tape are joined to the exposed outer leads of the primary packaged
devices, typically in a single step utilizing pressure, conductive
adhesive and/or other method. The polymer portion of the tape
between the buses may further have an adhesive surface for adhesion
to the stacked devices.
[0030] In another form of conductive bus, the stack is placed on a
circuit board with conductive pads and a thin stream of conductive
adhesive material such as a metal containing epoxy is applied to
corresponding outer leads and a conductive pad to form a conductive
bus.
[0031] In another aspect of the invention, a hollow cage is formed
for containing the stacked packaged devices. In one embodiment of
the invention, a pattern of bus traces is formed on a "flex PCB"
and attached to one inner wall of the cage. Each bus trace
terminates in a tab or lead end which is attachable to a host
circuit board. The outer leads of packages stacked in the cage are
bent to provide a degree of flexibility, and the flex PCB may be
attached to the cage wall with an elastomeric adhesive to provide
additional resiliency for accommodating variations in package
dimensions. The packages are stacked in the cage with friction fit,
i.e., without being adhesively joined to each other and having the
outer leads simply contacting the bus traces without being joined
to them by solder or other joining means. Thus, the primary
packaged devices may be individually removed and replaced without
desoldering or other disjoining step.
[0032] In a further embodiment of the present invention, the cage
is formed such that the primary packages have their major planar
surfaces aligned at right angles to the surface of the host PCB.
The single plane of outer leads is placed against and joined to
conductive pads on the surface of the host PCB. Thus, each outer
lead may be joined to a conductive pad. In an alternate version,
the PCB is formed with a series of elongate conductive pads. The
equivalent outer leads of all primary packages may be joined as a
set to a single elongate pad of the PCB.
[0033] In this description, the terms "chip" and "die" are used
interchangeably. In addition, the term "primary packaged device"
refers to an encapsulated package containing one or more dice, each
typically connected to a conductive lead frame having outer leads
or pins. Such packaged devices are typically identified as small
outline J-lead (SOJ), thin small outline packages (TSOP), plastic
leaded chip carrier (PLCC), single in-line plastic (SIP), dual
in-line plastic (DIP), and other descriptive names. The term
"secondary packaged device" refers to a device formed by combining
a plurality of primary packaged devices in a single module and
interconnecting the primary devices to provide a single set of
electrodes connectable to a circuit board or other host electrical
apparatus.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0034] The invention is illustrated in the following figures,
wherein the elements are not necessarily shown to scale and certain
features may be exaggerated in dimension:
[0035] FIG. 1 is a perspective view of a low profile multi-IC chip
package incorporating a package connector of the invention;
[0036] FIG. 2 is a cross-sectional view of a package connector for
a low profile multi-IC chip package of the invention, as taken
along line 2-2 of FIG. 8;
[0037] FIG. 3 is a cross-sectional view of another embodiment of a
package connector for a low profile multi-IC chip package of the
invention, as taken along line 2-2 of FIG. 8;
[0038] FIG. 4 is a cross-sectional view of a further embodiment of
a package connector for a low profile multi-IC chip package of the
invention, as taken along line 2-2 of FIG. 8;
[0039] FIG. 5 is a cross-sectional view of an additional embodiment
of a package connector for a low profile multi-IC chip package of
the invention, as taken along line 2-2 of FIG. 8;
[0040] FIG. 6 is a cross-sectional view of another embodiment of a
package connector for a low profile multi-IC chip package of the
invention, as taken along line 2-2 of FIG. 8;
[0041] FIG. 7 is a side view of a Y-axis conductive tape of a
package connector of the invention;
[0042] FIG. 8 is a top view of a Y-axis conductive tape of a
package connector of the invention;
[0043] FIG. 9 is a perspective view of another embodiment of a low
profile multi-IC chip package incorporating a package connector of
the invention;
[0044] FIG. 10 is a partial end view of a low profile multi-IC chip
package illustrating the formation of an electrical bus of a
connector thereof;
[0045] FIG. 11 is a plan view of a further embodiment of a low
profile multi-IC chip package incorporating a package connector of
the invention;
[0046] FIG. 12 is a cross-sectional side view of an embodiment of a
low profile multi-IC chip package incorporating a package connector
of the invention, as taken along line 11-11 of FIG. 11; and
[0047] FIG. 13 is a cross-sectional side view of another embodiment
of a low profile multi-IC chip package incorporating a package
connector of the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0048] An improved low profile, high-speed multi-IC chip connector
and resulting stack package for memory chips is provided by the
present invention. Different embodiments of the connector are
illustrated in the drawing figures. The connector is joined to a
stack of encapsulated semiconductor devices, each of which
comprises a primary package containing one or more electrically
connected dice. Preferably, each package has been burned-in and
tested prior to joining to the connector as part of a stack. The
stack package typically comprises at least two primary packages,
although the number of packages is more normally about 4 to 8, or
more. Any number of primary packages may be incorporated in a
secondary package, limited only by such considerations as space
requirements, the effect of bus length upon impedance, and the
like. Additionally, the secondary package is suitable for use of
primary packages having clock speeds of at least 400 MHZ, 800 MHZ,
or greater.
[0049] The various embodiments of the invention are particularly
applicable to high-speed memory packages such as are required to
achieve processing speeds of 800 MHZ or higher.
[0050] The speed capability of prior art memory chips has lagged
the capability of RAM (random access memory) chips, and has been a
significant limiting factor in the production of high-speed
computers and the like for operation at clock speeds of 600 MHZ and
higher. This invention may be particularly applied to the
advancement of memory chips, replacing current SIMM and DIMM module
designs which are inadequate.
[0051] Turning now to drawing FIG. 1, one embodiment of a
multi-chip package 10 of the invention is illustrated. The
multi-chip package 10 is shown with a stack 12 of four primary
semiconductor packaged devices 14, also simply called "primary
packages" herein, such as are well known in the art. Each primary
package 14 contains at least one semiconductor die having
interconnections such as by a lead frame to a plurality of outer
leads 16. The semiconductor die and lead frame are not visible in
the drawing figures, being within the protective layer of, e.g.,
insulative polymer on the exterior of each primary package 14. Each
primary package 14 is shown with major upper and lower surfaces 18
and 20 which are connected by package ends 22, 24 and lateral edges
26 and 28. Truncated outer leads 16 are shown extending outwardly
from each of lateral edges 26 and 28, respectively. The primary
packages 14 are joined to each other and to a host circuit board 30
by nonconductive adhesive material 32, which may be a tape such as
Kapton polyimide, or a flowable adhesive cement. Host circuit board
30 is shown with electrically conductive pads 34 for connection to
the multi-chip package 10.
[0052] The primary packages 14 are electrically joined by a
flexible connector 36, details of which are shown in drawing FIGS.
1-8.
[0053] The connector 36 comprises a layer 38 of insulative
polymeric material such as Kapton polyimide. On one side 42 of the
polymeric layer 38 is superposed a series of parallel conductive
buses 40. The buses 40 are spaced on the polymeric layer 38 to
match the spacing of the outer leads 16. The buses 40 may be metal
wire of varied cross-sectional shapes and adhesively joined to the
polymeric layer 38.
[0054] Shown in drawing FIGS. 2-6 are five exemplary configurations
of bus 40 which may be used in the connector 36. Other shapes may
also be used. The bus may be a simple round wire 40A attached with
adhesive 44 to side 42 of the polymeric layer 38, as shown in FIG.
2. The pitch 48 of the wires 40A is controlled to equal the spacing
or pitch of the outer leads 16. Side 54 of the polymeric layer 38
is the external surface of the connector 36.
[0055] In drawing FIG. 3, a semi-round wire 40B is depicted, and
drawing FIG. 4 shows a flat wire 40C attached with adhesive 44. As
depicted in drawing FIG. 5, a flat wire 40D with side grooves 46
for enhancing the attachment forces of the wire to the polymeric
layer 38 with adhesive 44 is shown.
[0056] Where the polymeric layer 38 is a thermoplastic, the bus 40
may be attached to the polymeric layer 38 by heating the wire and
pressing it into the polymeric layer 38. As shown in drawing FIG.
6, the wire 40E may have a shape which includes a lock 50 which is
embedded in the polymeric layer 38 for firmly attaching the bus to
the polymeric layer 38. The wire 40E may be heated by passing an
electric current through the wire.
[0057] As depicted in drawing FIG. 1, the flexibility of the
connector 36 permits conformation to the rows of outer leads 16 and
the lateral edges 26, 28 of the primary packages 14. The bending of
the connector 36 is exaggerated in FIG. 1 for better comprehension.
Use of the connector 36 of drawing FIG. 1 permits formation of a
four-package multi-chip package device 10 having an overall height
64 (FIG. 12) of about 6 mm or less.
[0058] The polymeric layer 38 of the connector 36 may have a
typical thickness 52 (FIG. 2) of about one (1) to about five (5)
mils, and is preferably formed of polyimide, although other
suitable polymers may be used. The buses 40 have cross-sectional
dimensions such that the impedance and inductance are sufficiently
low to enable high quality operation at the specified clock speed
and power rating. For example, in a multi-chip device of four
primary memory packages, a suitable round aluminum wire 40A
provides acceptable conductance and impedance.
[0059] In a preferred embodiment, the outer leads 16 of the primary
packages 14, as well as the buses 40, have a uniform pitch, i.e.,
spacing.
[0060] As shown in drawing FIG. 1, the buses 40 of connector 36 are
attached to the outer leads 16 of the primary packages 14 such that
the equivalent outer leads of the packages are attached to the same
bus. Each bus 40 has one end 56 which is attachable to a conductive
pad 34 of the host circuit board 30. The bus-to-lead and bus-to-pad
connections may be made with heat, e.g., a low temperature solder,
by pressure, or with application of a conductive adhesive, or by
any suitable well known connection methods in the art.
[0061] As depicted in drawing FIGS. 7 and 8, the connector 36 may
be formed as a semicontinuous tape 58 with transverse buses 40
attached to the polymeric layer 38, e.g., Kapton.TM. polyimide. The
tape 58 may be pre-manufactured to provide the desired bus
configurations, pitch 48 and tape widths 60 applicable to a
manufacturer's product line. The tape 58 is cut to fit each
multi-IC chip package. As shown, the tape 54 may be placed on a
spool 62 for easy dispensing and use. Alternately, a flex-circuit
having transverse buses 40 secured to an etched polymeric layer 38
exposing the buses 40 may be used.
[0062] In another embodiment of the invention shown in drawing FIG.
9, a multi-IC chip package 10 is shown with a stack 12 of primary
packages 14 as previously described. The outer leads 16 of the
primary packages 14 are truncated to extend only a short distance
outward from the packages. The connector 36 comprises a series of
buses 40 formed of a flowable conductive material which sets to a
hard but flexible conductor capable of high conductance, low
impedance performance. The conductive material of the buses 40 may
be a polymer e.g., epoxy, containing small particles of conductive
metal, i.e., silver, gold or aluminum. Alternatively, the bus
material may be a polymer having sufficient conductance and low
impedance for high-speed operation. Examples of conductive polymers
include doped polyacetylene, polypyrrole, polythiophene and
polyaniline. The dopant is selected to provide the desired
electrical properties and may be, for example, iodine. The material
may be selected to set upon a change in temperature or by
radiation, for example. If necessary, chemical agents for retarding
or enhancing the setting speed may be included in the polymer
formulation.
[0063] As shown in drawing FIG. 10, each bus 40 is formed by
passing conductive polymer 66 with a controlled setting rate in a
minute stream 68 from an outlet 74 of a polymer extruder 70. The
extruder is moved up and/or down in a vertical direction 72 and in
a horizontal direction 76 to join the equivalent outer leads 16 of
the primary packages 14 with the conductive pads 34 of the host
circuit board 30. The bus 40 is built up to the desired
cross-section for optimal device performance. A plurality, or even
all of the buses 40, may be formed simultaneously using a polymer
extruder 70 with multiple outlets 74.
[0064] In the embodiments of drawing FIGS. 1-10, the multi-IC chip
package is adaptable to stacks 12 of primary packages 14 having
outer leads 16 on one, two, three or four sides. The stack 12 may
comprise two or more primary packages 14, but typically will
comprise about four packages, each with outer leads 16 on one or
two sides.
[0065] Another embodiment of the invention is depicted in FIGS. 11
and 12. The multi-IC chip package 80 has a stack connector 82,
illustrated as comprising a cage 84, for holding by friction an
exemplary stack 86 of eight primary packages 14. The cage 84 is
shown to contact a portion or portions of lateral edge 26 of each
primary package 14, and closely approach or contact the package
ends 22, 24. The cage 84 partially encloses the primary packages 14
to retain them as a stack. The cage 84 may be formed of a thin
metal sheet, a strong polymeric material, ceramic, or the like. The
cage 84 is most easily formed from a metal sheet, extruded metal,
extruded plastic, molded plastic, thermoplastic, etc., typically of
five (5) to one hundred (100) mils thickness 100, which is cut and
bent at 90 degrees at each of the four corners 102, 104, 106, and
108, forming the five cage panels 110, 112, 114, 116 and 118. A gap
120 between coplanar panels 116 and 118 permits easy removal of
primary packages 14 from the cage 84. Particularly when formed of
metal, the high heat conductivity of the cage 84 results in
enhanced heat dissipation from the multi-IC chip package or module
80 during use. The cage 84 also acts as a heat sink to minimize
temperature variations of the primary packages 14.
[0066] On one interior wall 88, herein called the "active wall" of
the cage 84, a thin "flex PCB" 92 is attached by a layer 94 of
elastomeric adhesive. The thickness 96 of the elastomeric adhesive
layer 94 is controlled to provide a desired degree of flexibility.
Buses 90 are formed on the flex PCB 92 with a pitch 48 matching the
pitch 49 of the outer leads 16, and are positioned to contact the
sets of corresponding outer leads 16 of the primary packages 14
when they are inserted into the cage 84. The buses 90 may be metal
strips attached to the flex PCB 92 by adhesive, not shown, or may
be formed by metallization and lithographic bus separation, for
example. If desired, the outer leads 16 of the primary packages 14
may be soldered to the buses 90 or connected to the buses 90 using
suitable conductive material.
[0067] The lower end 124 of each of the buses 90 is shown as
comprising a horizontal portion insulated from the cage 84 by
non-conductive elastomeric adhesive layer 94. The lower end 124 may
be attached to a conductive pad or lead 34 of the host circuit
board 30 by methods well-known in the art, e.g., by surface
mounting with solder, bonding with conductive adhesive, and the
like.
[0068] The thin flex PCB 92 and elastomeric adhesive layer 94
provide resilience by which variations in dimensions of the primary
packages 14 and their buses 90 are accommodated. Typically, the
thickness 98 of the flex PCB 92 is about one (1) to five (5) mils,
and the thickness 96 of the adhesive layer is about three (3) to
eight (8) mils, but thicknesses lesser or greater than these values
may be used.
[0069] As shown, the outer leads 16 of the primary packages 14 are
bent to flex with compressive forces imposed by the cage 84, flex
PCB 92 and elastomeric adhesive layer 94. Thus, the electrical
connections are maintained by compression and friction. The primary
packages 14 may be easily inserted and extracted merely by pulling
them from the cage 84. Desoldering or other steps of heating,
cutting, etc. are not required to remove a primary package 14.
[0070] Where sharp forces on the host circuit board 30 may loosen a
primary package 14 within the cage 84, a small dab(s) of adhesive
may be used to fix the topmost primary package 14 to the cage. The
adhesive may be easily removed if necessary to replace a primary
package 14. Alternatively, a small node or nodes 122 of polymeric
material may be formed on one or more cage panels 110, 112, 114,
116 and 118 to provide an additional resistance to removal of any
primary package 14. The nodes 122 may be ribs which conform to the
shape of primary packages 14 to maintain the entire exemplary stack
86 immobile during use, yet allow easy removal.
[0071] In an example of this embodiment, a multi-IC chip package 80
with eight typical primary packages 14 eight-hundred (800) mils in
length and four-hundred-fifty (450) mils in width may have an
overall height of less than about ten (10) mm. This embodiment of a
multi-IC chip package 80 is most aptly applied to primary packages
14 having outer leads 16 along one side only. However, two opposing
flex PCB members 92 with buses 90 could be attached to opposing
inner walls of a cage 84 to accommodate primary packages 14 with
outer leads 16 along both opposing lateral edges 26 and 28.
[0072] In use, the cage 84 with attached flex PCB 92 and buses 90
is attached to the host circuit board 30 with adhesive and the bus
lower ends 124 are soldered or otherwise attached to the conductive
pads or leads 34 of the host circuit board 30. The primary packages
14 are then inserted and pushed downwardly within the cage 84 to
form an exemplary stack 86, the outer leads 16 of each primary
package 14 compressed slightly during the insertion step.
[0073] The footprints of the multi-IC chip packages 10 and 80 are
only slightly larger than the footprint of a primary package 14
which is stacked in packages 10 and 80. Thus, the density is
considerably greater than the SIMM and DIMM packages currently in
use. The number of primary packages 14 which may be incorporated in
the stack is typically eight or more, but fewer than eight may be
used.
[0074] Another embodiment of the multi-IC chip package is
illustrated in drawing FIG. 13. This multi-IC chip package 130 is
similar to the package 80 of drawing FIGS. 11 and 12, except that
the cage 132 has but three full panels and has no flex PCB or
buses. The cage 132 is rotated relative to cage 84 of package 80 so
that the outer leads 16 of the primary packages 14 may be directly
attached to conductive pads 34 or elongate leads of the host
circuit board 30 without an intervening panel. The primary packages
14 have their major upper and lower surfaces 18, 20 in a vertical
attitude and are stacked horizontally. Thus, the height dimension
134 is the same regardless of the number of primary packages 14 in
the stack. The two opposed cage walls are attached to the host
circuit board 30, e.g., by adhesive 136 or other means, such as
snap pins, not shown in drawing FIG. 13, which are fitted into
holes in the host circuit board 30. Alternately, the cage 132 may
be soldered to the host circuit board 30.
[0075] Nodes 122, such as small ribs, may be incorporated into
inner walls of the cage 132 to provide resistance to removal of the
primary packages 14 from the cage.
[0076] The footprint of the multi-IC chip package 130 is only
slightly larger than the footprint of a primary package 14 which is
stacked in packages 10 and 80. Thus, the density is considerably
greater than the SIMM and DIMM packages currently in use.
[0077] The invention provides for the use of buses which are
relatively short and of enhanced cross-section to produce low
impedance at high clock speeds, i.e., up to 800 MHZ, and relatively
high power ratings. The multi-IC chip packages are easy to produce
with high accuracy. Primary packages using well-developed
technologies and having pretested high reliability are used in the
stacks. The invention is applicable to high-speed memory modules
which are to supersede the SIMM and DIMM packages.
[0078] As indicated in the foregoing, each embodiment of the
multi-IC chip package of the invention has particular advantages
under particular circumstances.
[0079] It is apparent to those skilled in the art that various
changes and modifications may be made to the multi-IC chip stacked
package and package connector thereof in accordance with the
disclosure herein without departing from the spirit and scope of
the invention as defined in the following claims.
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