U.S. patent application number 11/448249 was filed with the patent office on 2006-10-26 for interconnects including members integral with bit lines, as well as metal nitride and metal silicide, and methods for fabricating interconnects and semiconductor device structures including the interconnects.
Invention is credited to Ralph Kauffman, J. Dennis Keller, Ruojia Lee.
Application Number | 20060237821 11/448249 |
Document ID | / |
Family ID | 22289312 |
Filed Date | 2006-10-26 |
United States Patent
Application |
20060237821 |
Kind Code |
A1 |
Lee; Ruojia ; et
al. |
October 26, 2006 |
Interconnects including members integral with bit lines, as well as
metal nitride and metal silicide, and methods for fabricating
interconnects and semiconductor device structures including the
interconnects
Abstract
An interconnect includes a member that is integral and lacks a
discernable boundary with a bit line, as well as metal nitride and
metal silicide between the member and an active-device region of a
semiconductor substrate. The interconnect may extend adjacent to
and be insulated from a stacked capacitor structure to facilitate
electrical communication between the active-device region and the
bit line. Methods for fabricating such an interconnect are
disclosed, as methods for fabricating semiconductor device
structures that include one or more such interconnects.
Inventors: |
Lee; Ruojia; (Boise, ID)
; Kauffman; Ralph; (Boise, ID) ; Keller; J.
Dennis; (Boise, ID) |
Correspondence
Address: |
TRASK BRITT
P.O. BOX 2550
SALT LAKE CITY
UT
84110
US
|
Family ID: |
22289312 |
Appl. No.: |
11/448249 |
Filed: |
June 6, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10931181 |
Aug 30, 2004 |
7057285 |
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11448249 |
Jun 6, 2006 |
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|
10180846 |
Jun 26, 2002 |
6787428 |
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10931181 |
Aug 30, 2004 |
|
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09651384 |
Aug 29, 2000 |
6465319 |
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10180846 |
Jun 26, 2002 |
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09102331 |
Jun 22, 1998 |
6165863 |
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09651384 |
Aug 29, 2000 |
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Current U.S.
Class: |
257/635 ;
257/E21.165; 257/E21.507; 257/E21.62; 257/E21.627 |
Current CPC
Class: |
H01L 21/76897 20130101;
H01L 21/823475 20130101; H01L 27/10811 20130101; H01L 27/10888
20130101; H01L 21/823425 20130101; H01L 28/91 20130101; H01L
21/28518 20130101 |
Class at
Publication: |
257/635 |
International
Class: |
H01L 23/58 20060101
H01L023/58 |
Claims
1. An interconnect for connecting an active-device region of a
semiconductor substrate to a bit line extending above a
semiconductor device structure, comprising: metal silicide in
contact with the active-device region; a member in communication
with the bit line, the member and the bit line comprising a unitary
structure with no discernable boundary therebetween; and metal
nitride substantially confined between the metal silicide and the
member.
2. The interconnect of claim 1, wherein the metal nitride comprises
titanium nitride.
3. The interconnect of claim 1, wherein the metal nitride and the
member comprise a buried metal diffusion structure.
4. The interconnect of claim 1, wherein the metal silicide
comprises at least one of titanium silicide and tungsten
silicide.
5. The interconnect of claim 1, wherein the member has a
resistivity of less than about 5 .mu..OMEGA.-cm.
6. The interconnect of claim 1, wherein the member comprises
aluminum.
7. An interconnect for connecting an active-device region of a
semiconductor substrate to a bit line extending above a
semiconductor device structure, comprising: a member extending from
the bit line, the member and the bit line comprising a unitary
structure with no discernable boundary therebetween; a metal
silicide adjacent to the active-device region; and metal nitride
positioned between the metal silicide and the member, an entirety
of the metal nitride being superimposed relative to the metal
silicide.
8. The interconnect of claim 7, wherein the metal silicide contacts
the active-device region.
9. The interconnect of claim 7, wherein the metal silicide contacts
the member.
10. The interconnect of claim 7, wherein the metal nitride
comprises titanium nitride.
11. The interconnect of claim 7, wherein adjacent portion of the
metal silicide and the member comprise a buried metal diffusion
structure.
12. The interconnect of claim 7, wherein the metal silicide
comprises at least one of titanium silicide and tungsten
silicide.
13. The interconnect of claim 7, wherein the member has a
resistivity of less than about 5 .mu..OMEGA.-cm.
14. The interconnect of claim 7, wherein the member comprises
aluminum.
15. A method for fabricating a semiconductor device structure,
comprising: forming at least one trench through at least one
stacked capacitor structure to expose at least one active device
region; forming a buried metal diffusion layer within the trench;
forming metal nitride adjacent to the buried metal diffusion layer;
concurrently introducing conductive material over the at least one
stacked capacitor structure and within the at least one trench, the
metal nitride substantially confined between the buried metal
diffusion layer and the conductive material; and forming at least
one bit line from conductive material located over at least the at
least one stacked capacitor structure, with no discernable boundary
between the at least one bit line and at least one member formed by
conductive material within the at least one trench.
16. The method of claim 15, further comprising: electrically
isolating the at least one trench from the at least one stacked
capacitor structure.
17. The method of claim 15, wherein forming the buried metal
diffusion layer comprises forming a metal silicide layer on the
surface of the at least one active-device region.
18. The method of claim 17, wherein forming the buried metal
diffusion layer includes selectively depositing the metal silicide
layer.
19. The method of claim 17, wherein forming the buried metal
diffusion layer includes depositing a metal or metal nitride and
annealing the metal or metal nitride layer to the at least one
active-device region.
20. The method of claim 15, wherein forming metal nitride comprises
depositing metal nitride on the buried metal diffusion layer.
21. The method of claim 20, wherein depositing metal nitride
comprises selectively depositing metal nitride.
22. The method of claim 21, further comprising: selectively
removing metal nitride from surfaces of the at least one trench and
over the at least one stacked capacitor structure.
23. The method of claim 15, wherein concurrently introducing
comprises concurrently introducing conductive material comprising
aluminum.
24. The method of claim 15, wherein forming the at least one bit
line comprises patterning the conductive material located over at
least the at least one stacked capacitor structure.
25. The method of claim 15, wherein forming the bit line comprising
selectively removing the material from locations over the at least
one stacked capacitor structure.
26. The method of claim 25, wherein selectively removing includes
planarizing the conductive material.
27. The method of claim 25, wherein selectively removing includes
etching the conductive material.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of application Ser. No.
10/931,181, filed Aug. 30, 2004, which will issue as U.S. Pat. No.
7,057,285, on Jun. 6, 2006, which is a continuation of application
Ser. No. 10/180,846, filed Jun. 26, 2002, now U.S. Pat. No.
6,787,428, issued Sep. 7, 2004, which is a continuation of
application Ser. No. 09/651,384, filed Aug. 29, 2000, now U.S. Pat.
No. 6,465,319, issued Oct. 15, 2002, which is a continuation of
application Ser. No. 09/102,331, filed Jun. 22, 1998, now U.S. Pat.
No. 6,165,863, issued Dec. 26, 2000.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to stacked capacitor
structures of semiconductor devices. In particular, the present
invention relates to semiconductor device structures which include
aluminum plugs disposed between the active device regions and bit
lines thereof. More specifically, the present invention relates to
semiconductor device structures which include an aluminum-filled
trench that electrically connects a bit line to an active device
region positioned between adjacent stacked capacitor
structures.
[0004] 2. Background of Related Art
[0005] Stacked capacitors are employed in many state of the art
semiconductor devices to maintain high storage capacitance despite
the ever-increasing densities of such semiconductor devices.
Stacked capacitors typically make an electrical connection with a
diffusion region, or active device region, of a semiconductor
substrate, such as silicon, polysilicon, gallium arsenide, or
indium phosphide. Some conventional processes for fabricating
stacked capacitors on semiconductor device structures facilitate
increased densities by employing electrically conductive layers
(e.g., polysilicon layers) that are somewhat convoluted or have
large surface areas, and which project outwardly relative to and
electrically contact their associated active device regions. The
remainders of the capacitor structures are then fabricated on the
electrically conductive layers.
[0006] Many stacked capacitor structures include electrically
conductive contacts between the active device regions and the bit
lines thereof. Typically, such electrically conductive contacts are
fabricated from polysilicon, which withstands the high temperature
processes (e.g., thermal oxidation processes or thermal anneal
processes) that are usually performed subsequent to the fabrication
of contacts on semiconductor device structures. Such contacts,
however, may create a somewhat undesirable amount of contact
resistance during operation of the semiconductor device.
[0007] Metals have also been employed as the contact material
between the active device region and bit lines of semiconductor
devices and through the stacked capacitor structures thereof.
Again, due to the high process temperatures that are employed
following the fabrication of the contacts, metals that will
withstand high process temperatures are typically employed in the
contacts. Metals that will withstand such high process temperatures
are commonly referred to as "refractory metals" and include
titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta).
While these metals and their silicides have low resistivities
relative to other metals, their resistivities (.rho..sub.Ti=43-47
.mu..OMEGA.-cm, .rho..sub.W=5.3 .mu..OMEGA.-cm, .rho..sub.Mo=5
.mu..OMEGA.-cm, and .rho..sub.Ta=13-16 .mu..OMEGA.-cm) may be
somewhat undesirable during the operation of state of the art very
large scale integration (VLSI) and ultra large scale integration
(ULSI) semiconductor devices. As metals of higher resistivity are
employed in such semiconductor devices, the power requirements and
operating temperature of such semiconductor devices increase
undesirably.
[0008] Conventionally, aluminum (Al) has been widely employed as an
electrically conductive material in semiconductor devices, as it
has low resistivity (.rho..sub.Al=2.7 .mu..OMEGA.-cm) and is
compatible with both silicon (Si) and silicon dioxide (SiO.sub.2).
Aluminum is not, however, typically employed in self-aligned
processes due to its inability to withstand high temperature
processing, such as the rapid thermal anneal processes that may be
employed in fabricating self-aligned silicide layers.
[0009] What is needed is a process for fabricating a stacked
capacitor structure on a semiconductor device structure which
increases the speed of the semiconductor device and reduces the
interconnect resistance and power consumption thereof and a stacked
capacitor structure and semiconductor device structure fabricated
by such a process.
SUMMARY OF THE INVENTION
[0010] The present invention includes a stacked capacitor structure
and methods of fabricating the stacked capacitor structure which
address the foregoing needs.
[0011] The stacked capacitor structure of the present invention
includes a trench disposed over an active device region of a
semiconductor device structure. The trench extends downward through
the stacked capacitor structure to the active device region of the
semiconductor substrate (e.g., silicon, gallium arsenide, indium
phosphide), exposing same through the stacked capacitor structure.
A layer of self-aligned metal silicide, or "salicide," is disposed
within the trench, adjacent the active device region and preferably
defining a buried metal diffusion (BMD) layer with the active
device region. An aluminum interconnect, or "contact," is disposed
within the trench in contact with the metal silicide and
substantially filling the trench. The aluminum interconnect
preferably provides an electrical link between the active device
region and a bit line that extends above the stacked capacitor
structure and electrically contacts the interconnect.
[0012] A method of fabricating a stacked capacitor structure is
also within the scope of the present invention. The method includes
fabricating a stacked capacitor structure over a semiconductor
device structure and defining a trench through the stacked
capacitor structure and over an active device region of the
semiconductor device structure. Processes for fabricating stacked
capacitor structures and defining trenches therethrough to an
underlying active device region, which may be employed in the
method of the present invention, are disclosed in U.S. Pat. No.
5,498,562 ("the '562 patent"), which issued to Dennison et al. on
Mar. 12, 1996, the disclosure of which is hereby incorporated by
reference in its entirety.
[0013] A layer of a metal that will form a salicide with the
silicon exposed through the trench, such as titanium or tungsten,
is then deposited over the semiconductor device structure. Known
processes, such as rapid thermal anneal (RTA) or silicide
deposition processes, may then be employed to form the salicide
layer, such as titanium silicide (TiSi.sub.x, predominantly
TiSi.sub.2) or tungsten silicide (WSi.sub.x, predominantly
WSi.sub.2), which is typically referred to as a "selective"
contact, over the active device region of the semiconductor device
structure. The formation of suicides such as TiSi.sub.2 and
WSi.sub.2 is said to be self-aligned since the silicide forms only
over exposed semiconductor substrate (e.g., silicon and
polysilicon) regions of a semiconductor device structure.
Everywhere else, the metal film overlies an insulative,
substantially non-reactive oxide layer, and may subsequently be
removed. Preferably, the metal silicide diffuses into the silicon
and defines a BMD layer. A metal nitride layer may also be
fabricated over the selective contact by known techniques. Such
metal nitride layers are typically referred to as "barrier" layers,
as they prevent the diffusion of silicon and silicide into any
metal layer or structure that is subsequently fabricated adjacent
thereto.
[0014] An interconnect is fabricated in the trench by depositing
aluminum over the semiconductor device structure in a manner that
substantially fills the trench. Known processes, such as physical
vapor deposition (PVD) and chemical vapor deposition (CVD)
techniques, may be employed to deposit aluminum over the
semiconductor device structure. The aluminum that covers other
areas of the semiconductor device structure may then be removed by
known processes, such as by known planarization (e.g., by
chemical-mechanical polishing (CMP) techniques) or etching
techniques, which do not remove aluminum from the trench.
Additional layers and structures may then be fabricated or defined
above the stacked capacitor, including, without limitation, bit
lines that are in electrical contact with one or more corresponding
aluminum interconnects.
[0015] Alternatively, portions of the aluminum layer that overlie
the semiconductor device structure may be selectively removed
therefrom by known techniques, such as masking and etching
processes, in order to define bit lines that are integral with the
aluminum interconnects and extend over an active surface of the
semiconductor device structure. Such aluminum bit lines may be
desirable since they may further reduce contact resistance and are
compatible with the adjacent silicon dioxide of the semiconductor
device structure.
[0016] The advantages of the present invention will become apparent
to those of skill in the art through a consideration of the ensuing
description, the accompanying drawings, and the appended
claims.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0017] FIG. 1 is a cross-sectional schematic representation of a
semiconductor device structure including an aluminum interconnect
extending from an active device region of the semiconductor
substrate and through a stacked capacitor structure to a bit line;
and
[0018] FIGS. 2-8 are cross-sectional schematic representations
which illustrate a process of fabricating the semiconductor device
structure of FIG. 1 in accordance with the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0019] With reference to FIG. 1, a semiconductor device structure
10 according to the present invention is shown. Semiconductor
device structure 10 includes a semiconductor substrate 12, such as
silicon, gallium arsenide, or indium phosphide, a field oxide layer
14 disposed over various regions of semiconductor substrate 12,
active device regions 16 in semiconductor substrate 12, word lines
18 extending over semiconductor substrate 12 and field oxide layer
14, and a stacked capacitor structure 20 disposed over word lines
18 and active device regions 16.
[0020] A trench 22 extends through stacked capacitor structure 20,
exposing a source/drain 24, or p-n region, of active device region
16 to an active surface 11 of semiconductor device structure 10. A
metal silicide selective contact 38 may be disposed over
source/drain 24, and preferably defines a buried metal diffusion
layer 39 in the semiconductor substrate 12 of source/drain 24.
Selective contact 38 preferably comprises titanium silicide. A
metal nitride layer 40, preferably titanium nitride (TiN), may be
disposed over selective contact 38. The remainder of trench 22 is
filled with aluminum, which defines an aluminum interconnect 34, or
contact or plug.
[0021] Aluminum interconnect 34 is in electrical communication with
a bit line 36 that extends over semiconductor device structure 10
above the stacked capacitor structures 20 thereof. Bit line 36 may
be fabricated from an electrically conductive material, including,
without limitation, metals such as aluminum, tungsten and titanium,
electrically conductive polymers, and doped polysilicon. If bit
line 36 is fabricated from aluminum, bit line 36 and aluminum
interconnect 34 are preferably integral.
[0022] Referring now to FIGS. 2-8, a method of fabricating a
semiconductor device structure 10 in accordance with the present
invention is illustrated. FIG. 2 illustrates a semiconductor device
structure 10 with active device regions 16, word lines 18, and a
stacked capacitor structure 20 disposed thereon. Each of these
features may be fabricated as known in the art, such as by the
process disclosed in the '562 patent.
[0023] Turning now to FIG. 3, a trench 22 is defined through
stacked capacitor structure 20 by known processes, such as the mask
and anisotropic etch processes that are disclosed in the '562
patent. Any electrically conductive features of the stacked
capacitor structure 20, such as the electrically conductive
(typically polysilicon) layer 21 thereof, that are exposed to
trench 22 may be oxidized by known processes to insulate these
electrically conductive features from the subsequently fabricated
aluminum interconnect 34 (see FIG. 1), as disclosed in the '562
patent. Preferably, in order to prevent oxidation of source/drain
24 as any exposed electrically conductive features of stacked
capacitor structure 20 are insulated, such insulation is performed
before trench 22 has been completely defined and, therefore, prior
to the exposure of source/drain 24 through trench 22.
[0024] With reference to FIG. 4, a selective contact 38 of a metal
silicide may then be fabricated over source/drain 24. Metal
silicides that may be employed as selective contact 38 include,
without limitation, titanium silicide (TiSi.sub.x, predominantly
TiSi.sub.2), tungsten silicide (WSi.sub.x, predominantly
WSi.sub.2), molybdenum silicide (MoSi.sub.x, predominantly
MoSi.sub.2), and platinum silicide (PtSi.sub.x, predominantly
PtSi.sub.2). Known processes may be employed to form selective
contact 38. An exemplary process for fabricating selective contact
38 includes the deposition of a metal or metal nitride over
semiconductor device structure 10, a rapid thermal anneal of the
metal or metal nitride to the exposed regions of semiconductor
substrate 12 to form the salicide selective contact 38, and removal
of the non-reacted metal or metal nitride from the active surface
11 of the semiconductor device structure 10.
[0025] Alternatively, selective contact 38 may be selectively
deposited onto source/drain 24 by chemical vapor deposition (CVD)
of a metallic precursor and a silicon-containing compound. For
example, when titanium silicide selective contacts are desired, a
titanium tetrahalide, such as titanium tetrachloride (TiCl.sub.4),
is reacted with either silane (SiH.sub.4) or dichlorosilane (DCS,
SiH.sub.2Cl.sub.2) as follows:
TiCl.sub.4+SiH.sub.4.fwdarw.TiSi.sub.2.dwnarw.
TiCl.sub.4+SiH.sub.2Cl.sub.2.fwdarw.TiSi.sub.2.dwnarw.
[0026] In order to optimize the selectivity of these titanium
silicide deposition reactions for the semiconductor substrate 12,
which is exposed through trench 22, a deposition temperature in the
range of about 650.degree. C. to about 750.degree. C. is
preferable. Since minimal amounts of the semiconductor substrate 12
are consumed by these reactions, the deposition reaction is allowed
to continue until a selective contact 38 of the desired thickness
is formed.
[0027] Other exemplary metal silicide deposition processes that may
be employed in the present invention to fabricate selective contact
38 include the reaction of a titanium halide and/or a gaseous
titanium organometallic precursor with a silicon-containing
compound of the formula Si.sub.nH.sub.2n+2, as disclosed in U.S.
Pat. No. 5,240,739, issued to Trung Doan et al. on Aug. 31, 1993;
U.S. Pat. No. 5,278,100, issued to Trung Doan et al. on Jan. 11,
1994; and U.S. Pat. No. 5,376,405, issued to Trung Doan et al. on
Dec. 27, 1994, the disclosures of each of which are hereby
incorporated by reference in their entirety. Titanium halides that
may be employed in the deposition of selective contact 38 over
source/drain 24 include, without limitation, TiCl.sub.4, titanium
tetraboride, titanium tetrafluoride, titanium tetraiodide, and
subhalides. Titanium organometallic precursors which may be used to
fabricate selective contact 38 include, but are not limited to,
compounds of the formula Ti(NR.sub.2).sub.4, where the titanium
atom is bonded to the nitrogen atom and R comprises hydrogen or a
carbon-containing radical. Exemplary compounds include
tetradimethylamido titanium (TDMAT or Ti(N(CH.sub.3).sub.2).sub.4
and Ti(N(C.sub.2H.sub.5).sub.2).sub.4).
[0028] The following are exemplary chemical reactions for
depositing metal silicide on source/drain 24:
nTiCl.sub.4+Si.sub.nH.sub.2n+2.fwdarw.nTiSi+4nHCl+H.sub.2+by-products;
nTiCl.sub.4+2Si.sub.nH.sub.2n+2.fwdarw.nTiSi+4nHCl+2H.sub.2+by-products;
TiCl.sub.4+Si.sub.nH.sub.2n+2.fwdarw.Ti.sub.5Si.sub.3+HCl+H.sub.2+by-prod-
ucts; TDMAT+Si.sub.2H.sub.6.fwdarw.TiSi.sub.2+organic by-products;
TDMAT+Si.sub.nH.sub.2n+2.fwdarw.(n/2)TiSi.sub.2+organic
by-products; and
Ti(NR.sub.2).sub.4+SiH.sub.4.fwdarw.TiSi.sub.x+TiSi.sub.yN.sub.1-y+organi-
c by-products, where x is predominantly equal to two, y is zero or
one and n is an integer equal to zero or more. The reaction between
TiCl.sub.4 and Si.sub.2H.sub.6 may be employed to deposit selective
contact 38 over source/drain 24 at a temperature as low as about
400.degree. C. The reaction of TiCl.sub.4 and Si.sub.3H.sub.8
deposits a titanium silicide selective contact 38 on a
semiconductor substrate 12 at a temperature of about 300.degree. C.
or higher.
[0029] Preferably, selective contact 38 and semiconductor substrate
12 diffuse into each other to define a buried metal diffusion layer
39.
[0030] Although silicide deposition in accordance with the
foregoing processes is selective for semiconductor substrate 12,
residual metal silicide may be deposited above stacked capacitor
structure 20. Thus, cleaning of semiconductor device structure 10
may be desirable in order to remove any residual metal silicide
from above stacked capacitor structure 20. Cleaning agents such as
chlorine (Cl.sub.2), hydrochloric acid (HCl) and hydrofluoric acid
(HF) may be employed in known cleaning techniques (e.g., thermal
gas, plasma assisted, and remote plasma activated cleaning) to
clean any residual metal silicides from field oxide layer 14.
[0031] Referring now to FIG. 5, upon depositing a selective contact
38 of the desired thickness, a metal nitride layer 40, which is
also referred to as a barrier layer, may be deposited over
selective contact 38. A metallic precursor and another reactant,
which are collectively referred to as second reactants, may be
reacted to deposit metal nitride layer 40 over semiconductor device
structure 10. The metallic precursor, which is preferably
TiCl.sub.4 when selective contact 38 is comprised of titanium
silicide, is reacted with ammonia (NH.sub.3) to initiate the
following chemical reaction, which deposits a metal nitride layer
40 of titanium nitride over the surface of semiconductor device
structure 10: TiCl.sub.4+NH.sub.3.fwdarw.TiN.dwnarw., including
above the stacked capacitor structures 20 and selective contacts 38
of the semiconductor device structure 10 (i.e., a "blanket"
deposition occurs). The duration of the foregoing reaction is
dependent upon the desired thickness of metal nitride layer 40.
This reaction may also be carried out in the presence of nitrogen
gas (N.sub.2), as discussed in U.S. Pat. No. 5,416,045 ("the '045
patent"), issued to Ralph E. Kauffman et al. on May 16, 1995, the
disclosure of which is hereby incorporated by reference in its
entirety. As explained in the '045 patent, nitrogen gas facilitates
the deposition of titanium nitride at temperatures of about
500.degree. C. or lower. Hydrogen gas (H.sub.2) may also be
introduced into the reaction chamber to facilitate the formation of
hydrochloric acid from chlorine.
[0032] Other chemical reactions are also useful for depositing
metal nitride layer 40. U.S. Pat. No. 5,399,379 ("the '379
patent"), issued to Gurtej S. Sandhu on Mar. 21, 1995, the
disclosure of which is hereby incorporated by reference in its
entirety, describes such a reaction, whereby one or more
organometallic compounds of the formula Ti(NR.sub.2).sub.4, which
is also referred to as a tetrakis-dialkylamido-titanium, are
reacted with a halide gas (e.g., F.sub.2, Cl.sub.2, Br.sub.2) to
form a titanium nitride film on a semiconductor device. In each
Ti(NR.sub.2).sub.4 molecule, the titanium atom is single-bonded to
four nitrogen atoms, each of which are also single-bonded to two
carbon-containing radical (R) groups, which include hydrogen atoms
or alkyl groups.
[0033] Another exemplary titanium nitride deposition reaction is
disclosed in U.S. Pat. No. 5,254,499 ("the '499 patent"), issued to
Gurtej S. Sandhu et al. on Oct. 19, 1993, the disclosure of which
is hereby incorporated by reference in its entirety. According to
the '499 patent, a titanium nitride layer may also be deposited by
reacting one or more compounds of the general formula
Ti(NR.sub.2).sub.4, where the titanium atom is bonded to a nitrogen
atom, which is in turn bonded to two hydrogen atoms or a
carbon-containing radical (R), with ammonia (NH.sub.3). The
following United States Patents disclose various other methods for
depositing titanium nitride films, wherein the second reactants are
Ti(NR.sub.2).sub.4 and ammonia: U.S. Pat. No. 5,192,589, issued to
Gurtej S. Sandhu on Mar. 9, 1993; U.S. Pat. No. 5,139,825, issued
to Roy G. Gordon et al. on Aug. 18, 1992; and U.S. Pat. No.
5,089,438, issued to Avishay Katz on Feb. 18, 1992, the disclosures
of each of which are hereby incorporated by reference in their
entirety.
[0034] U.S. Pat. No. 5,246,881, issued to Gurtej S. Sandhu et al.
on Sep. 21, 1993, the disclosure of which is hereby incorporated by
reference in its entirety, discloses another method for depositing
a titanium nitride film, wherein the second reactants are one or
more compounds of the formula Ti(NR.sub.2).sub.4, where the
titanium atom is bonded to the nitrogen atom which is, in turn,
bonded to two hydrogen atoms or a carbon-containing radical (R),
and an activated species which attacks the R-nitrogen bonds of the
Ti(NR.sub.2).sub.4, and which will convert the activated species to
a volatile compound. The activated species include halogens,
ammonia, and hydrogen, and are radiofrequency (RF) activated remote
from the Ti(NR.sub.2).sub.4.
[0035] Another titanium nitride deposition reaction that is useful
in the method of the present invention is disclosed in U.S. Pat.
No. 5,227,334, issued to Gurtej S. Sandhu on Jul. 13, 1993, which
is hereby incorporated by reference in its entirety. The second
reactants of that process include a titanium-containing compound,
such as Ti(NR.sub.2).sub.4, and nitrogen trifluoride
(NF.sub.3).
[0036] Alternatively, metal nitride layer 40 may comprise a mixed
phase layer, such as the TiN/TiSi.sub.x layer deposited by the
method disclosed in U.S. Pat. No. 5,252,518 ("the '518 patent"),
issued to Gurtej S. Sandhu et al. on Oct. 12, 1993, the disclosure
of which is hereby incorporated by reference in its entirety. The
process of the '518 patent includes reacting Ti(NR.sub.2).sub.4,
where the titanium atom is bonded to the nitrogen atom which is, in
turn, bonded to two hydrogen atoms or a carbon-containing radical
(R), with an organic silane reactive gas, such as
tris(dimethylamino) silane (SIN).
[0037] FIG. 6 illustrates the selective removal of metal nitride
layer 40 from the active surface 11 of semiconductor device
structure 10. Known patterning processes, such as mask and etch
techniques, may be employed to selectively remove metal nitride
layer 40 from various regions of semiconductor device structure 10
(e.g., from above the stacked capacitor structures 20 thereof),
while metal nitride layer 40 remains over selective contact 38.
Alternatively, a layer 42 (see FIG. 7) of aluminum may be disposed
over metal nitride layer 40 prior to such patterning.
[0038] With reference to FIG. 7, a layer 42 of aluminum may be
disposed over semiconductor device structure 10 and within trench
22 by known processes, such as PVD (e.g., sputtering, evaporation,
or other PVD processes) or CVD. Aluminum layer 42 may be patterned
by known techniques, such as masking and etching, to define bit
lines 36 (see FIG. 1) therefrom and integral therewith.
Alternatively, the layer 42 of aluminum overlying semiconductor
device structure 10 may be substantially completely removed from
above the stacked capacitor structures 20 thereof by known
techniques, such as etch processes or planarization processes
(e.g., chemical/mechanical planarization (CMP)) that will leave
aluminum interconnect 34 substantially intact.
[0039] Referring to FIG. 8, if aluminum layer 42 is removed from
active surface 11, a bit line 36 comprised of an electrically
conductive material, such as a metal (e.g., tungsten, titanium,
aluminum), an electrically conductive polymer, or polysilicon, may
be fabricated above stacked capacitor structure 20 and in
electrical contact with aluminum interconnect 34. Known metal layer
fabrication processes, such as PVD or CVD processes, may be
employed to deposit a layer of metal from which bit line 36 is to
be defined by known patterning techniques, such as mask and etch
processes.
[0040] Additional structures and layers may then be fabricated over
the active surface 11 of semiconductor device structure 10 by known
processes.
[0041] The semiconductor device structure 10 (see FIG. 1) of the
present invention may have increased speed and lower power
consumption than many state of the art semiconductor devices due to
the use of aluminum, which has a low resistivity, in interconnects
34 and due to the salicide selective contact 38 and the buried
metal diffusion layer 39, each of which may reduce contact
resistance.
[0042] In addition, the aluminum interconnects 34 of semiconductor
device structure 10 of the present invention may also facilitate
further increases in the density of semiconductor device structures
due to the low resistivity of aluminum and, thus, the potentially
thinner interconnects 34 that may be fabricated through the stacked
capacitor structures 20 of such semiconductor devices.
[0043] Although the foregoing description contains many specifics,
these should not be construed as limiting the scope of the present
invention, but merely as providing illustrations of some of the
presently preferred embodiments. Similarly, other embodiments of
the invention may be devised which do not depart from the spirit or
scope of the present invention. Features from different embodiments
may be employed in combination. The scope of the invention is,
therefore, indicated and limited only by the appended claims and
their legal equivalents, rather than by the foregoing description.
All additions, deletions and modifications to the invention as
disclosed herein which fall within the meaning and scope of the
claims are to be embraced thereby.
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