Keller; J. Dennis

Patent Applications and Registrations

Patent applications and USPTO patent grants for Keller; J. Dennis.The latest application filed is for "interconnects including members integral with bit lines, as well as metal nitride and metal silicide, and methods for fabricating interconnects and semiconductor device structures including the interconnects".

Company Profile

0.7.4

Keller; J. Dennis - Boise ID

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods of forming floating gate transistors Grant 7,192,829 - Keller , et al. March 20, 2	2007-03-20
Interconnects including members integral with bit lines, as well as metal nitride and metal silicide, and methods for fabricating interconnects and semiconductor device structures including the interconnects App 20060237821 - Lee; Ruojia ; et al.	2006-10-26
Aluminum interconnects with metal silicide diffusion barriers Grant 7,057,285 - Lee , et al. June 6, 2	2006-06-06
Aluminum interconnects with metal silicide diffusion barriers App 20050023587 - Lee, Ruojia ; et al.	2005-02-03
Semiconductor constructions comprising stacks with floating gates therein Grant 6,791,141 - Keller , et al. September 14, 2	2004-09-14
Aluminum-filled self-aligned trench for stacked capacitor structure and methods Grant 6,787,428 - Lee , et al. September 7, 2	2004-09-07
Aluminum-filled self-aligned trench for stacked capacitor structure and methods Grant 6,720,605 - Lee , et al. April 13, 2	2004-04-13
Aluminum-filled self-aligned trench for stacked capacitor structure and methods App 20020177272 - Lee, Ruojia ; et al.	2002-11-28
Methods Of Enhancing Data Retention Of A Floating Gate Transistor, Methods Of Forming Floating Gate Transistors, And Floating Gate Transistors App 20010021549 - KELLER, J. DENNIS ; et al.	2001-09-13
Method of forming a programmable non-volatile memory cell by providing a shielding layer over the gate sidewalls Grant 5,707,898 - Keller , et al. January 13, 1	1998-01-13
Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors Grant 5,292,681 - Lee , et al. March 8, 1	1994-03-08

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