U.S. patent application number 11/421084 was filed with the patent office on 2006-09-28 for using oxynitride spacer to reduce parasitic capacitance in cmos devices.
This patent application is currently assigned to TEXAS INSTRUMENTS INCORPORATED. Invention is credited to Haowen Bu, Yuanning Chen, Kaiping Liu.
Application Number | 20060216882 11/421084 |
Document ID | / |
Family ID | 36032981 |
Filed Date | 2006-09-28 |
United States Patent
Application |
20060216882 |
Kind Code |
A1 |
Chen; Yuanning ; et
al. |
September 28, 2006 |
Using Oxynitride Spacer to Reduce Parasitic Capacitance in CMOS
Devices
Abstract
A complementary metal oxide semiconductor (CMOS) device has a
substrate 100, a gate structure 108 disposed atop the substrate,
and spacers 250, deposited on opposite sides of the gate structure
108 to govern formation of deep source drain regions S, D in the
substrate. Spacers 250 are formed of an oxynitride
(SiO.sub.xN.sub.yC.sub.z) wherein x and y are non-zero but z may be
zero or greater; such oxynitride spacers reduce parasitic
capacitance, thus improving device performance. A method of
fabricating a portion of a complementary metal oxide semiconductor
(CMOS) device involves providing a substrate 100, forming a gate
structure 108 over the substrate, depositing a first layer 104 atop
the substrate on opposite sides of the gate structure to govern
formation of deep source drain regions in the substrate, depositing
an oxynitride (SiO.sub.xN.sub.yC.sub.z) layer 250 atop the first
layer (in which x and y are non-zero but z may be zero or greater),
depositing a second layer 112 atop the oxynitride layer, and
depositing a nitride layer 114B atop the second layer.
Inventors: |
Chen; Yuanning; (Plano,
TX) ; Bu; Haowen; (Plano, TX) ; Liu;
Kaiping; (Plano, TX) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
US
|
Assignee: |
TEXAS INSTRUMENTS
INCORPORATED
P.O. Box 655474 MS 3999
Dallas
TX
|
Family ID: |
36032981 |
Appl. No.: |
11/421084 |
Filed: |
May 31, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10938179 |
Sep 11, 2004 |
|
|
|
11421084 |
May 31, 2006 |
|
|
|
Current U.S.
Class: |
438/199 ;
257/E21.64; 257/E29.266; 438/786 |
Current CPC
Class: |
H01L 29/66598 20130101;
H01L 29/6656 20130101; H01L 21/823864 20130101; H01L 29/7833
20130101 |
Class at
Publication: |
438/199 ;
438/786 |
International
Class: |
H01L 21/8238 20060101
H01L021/8238; H01L 21/31 20060101 H01L021/31; H01L 21/469 20060101
H01L021/469 |
Claims
1-13. (canceled)
14. A method of fabricating a portion of a complementary metal
oxide semiconductor (CMOS) device, the method comprising: providing
a substrate; forming a gate structure over the substrate;
depositing a first layer atop the substrate on opposite sides of
the gate structure to govern formation of deep source drain regions
in the substrate; depositing an oxynitride
(SiO.sub.xN.sub.yC.sub.z) layer atop the first layer, wherein x and
y are non-zero but z may be zero or greater; depositing a second
layer atop the oxynitride layer; and depositing a nitride layer
atop the second layer.
15. The method of claim 14, wherein: the oxynitride depositing step
is a low pressure chemical vapor deposition (LPCVD) process.
16. The method of claim 15, wherein: the LPCVD process involves gas
mixtures including ammonia and nitrous oxide.
17. The method of claim 14, wherein the oxynitride layer depositing
step includes: depositing a carbon doped oxynitride
(SiO.sub.xN.sub.yC.sub.z) layer, wherein z>0, using an organic
precursors such as bis t-ButylaminoSilane (BTBAS,
C.sub.8H.sub.22N.sub.2Si).
18. The method of claim 14, wherein the oxynitride layer depositing
step includes: forming the oxynitride (SiO.sub.xN.sub.yC.sub.z)
layer with a nitrogen/oxygen ratio that varies as a function of
depth, with less oxygen content near faces of the oxynitride layer
than at a center of the oxynitride layer so that a nitrogen/oxygen
ratio is greatest near the faces of the oxynitride layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates to arrangements for reducing parasitic
capacitance in complementary metal oxide semiconductor (CMOS)
devices (such as C.sub.GD between the gate and the drain or source,
and C.sub.GC between the gate and source/drain contacts). More
specifically, the invention relates to arrangements employing a
sidewall spacer made of oxynitride to reduce parasitic capacitance
and to thus increase the speed of CMOS transistors.
[0003] 2. Related Art
[0004] FIG. 1 shows a conventional CMOS transistor having a source
S and drain D embedded in a substrate 100 which may be made of
silicon. A gate dielectric layer 102 is provided between
symmetrically arranged L-shaped structures 104. A gate 108,
conventionally made of polysilicon, is provided atop the dielectric
layer 102. Structure 110 is a silicide layer and is conventionally
made of cobalt silicide (CoSi) or nickel silicide (NiSi). On
opposite sides of the gate structure 108, a stack is provided that
includes: [0005] a first oxide layer 104 (may also be nitride, or a
combination of oxide and nitride), [0006] followed by a first
nitride layer 114A, [0007] followed by a second oxide layer 112,
[0008] followed by a second nitride layer 114B, which is known as
the contact etch stop layer or pre-metal dielectric (PMD)
liner.
[0009] In the finished device, the second nitride layer 114B
effectively joins with first nitride layer 114A to surround oxide
structure 112. Source and drain contacts (not specifically
illustrated, usually made of metal (tungsten)) are provided atop
outlying portions of the source drain extensions (SDEs) such as by
etching through the top dielectric. The CMOS transistor of FIG. 1
may be fabricated according to well known techniques (such as those
disclosed in, for example, U.S. Pat. Nos. 6,743,705 and 6,677,201
which are incorporated herein by reference).
[0010] Structure 114A has conventionally served the purpose of a
spacer to help define deep source and deep drain regions (S and D,
respectively), which reduces the hot carrier problem and helps to
prevent overrun of source and drain given recent technology
advances. In conventional CMOS devices, the practice and trend has
been to use spacers 114A made of pure nitride.
[0011] However, the dielectric constant of pure nitride (that is,
pure silicon nitride Si.sub.3N.sub.4) is .epsilon.=7.5, and the
nitride spacer causes parasitic capacitance (such as the total gate
to source/drain capacitance C.sub.GD, and gate to source/drain
contact capacitance C.sub.GC) to be undesirably high. Undesirably,
higher parasitic capacitance slows the transistor's operation.
Accordingly, there is a need in the art to provide a spacer that
has the advantages of conventional spacer arrangements but without
having their disadvantages.
SUMMARY
[0012] A complementary metal oxide semiconductor (CMOS) device has
a substrate, a gate structure 108 disposed atop the substrate, and
spacers, deposited on opposite sides of the gate structure to
govern formation of deep source drain regions in the substrate. The
spacers are formed of an oxynitride (SiO.sub.xN.sub.yC.sub.z) in
which x and y are non-zero but z may be zero or greater.
[0013] A method of fabricating a portion of a complementary metal
oxide semiconductor (CMOS) device involves providing a substrate,
forming a gate structure over the substrate, depositing a first
layer atop the substrate on opposite sides of the gate structure to
govern formation of deep source drain regions in the substrate,
depositing an oxynitride (SiO.sub.xN.sub.yC.sub.z) layer atop the
first layer (in which x and y are non-zero but z may be zero or
greater), depositing a second layer atop the oxynitride layer, and
depositing a nitride layer atop the second layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] A more complete appreciation of the described embodiments is
better understood by reference to the following Detailed
Description considered in connection with the accompanying
drawings, in which like reference numerals refer to identical or
corresponding parts throughout, and in which:
[0015] FIG. 1 illustrates a conventional CMOS transistor that
includes a pure nitride spacer 114A that results in a high
parasitic capacitance (C.sub.GD between the gate and source or
drain, and C.sub.GC between gate and source/drain contacts);
[0016] FIG. 2 illustrates on embodiment in which an oxynitride
spacer 250 is provided so as to reduce parasitic capacitance and
thus increase device performance;
[0017] FIGS. 3A, 3B and 3C illustrate structures involved in stages
of a fabrication process that forms the embodiment shown in FIG. 2;
and
[0018] FIG. 4 illustrates the ratio of nitrogen/oxygen (y/x) in a
variable graded composition oxynitride spacer 250.
DETAILED DESCRIPTION
[0019] In describing embodiments illustrated in the drawings,
specific terminology is employed for the sake of clarity. However,
the invention is not intended to be limited to the specific
terminology so selected, and it is to be understood that each
specific element includes all technical equivalents that operate in
a similar manner to accomplish a similar purpose. Various terms
that are used in this specification are to be given their broadest
reasonable interpretation when used in interpreting the claims.
[0020] Moreover, features and procedures whose implementations are
well known to those skilled in the art are omitted for brevity. For
example, design, selection, and implementation of basic electronic
elements and fabrication steps, lies within the ability of those
skilled in the art, and accordingly any detailed discussion thereof
may be omitted.
[0021] The present inventors have recognized that, contrary to the
present trend to use pure nitride spacers 114A in CMOS devices,
spacers made of oxynitride (SiO.sub.xN.sub.y) or carbon doped
oxynitride (SiO.sub.xN.sub.yC.sub.z) reduce parasitic capacitance
and thus increase the operational speed of the CMOS transistors.
Various elements FIG. 2 may be sized, arranged, and composed of
materials similar to those in the conventional CMOS transistor of
FIG. 1, and a description thereof may be omitted. Likewise, a
fabrication method of the FIG. 2 embodiment may incorporate well
known methods employed to form conventional CMOS transistors,
except as specifically noted below with reference to the oxynitride
spacer 250; accordingly, a detailed discussion of conventional
fabrication steps is omitted.
[0022] The FIG. 2 embodiment provides a spacer 250 made of
oxynitride (SiO.sub.xN.sub.y) or carbon doped oxynitride
(SiO.sub.xN.sub.yC.sub.z), not nitride (such as Si.sub.3N.sub.4),
resulting in the aforementioned reduction in parasitic capacitance
and resultant increase in transistor speed. In the illustrated
embodiment, the spacer 250 happens to be of an "L" shape; of
course, it is recognized that the spacer may be shaped other than
as specifically illustrated.
[0023] The structure shown in FIG. 2 may be fabricated in a manner
illustrated in FIGS. 3A, 3B and 3C.
[0024] Referring to FIG. 3A, a gate 108 is shown atop gate
dielectric layer 102 which is atop the substrate 100 in which are
formed source and drain extension (SDE) regions.
[0025] Thereafter, successive layers of a first oxide 104, an
oxynitride 250, and a second oxide 112 are deposited, as shown in
FIG. 3B. Then, the resulting structure is etched along a line E,
removing material above line E to arrive at the structure shown in
FIG. 3C.
[0026] Deep source drain implant is then performed with n-type
dopants (such as arsenic (As) or phosphorus (P)) for nFET devices,
or with p-type dopants (such as boron (B)) for pFET devices. This
results in the deep source drain regions, S, D, respectively, shown
in FIG. 2. The dopants are activated by a rapid thermal annealing
(RTA) process. A CoSi or NiSi layer 110 is deposited atop the
substrate, and a PMD liner nitride layer 114B is deposited atop the
resulting structure, to form the CMOS transistor of FIG. 2.
[0027] Most steps in the process may be carried out in the same
manner in which the conventional CMOS transistor of FIG. 1 is
fabricated, and, accordingly, a detailed description thereof is
omitted. However, this embodiment's fabrication method involves
deposition of oxynitride rather than pure nitride to form spacer
250, and the particular deposition step differs from that of
conventional fabrication methods.
[0028] Oxynitride spacer 250 may be deposited using low pressure
chemical vapor deposition (LPCVD) in which the reactive gases
include: [0029] SiH.sub.4 (silane) or Si.sub.2H.sub.6 (disilane),
[0030] NH.sub.3 (ammonia) and [0031] N.sub.2O (nitrous oxide) or
other oxidants.
[0032] In contrast to the fabrication methods resulting in the
embodiment of FIG. 2, conventional LPCVD silicon nitride
arrangements are not believed to include an oxidant such as nitrous
oxide. But in fabricating the FIG. 2 embodiment, as a result of
using an inert carrier gas such as N.sub.2 (nitrogen) and an
oxidant such as nitrous oxide, the final device includes a spacer,
which may be an L-shaped spacer, that is made of oxynitride
(SiO.sub.xN.sub.y) as distinguished from pure nitride (such as
Si.sub.3N.sub.4).
[0033] An exemplary process is conducted in a rapid thermal
chemical vapor deposition (RTCVD) at 600-700.degree. C.: [0034]
SiH.sub.4 flow is 1-20 sccm (standard centimeter cube per minute),
[0035] NH.sub.3 flow is 1000-4000 sccm, and [0036] N.sub.2O flow is
20-500 sccm.
[0037] Oxynitrides (SiO.sub.xN.sub.y) may be fabricated with
different ratios x/y of oxygen and nitrogen by varying the N.sub.2O
to NH.sub.3 gas flow ratio. Bracketing the oxynitride of which
spacer 250 may be fabricated, are oxides (SiO.sub.2, which has a
dielectric constant .epsilon.=3.9), and pure nitrides
(Si.sub.3N.sub.4, which has a dielectric constant .epsilon.=7.5).
In contrast, oxynitrides may choose an oxygen/nitrogen ratio x/y to
provide a dielectric constant along a continuum between the
extremes of 3.9 and 7.5. In one embodiment to which the invention
should not be limited, in (SiO.sub.xN.sub.y), x and y are chosen so
that x=y=1.
[0038] In simulations in which .epsilon.=4.5, significant
reductions in parasitic capacitance C.sub.GD of from 10 to 17
percent were arrived at, depending on the particular device
configuration. In addition to the advantage of lower parasitic
capacitance and resulting higher transistor switching speed,
oxynitride spacers are easy to form using existing manufacturing
processes. In particular, the process involves a substitution of an
oxynitride (250) deposition step for a conventional nitride (114A)
deposition step. Moreover, oxynitrides normally have lower hydrogen
content. Better boron retention is achieved due to reduced hydrogen
enhance dopant loss, leading to a lower R.sub.SD (source drain
parasitic sheet resistance).
[0039] In another embodiment, an organic precursor (such as bis
t-ButylaminoSilane (BTBAS, C.sub.8H.sub.22N.sub.2Si)) is used
instead of silane or disilane. In this embodiment, the reactive
gases include: [0040] C.sub.8H.sub.22N.sub.2Si (BTBAS) or other
organic precursors, [0041] NH.sub.3 (ammonia) and [0042] N.sub.2O
(nitrous oxide) or other oxidants. In this embodiment, a carbon
doped oxynitride layer (SiO.sub.xN.sub.yC.sub.z) 250 is formed,
with 5-10 atomic percent carbon in the film. The carbon
concentration, however, is tunable over a wide range with process
conditions. With carbon doped oxynitride, further reduction in
parasitic capacitance and dopant loss is achieved.
[0043] In yet another embodiment, instead of a constant composition
throughout the SiO.sub.xN.sub.y or SiO.sub.xN.sub.yC.sub.z layer
250, an oxynitride film with a graded O/N ratio is formed. For
example, oxygen contribution x is approximately 0 at the top and
bottom of the layer 250, so that y/x approaches infinity (extreme
ends of the curve in FIG. 4). Thus, at the top and bottom of
oxynitride layer 250, the film resembles silicon nitride. However,
nitrogen contribution y is approimately 0 at the middle the layer
250 so that the film resembles silicon oxide (the middle of the
curve in FIG. 4). By using a variable composition film for layer
250, etch selectivity is improved at the interfaces between oxide
104 and oxynitride 250, and between oxide 112 and oxynitride 250,
while the overall dielectric constant .epsilon. is kept low.
[0044] The present disclosure supports a complementary metal oxide
semiconductor (CMOS) device that has a substrate (100); a gate
structure (108) disposed atop the substrate; and spacers (250),
deposited on opposite sides of the gate structure (108) to govern
formation of deep source drain regions in the substrate, the
spacers being formed of an oxynitride (SiO.sub.xN.sub.yC.sub.z)
wherein x and y are non-zero but z may be zero or greater.
[0045] The spacers may be substantially "L"-shaped.
[0046] The spacers may be substantially "L"-shaped and may be
sandwiched between two oxide layers (104, 112).
[0047] In addition to the oxynitride, the spacers that govern
formation of the deep source drain regions may further include an
oxide layer (104) deposited between the oxynitride (250) and the
substrate (100), but the spacers do not include an oxide layer
(112) deposited atop the oxynitride (250).
[0048] The spacers may be formed of an oxynitride having a
dielectric constant .epsilon. of about 4.5.
[0049] In the spacers formed of oxynitride
(SiO.sub.xN.sub.yC.sub.z), x and y may be set equal to 1 and y may
be greater than or equal to zero.
[0050] In the spacers formed of oxynitride
(SiO.sub.xN.sub.yC.sub.z), z may be greater than zero to form a
carbon doped oxynitride.
[0051] The device may further have source and drain extension
regions (SDE), embedded in the substrate (100), and formed on
opposite sides of the gate structure (108) and over which
respective spacers (250) are located.
[0052] The spacers (250) formed of oxynitride
(SiO.sub.xN.sub.yC.sub.z) may have a nitrogen/oxygen ratio that
varies as a function of depth, with less oxygen content near faces
of the oxynitride layer than at a center of the oxynitride layer so
that a nitrogen/oxygen ratio is greatest near the faces of the
oxynitride layer.
[0053] The present disclosure also supports a complementary metal
oxide semiconductor (CMOS) transistor. The CMOS transistor may have
a substrate (100); a gate structure (108) located over the
substrate; a first oxide layer (104) atop the substrate on opposite
sides of the gate structure; an oxynitride
(SiO.sub.xN.sub.yC.sub.z) layer (250) atop the first oxide layer,
and deposited on opposite sides of the gate structure (108) to
govern formation of deep source drain regions in the substrate,
wherein x and y are non-zero but z may be zero or greater; a second
oxide layer (112) atop the oxynitride layer; a silicide (110)
disposed on the substrate outwardly from the first oxide layer; and
a nitride layer (114B) atop the second oxide layer (112) and atop
the silicide (110).
[0054] The oxynitride layer (250) may be formed into two "L"-shaped
spacers disposed on opposite sides of the gate structure (108).
[0055] The value of z may be set to be greater than zero to form a
carbon doped oxynitride.
[0056] The oxynitride (SiO.sub.xN.sub.yC.sub.z) layer may have a
nitrogen/oxygen ratio that varies as a function of depth, with less
oxygen content near faces of the oxynitride layer than at a center
of the oxynitride layer so that a nitrogen/oxygen ratio is greatest
near the faces of the oxynitride layer.
[0057] The present disclosure further supports a method of
fabricating a portion of a complementary metal oxide semiconductor
(CMOS) device. The method may involve providing a substrate (100);
forming a gate structure (108) over the substrate; depositing a
first layer (104) atop the substrate on opposite sides of the gate
structure to govern formation of deep source drain regions in the
substrate; depositing an oxynitride (SiO.sub.xN.sub.yC.sub.z) layer
(250) atop the first layer, wherein x and y are non-zero but z may
be zero or greater; depositing a second layer (112) atop the
oxynitride layer; and depositing a nitride layer (114B) atop the
second layer.
[0058] The oxynitride depositing step may be a low pressure
chemical vapor deposition (LPCVD) process.
[0059] The LPCVD process may involve gas mixtures including ammonia
and nitrous oxide.
[0060] The oxynitride layer depositing step may include depositing
a carbon doped oxynitride (SiO.sub.xN.sub.yC.sub.z) layer (250),
wherein z>0, using an organic precursors such as bis
t-ButylaminoSilane (BTBAS, C.sub.8H.sub.22N.sub.2Si).
[0061] The oxynitride layer depositing step may include forming the
oxynitride (SiO.sub.xN.sub.yC.sub.z) layer (250) with a
nitrogen/oxygen ratio that varies as a function of depth, with less
oxygen content near faces of the oxynitride layer than at a center
of the oxynitride layer so that a nitrogen/oxygen ratio is greatest
near the faces of the oxynitride layer.
[0062] Many alternatives, modifications, and variations will be
apparent to those skilled in the art in light of the above
teachings. For example, the particular ratio of oxygen to nitrogen
in the oxynitride, the particular physical dimensions of the device
layers involved, and the particular details of the fabrication
steps chosen, may be varied while still remaining within the scope
of the invention. It is therefore to be understood that within the
scope of the appended claims and their equivalents, the invention
may be practiced otherwise than as specifically described
herein.
* * * * *