U.S. patent application number 11/316505 was filed with the patent office on 2006-05-04 for stacking system and method.
Invention is credited to Jeff Buchle, James W. Cady, Julian Dowden, David L. Roper, James Douglas JR. Wehrly, James Wilder.
Application Number | 20060091521 11/316505 |
Document ID | / |
Family ID | 21716598 |
Filed Date | 2006-05-04 |
United States Patent
Application |
20060091521 |
Kind Code |
A1 |
Cady; James W. ; et
al. |
May 4, 2006 |
Stacking system and method
Abstract
The present invention stacks integrated circuits into modules
that conserve board surface area. In a two-high stack or module
devised in accordance with a preferred embodiment of the present
invention, a pair of integrated circuits is stacked, with one
integrated circuit above the other. The two integrated circuits are
connected with a pair of flexible circuit structures. Each of the
pair of flexible circuit structures is partially wrapped about a
respective opposite lateral edge of the lower integrated circuit of
the module. The flex circuit pair connects the upper and lower
integrated circuits and provides a thermal and electrical path
connection path between the module and an application environment
such as a printed wiring board (PWB). The present invention may be
employed to advantage in numerous configurations and combinations
of integrated circuits in modules provided for high-density
memories or high capacity computing.
Inventors: |
Cady; James W.; (Austin,
TX) ; Wilder; James; (Austin, TX) ; Roper;
David L.; (Austin, TX) ; Wehrly; James Douglas
JR.; (Austin, TX) ; Dowden; Julian; (Austin,
TX) ; Buchle; Jeff; (Austin, TX) |
Correspondence
Address: |
J. SCOTT DENKO
ANDREWS & KURTH LLP
111 CONGRESS AVE., SUITE 1700
AUSTIN
TX
78701
US
|
Family ID: |
21716598 |
Appl. No.: |
11/316505 |
Filed: |
December 21, 2005 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10400309 |
Mar 27, 2003 |
|
|
|
11316505 |
Dec 21, 2005 |
|
|
|
10005581 |
Oct 26, 2001 |
6576992 |
|
|
10400309 |
Mar 27, 2003 |
|
|
|
Current U.S.
Class: |
257/686 ;
257/723; 257/777; 257/E25.023 |
Current CPC
Class: |
H01L 2924/01087
20130101; H01L 23/3114 20130101; H01L 2924/3011 20130101; H01L
2225/06541 20130101; H05K 3/363 20130101; H05K 2201/10689 20130101;
H01L 2924/19041 20130101; H05K 2201/10734 20130101; H01L 23/49816
20130101; H01L 23/49827 20130101; H01L 2225/06586 20130101; H01L
2225/107 20130101; H01L 2224/16237 20130101; H01L 2225/06517
20130101; H01L 25/0657 20130101; H05K 1/189 20130101; H05K 2201/056
20130101; H01L 23/5387 20130101; H01L 2225/06579 20130101; H05K
1/141 20130101; H01L 23/4985 20130101; H05K 1/147 20130101; H01L
25/105 20130101 |
Class at
Publication: |
257/686 ;
257/777; 257/723 |
International
Class: |
H01L 23/48 20060101
H01L023/48 |
Claims
1. A high-density circuit module comprising: a first flex circuit
and a second flex circuit, each comprising a set of first flex
contacts, a set of second flex contacts, a first conductive layer,
a second conductive layer, and an intermediate layer between the
first and second conductive layers; a first CSP having contacts,
the contacts of the first CSP being connected to the first flex
contacts of each of the first and second flex circuits; a second
CSP having contacts, the first CSP being disposed above the second
CSP and the contacts of the second CSP being connected to the
second flex contacts of each of the first and second flex circuits;
and module contacts in contact with the second flex contacts.
2. The high-density module of claim 1 in which for at least the
first flex circuit or the second flex circuit, the first conductive
layer, the intermediate layer, and the second conductive layer are
configured to provide distributed capacitance.
3. The high-density circuit module of claim 1 in which selected
ones of the first flex contacts are connected to selected ones of
the second flex contacts.
4. The high-density circuit module of claim 3 in which selected
ones of the first flex contacts are connected to selected ones of
the second flex contacts with traces.
5. The high-density circuit module of claim 4 in which selected
ones of the traces have substantially equal signal lengths.
6. The high-density circuit module of claim 1 in which at least one
of the contacts of the first CSP and at least one of the contacts
of the second CSP are connected to the first conductive layer of
the first flex circuit.
7. The high-density circuit module of claim 6 in which at least one
of the contacts of the first CSP or at least one of the contacts of
the second CSP is connected to the first conductive layer of the
first flex circuit with an on-pad via.
8. The high-density circuit module of claim 6 in which at least one
of the contacts of the first CSP or at least one of the contacts of
the second CSP is connected to the first conductive layer of the
first flex circuit with an off-pad via.
9. The high-density circuit module of claim 1 in which the first
conductive layer and the second conductive layers of the first flex
circuit and the second flex circuit are metal.
10. The high-density circuit module of claim 9 in which the metal
of the first conductive layer and the second conductive layers is
alloy 110.
11. A module comprising a lower CSP and an upper CSP, each of the
CSPs having a top surface and a bottom surface, and each of the
CSPs having a first lateral side and a second lateral side, the
module comprising: a first flex circuit partially wrapped about the
first lateral side of the lower CSP, the first flex circuit having
a first plurality of upper flex contacts and a first plurality of
lower flex contacts; and a second flex circuit partially wrapped
about the second lateral side of the lower CSP, the second flex
circuit having a second plurality of upper flex contacts and a
second plurality of lower flex contacts, the first plurality of
upper flex contacts and the second plurality of upper flex contacts
configured to connect the first flex circuit and the second flex
circuit, respectively, to the upper CSP, and the first plurality of
lower flex contacts and the second plurality of lower flex contacts
configured to connect the first flex circuit and the second flex
circuit, respectively, to the lower CSP.
12. The module of claim 11 in which the first flex circuit and the
second flex circuit each have an upper conductive layer and a lower
conductive layer, each having at least one electrical path
connecting a selected one of the plurality of upper flex contacts
to a selected one of the plurality of lower flex contacts.
13. The high-density circuit module of claim 12 in which selected
ones of the electrical paths comprise traces having substantially
equal signal lengths.
14. A high-density circuit module comprising: a first CSP having
CSP contacts; a second CSP having CSP contacts and disposed in a
stack with the first CSP; a first flex circuit and a second flex
circuit, each having first and second conductive layers, an
intermediate layer between the first and second conductive layers,
first flex contacts in electrical connection with CSP contacts of
the first CSP, second flex contacts in electrical connection with
CSP contacts of the second CSP, and electrical paths of the first
conductive layer or the second conductive layer, selected ones of
the electrical paths connecting a selected one of the first flex
contacts and a selected one of the second flex contacts; and a
plurality of module contacts connectable to an application
platform, each one of the plurality of module contacts being in
electrical connection to an electrical path of the first flex
circuit, to an electrical path of the second flex circuit, or to
one of the CSP contacts of the first CSP or the second CSP.
15. The high-density circuit module of claim 14 in which at least
one of the first conductive layers comprises a ground plane.
16. The high-density circuit module of claim 14 in which at least
one of the CSP contacts of the first CSP is connected to a first
conductive layer and a plurality of the CSP contacts of the first
CSP are connected to a second conductive layer.
17. The high-density circuit module of claim 14 in which, for at
least the first flex circuit or the second flex circuit, the first
conductive layer, the intermediate layer, and the second conductive
layer are configured to provide distributed capacitance.
18. The high-density circuit module of claim 14 in which, for at
least the first flex circuit or the second flex circuit, the second
conductive layer comprises plural traces each connecting a selected
one of the CSP contacts of the first CSP to a selected one of the
CSP contacts of the second CSP.
19. The high-density circuit module of claim 18 in which selected
ones of the traces have substantially equal signal lengths.
20. The high-density circuit module of claim 18 in which the second
conductive layer further comprises a voltage plane.
21. The high-density circuit module of claim 14 in which thermally
conductive material is disposed between the first CSP and the
second CSP.
22. The high-density circuit module of claim 21 in which the
thermally conductive material is a thermally conductive
adhesive.
23. A high-density circuit module comprising: a first flex circuit
comprising first flex contacts, second flex contacts, a first
conductive layer, a second conductive layer having plural
electrical paths, and an intermediate layer between the first
conductive layer and the second conductive layer; a second flex
circuit comprising first flex contacts and second flex contacts; a
first CSP having contacts, selected contacts of the first CSP being
connected to selected first flex contacts of each of the first and
second flex circuits; a second CSP having contacts, the first CSP
being disposed above the second CSP and selected contacts of the
second CSP being connected to selected second flex contacts of each
of the first and second flex circuits; module contacts; and a
plurality of electrical connections each connecting one of the
contacts of the first CSP to one of the module contacts.
24. The high-density circuit module of claim 23 in which the
plurality of electrical connections comprises at least three
electrical connections, at least one of which transits a portion of
the first conductive layer and at least two of which each transits
the second conductive layer along one of the electrical paths of
the second conductive layer.
25. The high-density circuit module of claim 23 in which the first
conductive layer has a ground plane and the second conductive layer
has a voltage plane.
26. The high-density circuit module of claim 23 in which selected
ones of the electrical paths of the second conductive layer have
substantially equal signal length.
27. The high-density circuit module of claim 26 in which the first
conductive layer has a ground plane and the second conductive layer
has a voltage plane.
28. The high-density circuit module of claim 23 in which thermally
conductive material is disposed between the first CSP and the
second CSP.
29. The high-density circuit module of claim 28 in which the
thermally conductive material is a thermally conductive adhesive.
Description
RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 10/400,309 filed Mar. 27, 2003, which is a continuation of U.S.
application Ser. No. 10/005,581, filed Oct. 26, 2001, now issued as
U.S. Pat. No. 6,576,992, each of which is hereby incorporated by
reference for all purposes.
TECHNICAL FIELD
[0002] The present invention relates to aggregating integrated
circuits and, in particular, to stacking integrated circuits in
chip-scale packages.
BACKGROUND OF THE INVENTION
[0003] A variety of techniques are used to stack packaged
integrated circuits. Some methods require special packages, while
other techniques stack conventional packages. In some stacks, the
leads of the packaged integrated circuits are used to create a
stack, while in other systems, added structures such as rails
provide all or part of the interconnection between packages. In
still other techniques, flexible conductors with certain
characteristics are used to selectively interconnect packaged
integrated circuits.
[0004] The predominant package configuration employed during the
past decade has encapsulated an integrated circuit (IC) in a
plastic surround typically having a rectangular configuration. The
enveloped integrated circuit is connected to the application
environment through leads emergent from the edge periphery of the
plastic encapsulation. Such "leaded packages" have been the
constituent elements most commonly employed by techniques for
stacking packaged integrated circuits.
[0005] Leaded packages play an important role in electronics, but
efforts to miniaturize electronic components and assemblies have
driven development of technologies that preserve circuit board
surface area. Because leaded packages have leads emergent from
peripheral sides of the package, leaded packages occupy more than a
minimal amount of circuit board surface area. Consequently,
alternatives to leaded packages have recently gained market
share.
[0006] One family of alternative packages is identified generally
by the term "chip scale packaging" or CSP. CSP refers generally to
packages that provide connection to an integrated circuit through a
set of contacts (often embodied as "bumps" or "balls") arrayed
across a major surface of the package. Instead of leads emergent
from a peripheral side of the package, contacts are placed on a
major surface and typically emerge from the planar bottom surface
of the package.
[0007] The goal of CSP is to occupy as little area as possible and,
preferably, approximately the area of the encapsulated IC.
Therefore, CSP leads or contacts do not typically extend beyond the
outline perimeter of the package. The absence of "leads" on package
sides renders most stacking techniques devised for leaded packages
inapplicable for CSP stacking.
[0008] CSP has enabled reductions in size and weight parameters for
many applications. For example, micro ball grid array (.mu.BGA) for
flash and SRAM and wirebond on tape or rigid laminate CSPs for SRAM
or EEPROM have been employed in a variety of applications. CSP is a
broad category including a variety of packages from near chip scale
to die-sized packages such as the die sized ball grid array (DSBGA)
recently described in proposed JEDEC standard 95-1 for DSBGA. To
meet the continuing demands for cost and form factor reduction with
increasing memory capacities, CSP technologies that aggregate
integrated circuits in CSP technology have recently been developed.
For example, Sharp, Hitachi, Mitsubishi and Intel recently
undertook support of what are called the S-CSP specifications for
flash and SRAM applications. Those S-CSP specifications describe,
however, stacking multiple die within a single chip scale package
and do not provide a technology for stacking chip scale packages.
Stacking integrated circuits within a single package requires
specialized technology that includes reformulation of package
internals and significant expense with possible supply chain
vulnerabilities.
[0009] There are several known techniques for stacking packages
articulated in chip scale technology. The assignee of the present
invention has developed previous systems for aggregating PBGA
packages in space saving topologies. The assignee of the present
invention has systems for stacking BGA packages on a DIMM in a
RAMBUS environment.
[0010] In U.S. Pat. No. 6,205,654 B1 owned by the assignee of the
present invention, a system for stacking ball grid array packages
that employs lead carriers to extend connectable points out from
the packages is described. Other known techniques add structures to
a stack of BGA-packaged ICs. Still others aggregate CSPs on a DIMM
with angular placement of the packages. Such techniques provide
alternatives, but require topologies of added cost and
complexity.
[0011] U.S. Pat. No. 6,262,895 B1 to Forthun (the "Forthun patent")
purports to disclose a technique for stacking chip scale packaged
ICs. The Forthun patent discloses a "package" that exhibits a flex
circuit wrapped partially about a CSP. The flex circuit is said to
have pad arrays on upper and lower surfaces of the flex.
[0012] The flex circuit of the Forthun "package" has a pad array on
its upper surface and a pad array centrally located upon its lower
surface. On the lower surface of the flex there are third and
fourth arrays on opposite sides from the central lower surface pad
array. To create the package of Forthun, a CSP contacts the pad
array located on the upper surface of the flex circuit. As
described in the Forthun patent, the contacts on the lower surface
of the CSP are pushed through "slits" in the upper surface pads and
advanced through the flex to protrude from the pads of the lower
surface array and, therefore, the bottom surface of the package.
Thus, the contacts of the CSP serve as the contacts for the
package. The sides of the flex are partially wrapped about the CSP
to adjacently place the third and fourth pad arrays above the upper
major surface of the CSP to create from the combination of the
third and fourth pad arrays, a fifth pad array for connection to
another such package. Thus, as described in the Forthun disclosure,
a stacked module of CSPs created with the described packages will
exhibit a flex circuit wrapped about each CSP in the module.
[0013] The previous known methods for stacking CSPs apparently have
various deficiencies including complex structural arrangements and
thermal or high frequency performance issues. Typically, the
reliability of chip scale packaging is closely scrutinized. During
such reliability evaluations, CSP devices often exhibit temperature
cycle performance issues. CSPs are generally directly mounted on a
PWB or other platform offset from the PWB by only the height of the
ball or bump array emergent from the lower surface of the CSP.
Consequently, stresses arising from temperature gradients over time
are concentrated in the short lever arm of a low-height ball array.
The issues associated with temp cycle performance in single CSPs
will likely arise in those prior art CSP stacking solutions where
the stack is offset from the PWB or application platform by only
the height of the lower CSP ball grid array.
[0014] Thermal performance is also a characteristic of importance
in CSP stacks. To increase dissipation of heat generated by
constituent CSPs, the thermal gradient between the lower CSP and
upper CSP in a CSP stack or module should be minimized. Prior art
solutions to CSP stacking do not, however, address thermal gradient
minimization in disclosed constructions.
[0015] What is needed, therefore, is a technique and system for
stacking integrated circuits packaged in chip scale technology
packaging that provides a thermally efficient, reliable structure
that performs well at higher frequencies but does not add excessive
height to the stack yet allows production at reasonable cost with
readily understood and managed materials and methods.
SUMMARY OF THE INVENTION
[0016] The present invention stacks chip scale-packaged integrated
circuits (CSPs) into modules that conserve PWB or other board
surface area. The present invention can be used to advantage with
CSP packages of a variety of sizes and configurations ranging from
typical BGAs with footprints somewhat larger than the contained die
to smaller packages such as, for example, die-sized packages such
as DSBGA. Although the present invention is applied most frequently
to chip scale packages that contain one die, it may be employed
with chip scale packages that include more than one integrated
circuit die.
[0017] In a two-high CSP stack or module devised in accordance with
a preferred embodiment of the present invention, two CSPs are
stacked, with one CSP disposed above the other. The two CSPs are
connected with a pair of flex circuits. Each of the pair of flex
circuits is partially wrapped about a respective opposite lateral
edge of the lower CSP of the module. The flex circuit pair connects
the upper and lower CSPs and provides a thermal and electrical path
connection path between the module and an application environment
such as a printed wiring board (PWB).
[0018] The present invention may be employed to advantage in
numerous configurations and combinations of CSPs in modules
provided for high-density memories or high capacity computing.
SUMMARY OF THE DRAWINGS
[0019] FIG. 1 is an elevation view of module 10 devised in
accordance with a preferred embodiment of the present
invention.
[0020] FIG. 2 is an elevation view of module 10 devised in
accordance with a preferred embodiment of the present
invention.
[0021] FIG. 3 depicts, in enlarged view, the area marked "A" in
FIG. 2.
[0022] FIG. 4 is an enlarged detail of an exemplar connection in a
preferred embodiment of the present invention.
[0023] FIG. 5 is an enlarged depiction of an exemplar area around a
lower flex contact in a preferred embodiment of the present
invention.
[0024] FIG. 6 depicts a first outer surface layer of a flex circuit
employed in a preferred embodiment of the present invention.
[0025] FIG. 7 depicts a first outer surface layer of a flex circuit
employed in a preferred embodiment of the present invention.
[0026] FIG. 8 depicts a first conductive layer of a flex circuit
employed in a preferred embodiment of the present invention.
[0027] FIG. 9 illustrates a first conductive layer of a flex
circuit employed in a preferred embodiment of the present
invention.
[0028] FIG. 10 depicts an intermediate layer of a flex circuit
employed in a preferred embodiment of the present invention.
[0029] FIG. 11 depicts an intermediate layer of a right side flex
circuit employed in a preferred embodiment of the present
invention.
[0030] FIG. 12 depicts a second conductive layer of a flex circuit
of a preferred embodiment of the present invention.
[0031] FIG. 13 depicts a second conductive layer of a flex circuit
of a preferred embodiment of the present invention.
[0032] FIG. 14 depicts a second outer layer of a flex circuit
employed in a preferred embodiment of the present invention.
[0033] FIG. 15 reflects a second outer layer of a flex circuit
employed in a preferred embodiment of the present invention.
[0034] FIG. 16 depicts an alternative preferred embodiment of the
present invention.
[0035] FIG. 17 illustrates a JEDEC pinout for DDR-II FBGA
packages.
[0036] FIG. 18 illustrates the pinout of a module 10 in an
alternative preferred embodiment of the invention.
[0037] FIG. 19 illustrates the pinout of a module 10 in an
alternative embodiment of the invention.
[0038] FIG. 20 depicts the pinout of an exemplar CSP employed in a
preferred embodiment of the invention.
[0039] FIG. 21 depicts a second conductive layer of a flex circuit
employed in an alternative preferred embodiment of the present
invention.
[0040] FIG. 22 depicts a second conductive layer of a flex circuit
employed in an alternative preferred embodiment of the present
invention.
DESCRIPTION OF PREFERRED EMBODIMENTS
[0041] FIG. 1 is an elevation view of module 10 devised in
accordance with a preferred embodiment of the present invention.
Module 10 is comprised of upper CSP 12 and lower CSP 14. Each of
CSPs 12 and 14 have an upper surface 16 and a lower surface 18 and
opposite lateral sides 20 and 22.
[0042] The invention is used with CSP packages of a variety of
types and configurations such as, for example, those that are
die-sized, as well those that are near chip-scale as well as the
variety of ball grid array packages known in the art. Collectively,
these will be known herein as chip scale packaged integrated
circuits (CSPs) and preferred embodiments will be described in
terms of CSPs, but the particular configurations used in the
explanatory figures are not, however, to be construed as limiting.
For example, the elevation views of FIGS. 1 and 2 are depicted with
CSPs of a particular profile known to those in the art, but it
should be understood that the figures are exemplary only. Later
figures show embodiments of the invention that employ CSPs of other
configurations as an example of one other of the many alternative
CSP configurations with which the invention may be employed. The
invention may be employed to advantage in the wide range of CSP
configurations available in the art where an array of connective
elements is emergent from at least one major surface. The invention
is advantageously employed with CSPs that contain memory circuits
but may be employed to advantage with logic and computing circuits
where added capacity without commensurate PWB or other board
surface area consumption is desired.
[0043] Typical CSPs, such as, for example, ball-grid-array ("BGA"),
micro-ball-grid array (".mu.BGA"), and fine-pitch ball grid array
("FBGA") packages have an array of connective contacts embodied,
for example, as leads, bumps, solder balls, or balls that extend
from lower surface 18 of a plastic casing in any of several
patterns and pitches. An external portion of the connective
contacts is often finished with a ball of solder. Shown in FIG. 1
are CSP contacts 24 along lower surfaces 18 of CSPs 12 and 14. CSP
contacts 24 provide connection to the integrated circuit within the
respective packages. Collectively, CSP contacts 24 comprise CSP
array 26 shown as to lower CSP 14 in the depicted particular
package configuration as CSP arrays 26.sub.1 and 26.sub.2 which
collectively comprise CSP array 26.
[0044] In FIG. 1, flex circuits ("flex", "flex circuits" or
"flexible circuit structures") 30 and 32 are shown partially
wrapped about lower CSP 14 with flex 30 partially wrapped over
lateral side 20 of lower CSP 14 and flex 32 partially wrapped about
lateral side 22 of lower CSP 14. Lateral sides 20 and 22 may be in
the character of sides or may, if the CSP is especially thin, be in
the character of an edge. Any flexible or conformable substrate
with a multiple internal layer connectivity capability may be used
as a flex circuit in the invention. The entire flex circuit may be
flexible or, as those of skill in the art will recognize, a PCB
structure made flexible in certain areas to allow conformability
around lower CSP 14 and rigid in other areas for planarity along
CSP surfaces may be employed as an alternative flex circuit in the
present invention. For example, structures known as rigid-flex may
be employed.
[0045] Portions of flex circuits 30 and 32 are fixed to upper
surface 16 of lower CSP 14 by adhesive 34 which is shown as a tape
adhesive, but may be a liquid adhesive or may be placed in discrete
locations across the package. Preferably, adhesive 34 is thermally
conductive. Adhesives that include a flux are used to advantage in
assembly of module 10. Layer 34 may also be a thermally conductive
medium to encourage heat flow between the CSPs of module 10.
[0046] Flex circuits 30 and 32 are multi-layer flexible circuit
structures that have at least two conductive layers. Preferably,
the conductive layers are metal such as alloy 110. The use of
plural conductive layers provides advantages as will be seen and
the creation of a distributed capacitance across module 10 intended
to reduce noise or bounce effects that can, particularly at higher
frequencies, degrade signal integrity, as those of skill in the art
will recognize. Module 10 of FIG. 1 has module contacts 36
collectively identified as module array 38.
[0047] FIG. 2 shows a module 10 devised in accordance with a
preferred embodiment of the invention. FIG. 2 illustrates use of a
conformal media 40 provided in a preferred embodiment to assist in
creating conformality of structural areas of module 10. Planarity
of the module is improved by conformal media 40. Preferably,
conformal media 40 is thermally conductive. In alternative
embodiments, thermal spreaders or a thermal medium may be placed as
shown by reference 41. Identified in FIG. 2 are upper flex contacts
42 and lower flex contacts 44 that are at one of the conductive
layers of flex circuits 30 and 32. Upper flex contacts 42 and lower
flex contacts 44 are conductive material and, preferably, are solid
metal. Lower flex contacts 44 are collectively lower flex contact
array 46. Upper flex contacts 42 are collectively upper flex
contact array 48. Only some of upper flex contacts 42 and lower
flex contacts 44 are identified in FIG. 2 to preserve clarity of
the view. It should be understood that each of flex circuits 30 and
32 have both upper flex contacts 42 and lower flex contacts 44.
Lower flex contacts 44 are employed with lower CSP 14 and upper
flex contacts 42 are employed with upper CSP 12. FIG. 2 has an area
marked "A" that is subsequently shown in enlarged depiction in FIG.
3.
[0048] FIG. 3 depicts in enlarged view, the area marked "A" in FIG.
2. FIG. 3 illustrates the connection between example CSP contact 24
and module contact 36 through lower flex contact 44 to illustrate
the solid metal path from lower CSP 14 to module contact 36 and,
therefore, to an application PWB to which module is connectable. As
those of skill in the art will understand, heat transference from
module 10 is thereby encouraged.
[0049] With continuing reference to FIG. 3, CSP contact 24 and
module contact 36 together offset module 10 from an application
platform such as a PWB. The combined heights of CSP contact 24 and
module contact 36 provide a moment arm longer than the height of a
single CSP contact 24 alone. This provides a longer moment arm
through which temperature-gradient-over-time stresses (such as
typified by temp cycle), can be distributed.
[0050] Flex 30 is shown in FIG. 3 to be comprised of multiple
layers. Flex 30 has a first outer surface 50 and a second outer
surface 52. Flex circuit 30 has at least two conductive layers
interior to first and second outer surfaces 50 and 52. There may be
more than two conductive layers in flex 30 and flex 32. In the
depicted preferred embodiment, first conductive layer 54 and second
conductive layer 58 are interior to first and second outer surfaces
50 and 52. Intermediate layer 56 lies between first conductive
layer 54 and second conductive layer 58. There may be more than one
intermediate layer, but one intermediate layer of polyimide is
preferred.
[0051] As depicted in FIG. 3 and seen in more detail in later
figures, lower flex contact 44 is preferably comprised from metal
at the level of second conductive layer 58 interior to second outer
surface 52. Lower flex contact 44 is solid metal in a preferred
embodiment and is comprised of metal alloy such as alloy 110. This
results in a solid metal pathway from lower CSP 14 to an
application board thereby providing a significant thermal pathway
for dissipation of heat generated in module 10.
[0052] FIG. 4 is an enlarged detail of an exemplar connection
between example CSP contact 24 and example module contact 36
through lower flex contact 44 to illustrate the solid metal path
from lower CSP 14 to module contact 36 and, therefore, to an
application PWB to which module 10 is connectable. As shown in FIG.
4, lower flex contact 44 is at second conductive layer 58 that is
interior to first and second outer surface layers 50 and 52
respectively, of flex circuit 30.
[0053] FIG. 5 is an enlarged depiction of an exemplar area around a
lower flex contact 44 in a preferred embodiment. Windows 60 and 62
are opened in first and second outer surface layers 50 and 52
respectively, to provide access to particular lower flex contacts
44 residing at the level of second conductive layer 58 in the flex.
The upper flex contacts 42 are contacted by CSP contacts 24 of
upper CSP 12. Lower flex contacts 44 and upper flex contacts 42 are
particular areas of conductive material (preferably metal such as
alloy 110) at the level of second conductive layer 58 in the flex.
Upper flex contacts 42 and lower flex contacts 44 are demarked in
second conductive layer 58 and, as will be shown in subsequent
Figs., may be connected to or isolated from the conductive plane of
second conductive layer 58. Demarking a lower flex contact 44 from
second conductive layer 58 is represented in FIG. 5 by demarcation
gap 63 shown at second conductive layer 58. Where an upper or lower
flex contact 42 or 44 is not completely isolated from second
conductive layer 58, demarcation gaps do not extend completely
around the flex contact as shown, for example, by lower flex
contacts 44C in later FIG. 12. CSP contacts 24 of lower CSP 14 pass
through a window 60 opened through first outer surface layer 50,
first conductive layer 54, and intermediate layer 56, to contact an
appropriate lower flex contact 44. Window 62 is opened through
second outer surface layer 52 through which module contacts 36 pass
to contact the appropriate lower flex contact 44.
[0054] Respective ones of CSP contacts 24 of upper CSP 12 and lower
CSP 14 are connected at the second conductive layer 58 level in
flex circuits 30 and 32 to interconnect appropriate signal and
voltage contacts of the two CSPs. Respective CSP contacts 24 of
upper CSP 12 and lower CSP 14 that convey ground (VSS) signals are
connected at the first conductive layer 54 level in flex circuits
30 and 32 by vias that pass through intermediate layer 56 to
connect the levels as will subsequently be described in further
detail. Thereby, CSPs 12 and 14 are connected. Consequently, when
flex circuits 30 and 32 are in place about lower CSP 14, respective
CSP contacts 24 of each of upper and lower CSPs 12 and 14 are in
contact with upper and lower flex contacts 42 and 44, respectively.
Selected ones of upper flex contacts 42 and lower flex contacts 44
are connected. Consequently, by being in contact with lower flex
contacts 44, module contacts 36 are in contact with both upper and
lower CSPs 12 and 14.
[0055] In a preferred embodiment, module contacts 36 pass through
windows 62 opened in second outer layer 52 to contact lower CSP
contacts 44. In some embodiments, as will be later shown, module 10
will exhibit a module contact array 38 that has a greater number of
contacts than do the constituent CSPs of module 10. In such
embodiments, some of module contacts 36 may contact lower flex
contacts 44 that do not contact one of the CSP contacts 24 of lower
CSP 14 but are connected to CSP contacts 24 of upper CSP 12. This
allows module 10 to express a wider datapath than that expressed by
the constituent CSPs 12 or 14. A module contact 36 may also be in
contact with a lower flex contact 44 to provide a location through
which different levels of CSPs in the module may be enabled when no
unused CSP contacts are available or convenient for that
purpose.
[0056] In a preferred embodiment, first conductive layer 54 is
employed as a ground plane, while second conductive layer 58
provides the functions of being a signal conduction layer and a
voltage conduction layer. Those of skill will note that roles of
the first and second conductive layers may be reversed with
attendant changes in windowing and use of commensurate
interconnections.
[0057] As those of skill will recognize, interconnection of
respective voltage CSP contacts 24 of upper and lower CSPs 12 and
14 will provide a thermal path between upper and lower CSPs to
assist in moderation of thermal gradients through module 10. Such
flattening of the thermal gradient curve across module 10 is
further encouraged by connection of common ground CSP contacts 24
of upper and lower CSPs 12 and 14 through first conductive layer
54. Those of skill will notice that between first and second
conductive layers 54 and 58 there is at least one intermediate
layer 56 that, in a preferred embodiment, is a polyimide. Placement
of such an intermediate layer between ground-conductive first
conductive layer 54 and signal/voltage conductive second conductive
layer 58 provides, in the combination, a distributed capacitance
that assists in mitigation of ground bounce phenomena to improve
high frequency performance of module 10.
[0058] In a preferred embodiment, FIG. 6 depicts first outer
surface layer 50 of flex 30 (i.e., left side of FIG. 1). The view
is from above the flex looking down into flex 30 from the
perspective of first conductive layer 54. Throughout the Figs., the
location reference "B" is to orient views of layers of flex 30 to
those of flex 32 as well as across layers. Windows 60 are opened
through first outer surface layer 50, first conductive layer 54,
and intermediate layer 56. CSP contacts 24 of lower CSP 14 pass
through windows 60 of first outer surface layer 50, first
conductive layer 54, and intermediate layer 56 to reach the level
of second conductive layer 58 of flex 30. At second conductive
layer 58, selected CSP contacts 24 of lower CSP 14 make contact
with selected lower flex contacts 44. Lower flex contacts 44
provide several types of connection in a preferred embodiment as
will be explained with reference to later FIG. 12. When module 10
is assembled, a portion of flex 30 will be wrapped about lateral
side 20 of lower CSP 14 to place edge 62 above upper surface 16 of
lower CSP 14.
[0059] In a preferred embodiment, FIG. 7 depicts first outer
surface layer 50 of flex 32 (i.e., right side of FIG. 1). The view
is from above the flex looking down into flex 32 from the
perspective of first conductive layer 54. The location reference
"B" relatively orients the views of FIGS. 6 and 7. The views of
FIGS. 6 and 7 may be understood together with the reference marks
"B" of each view being placed nearer each other than to any other
corner of the other view of the pair of views of the same layer. As
shown in FIG. 7, windows 60 are opened through first outer surface
layer 50, first conductive layer 54 and intermediate layer 56. CSP
contacts 24 of lower CSP 14 pass through windows 60 of first outer
surface layer 50, first conductive layer 54, and intermediate layer
56 to reach the level of second conductive layer 58 of flex 30. At
second conductive layer 58, selected CSP contacts 24 of lower CSP
14 make contact with lower flex contacts 44. Lower flex contacts 44
provide several types of connection in a preferred embodiment as
will be explained with reference to later FIG. 12. When module 10
is assembled, a portion of flex 32 will be wrapped about lateral
side 22 of lower CSP 14 to place edge 64 above upper surface 16 of
lower CSP 14.
[0060] FIG. 8 depicts first conductive layer 54 of flex 30. Windows
60 continue the opened orifice in flex 30 through which CSP
contacts 24 of lower CSP 14 pass to reach second conductive layer
58 and, therefore, selected lower flex contacts 44 at the level of
second conductive layer 58.
[0061] Those of skill will recognize that as flex 30 is partially
wrapped about lateral side 20 of lower CSP 14, first conductive
layer 54 becomes, on the part of flex 30 disposed above upper
surface 16 of lower CSP 14, the lower-most conductive layer of flex
30 from the perspective of upper CSP 12. In the depicted
embodiment, those CSP contacts 24 of upper CSP 12 that provide
ground (VSS) connections are connected to the first conductive
layer 54. First conductive layer 54 lies beneath, however, second
conductive layer 58 in that part of flex 30 that is wrapped above
lower CSP 14. Consequently, some means must be provided for
connection of the upper flex contact 42 to which ground-conveying
CSP contacts 24 of upper CSP 12 are connected and first conductive
layer 54. Consequently, in the depicted preferred embodiment, those
upper flex contacts 42 that are in contact with ground-conveying
CSP contacts 24 of upper CSP 12 have vias that route through
intermediate layer 56 to reach first conductive layer 54. The sites
where those vias meet first conductive layer 54 are identified in
FIG. 8 as vias 66. These vias may be "on-pad" or coincident with
the flex contact 42 to which they are connected. Those of skill
will note a match between the vias 66 identified in FIG. 8 and vias
66 identified in the later view of second conductive layer 58 of
the depicted preferred embodiment. In a preferred embodiment, vias
66 in coincident locations from Fig. to Fig. are one via. For
clarity of the view, depicted vias in the figures are shown larger
in diameter than in manufactured embodiments. As those of skill
will recognize, the connection between conductive layers provided
by vias (on or off pad) may be provided any of several well-known
techniques such as plated holes or solid lines or wires and need
not literally be vias.
[0062] Also shown in FIG. 8 are off-pad vias 74. Off-pad vias 74
are disposed on first conductive layer 54 at locations near, but
not coincident with selected ones of windows 60. Unlike vias 66
that connect selected ones of upper flex contacts 42 to first
conductive layer 54, off-pad vias 74 connect selected ones of lower
flex contacts 44 to first conductive layer 54. In the vicinity of
upper flex contacts 42, second conductive layer 58 is between the
CSP connected to module 10 by the upper flex contacts 42 (i.e.,
upper CSP 12) and first conductive layer 54. Consequently, vias
between ground-conveying upper flex contacts 42 and first
conductive layer 54 may be directly attached to the selected upper
flex contacts 42 through which ground signals are conveyed. In
contrast, in the vicinity of lower flex contacts 44, first
conductive layer 54 is between the CSP connected to module 10 by
the lower flex contacts 44 (i.e., lower CSP 14) and second
conductive layer 58. Consequently, vias between ground-conveying
lower flex contacts 44 and first conductive layer 54 are offset
from the selected lower flex contacts 44 by off-pad vias 74 shown
in offset locations.
[0063] FIG. 9 illustrates first conductive layer 54 of flex 32. The
location reference marks "B" are employed to relatively orient
FIGS. 8 and 9. Windows 60, vias 66 and off-pad vias 74 are
identified in FIG. 9. Also shown in FIG. 9, are enable vias 68 and
70 and enable trace 72. Enable via 70 is connected off-pad to a
selected lower flex contact 44 that corresponds, in this preferred
embodiment, to an unused CSP contact 24 of lower CSP 14 (i.e., a
N/C). A module contact 36 at that site conveys an enable signal
(C/S) for upper CSP 12 through the selected lower flex contact 44
(which is at the level of second conductive layer 58) to off-pad
enable via 70 that conveys the enable signal to first conductive
layer 54 and thereby to enable trace 72. Enable trace 72 further
conveys the enable signal to enable via 68 which extends through
intermediate layer 56 to selected upper flex contact 42 at the
level of second conductive layer 58 where contact is made with the
C/S pin of upper CSP 12. Thus, upper and lower CSPs 12 and 14 may
be independently enabled.
[0064] FIG. 10 depicts intermediate layer 56 of flex 30. Windows 60
are shown opened in intermediate surface 56. CSP contacts 24 of
lower CSP 14 pass through windows 60 in intermediate layer 58 to
reach lower flex contacts 44 at the level of second conductive
layer 58. Those of skill will notice that, in the depicted
preferred embodiment, windows 60 narrow in diameter from their
manifestation in first outer layer 50. Vias 66, off-pad vias 74,
and enable vias 68 and 70 pass through intermediate layer 56
connecting selected conductive areas at the level of first and
second conductive layers 54 and 58, respectively. FIG. 11 depicts
intermediate layer 56 of flex 32 showing windows 60, vias 66,
off-pad vias 74, and enable vias 68 and 70 passing through
intermediate layer 56.
[0065] FIG. 12 depicts second conductive layer 58 of flex 30 of a
preferred embodiment of the present invention. Depicted are various
types of upper flex contacts 42, various types of lower flex
contacts 44, signal traces 76, and VDD plane 78 as well as
previously described vias 66 and off-pad vias 74. Throughout FIGS.
12 and 13, only exemplars of particular features are identified to
preserve clarity of the view. Flex contacts 44A are connected to
corresponding selected upper flex contacts 42A with signal traces
76. To enhance the clarity of the view, only exemplar individual
flex contacts 44A and 42A are literally identified in FIG. 12. As
shown, in this preferred embodiment, signal traces 76 exhibit path
routes determined to provide substantially equal signal lengths
between corresponding flex contacts 42A and 44A. As shown, traces
76 are separated from the larger surface area of second conductive
layer 58 that is identified as VDD plane 78. VDD plane 78 may be in
one or more delineated sections but, preferably is one section.
Lower flex contacts 44C provide connection to VDD plane 78. In a
preferred embodiment, upper flex contacts 42C and lower flex
contacts 44C connect upper CSP 12 and lower CSP 14, respectively,
to VDD plane 78. Lower flex contacts 44 that are connected to first
conductive layer 54 by off-pad vias 74 are identified as lower flex
contacts 44B. To enhance the clarity of the view, only exemplar
individual lower flex contacts 44B are literally identified in FIG.
12. Upper flex contacts 42 that are connected to first conductive
layer 54 by vias 66 are identified as upper flex contacts 42B.
[0066] FIG. 13 depicts second conductive layer 58 of right side
flex 32 of a preferred embodiment of the present invention.
Depicted are various types of upper flex contacts 42, various types
of lower flex contacts 44, signal traces 76, and VDD plane 78 as
well as previously described vias 66, off-pad vias 74, and enable
vias 70 and 68. FIG. 13 illustrates upper flex contacts 42A
connected by traces 76 to lower flex contacts 44A. VDD plane 78
provides a voltage plane at the level of second conductive layer
58. Lower flex contacts 44C and upper flex contacts 42C connect
lower CSP 14 and upper CSP 12, respectively, to VDD plane 78. Lower
flex contact 44D is shown with enable via 70 described earlier.
Corresponding upper flex contact 42D is connected to lower flex
contact 44D through enable vias 70 and 68 that are connected to
each other through earlier described enable trace 72 at the first
conductive layer 54 level of flex 32.
[0067] FIG. 14 depicts second outer layer 52 of flex 30. Windows 62
are identified. Those of skill will recognize that module contacts
36 pass through windows 62 to contact appropriate lower flex
contacts 44. When flex 30 is partially wrapped about lateral side
20 of lower CSP 14, a portion of second outer layer 52 becomes the
upper-most layer of flex 30 from the perspective of upper CSP 12.
CSP contacts 24 of upper CSP 12 pass through windows 64 to reach
second conductive layer 58 and make contact with appropriate ones
of upper flex contacts 42 located at that level. FIG. 15 reflects
second outer layer 52 of flex 32 and exhibits windows 64 and 62.
Module contacts 36 pass through windows 62 to contact appropriate
lower flex contacts 44. CSP contacts 24 of upper CSP 12 pass
through windows 64 to reach second conductive layer 58 and make
contact with appropriate ones of upper flex contacts 42 located at
that level.
[0068] FIG. 16 depicts an alternative preferred embodiment of the
present invention showing module 10. Those of skill will recognize
that the embodiment depicted in FIG. 16 differs from that in FIG. 2
by the presence of module contacts 36E. Module contacts 36E supply
a part of the datapath of module 10 and may provide a facility for
differential enablement of the constituent CSPs. A module contact
36E not employed in wide datapath provision may provide a contact
point to supply an enable signal to differentially enable upper CSP
12 or lower CSP 14.
[0069] In a wide datapath module 10, the data paths of the
constituent upper CSP 12 and lower CSP 14 are combined to provide a
module 10 that expresses a module datapath that is twice the width
of the datapaths of the constituent CSPs in a two-high module 10.
The preferred method of combination is concatenation, but other
combinations may be employed to combine the datapaths of CSPs 12
and 14 on the array of module contacts 36 and 36E.
[0070] As an example, FIGS. 17, 18, and 19 are provided to
illustrate using added module contacts 36E in alternative
embodiments of the present invention to provide wider datapaths for
module 10 than are present in constituent CSPs 12 and 14. FIG. 17
illustrates a JEDEC pinout for DDR-II FBGA packages. FIG. 18
illustrates the pinout provided by module contacts 36 and 36E of a
module 10 expressing an 8-bit wide datapath. Module 10 is devised
in accordance with the present invention and is, in the exemplar
embodiment, comprised of an upper CSP 12 and lower CSP 14 that are
DDR-II-compliant in timing, but each of which are only 4 bits wide
in datapath. As will be recognized, the module 10 mapped in FIG. 18
expresses an 8-bit wide datapath. For example, FIG. 18 depicts DQ
pins differentiated in source between upper CSP 12 ("top") and
lower CSP 14 ("bot") to aggregate to 8-bits. FIG. 19 illustrates
the pinout provided by module contacts 36 and 36E of module 10
expressing a 16-bit wide datapath. Module 10 is devised in
accordance with the present invention and is, in this exemplar
embodiment, comprised of an upper CSP 12 and lower CSP 14 that are
DDR-II-compliant in timing, but each of which are only 8-bits wide
in datapath. Those of skill in the art will recognize that the wide
datapath embodiment may be employed with any of a variety of CSPs
available in the field and such CSPs need not be DDR compliant.
[0071] FIG. 20 illustrates a typical pinout of a memory circuit
provided as a CSP and useable in the present invention. Individual
array positions are identified by the JEDEC convention of numbered
columns and alphabetic rows. The central area (e.g., A3-A6; B3-B6;
etc.) is unpopulated. CSP contacts 24 are present at the locations
that are identified by alpha-numeric identifiers such as, for
example, A3, shown as an example CSP contact 24. FIG. 21 depicts
second metal layer 58 of flex 30 in an alternative embodiment of
the invention in which module 10 expresses a datapath wider than
that expressed by either of the constituent CSPs 12 and 14. Lower
flex contacts 44E are not contacted by CSP contacts 24 of lower CSP
14, but are contacted by module contacts 36E to provide, with
selected module contacts 36, a datapath for module 10 that is
2n-bits in width where the datapaths of CSPs 12 and 14 have a width
of n-bits. As shown in FIG. 21, lower flex contacts 44E are
connected to upper flex contacts 42E. As shown in earlier FIG. 14,
windows 62 pass through second outer layer 52. In the alternative
preferred embodiment for which second conductive layer 58 is shown
in FIG. 21, module contacts 36 and 36E pass through windows 62 in
second outer layer 52 of flex circuit 30, to contact appropriate
lower flex contacts 44.
[0072] FIG. 22 illustrates second metal layer 58 of flex 32 in an
alternative embodiment of the invention in which module 10
expresses a datapath wider than that expressed by either of the
constituent CSPs 12 and 14. Lower flex contacts 44E are not
contacted by CSP contacts 24 of lower CSP 14, but are contacted by
module contacts 36E to provide, with selected module contacts 36, a
datapath for module 10 that is 2n-bits in width where the datapaths
of CSPs 12 and 14 have a width of n-bits. As shown in FIG. 22,
lower flex contacts 44E are connected to upper flex contacts 42E.
As shown in earlier FIG. 14, windows 62 pass through second outer
layer 52. In the alternative preferred embodiment for which second
conductive layer 58 is shown in FIG. 22, module contacts 36 pass
through windows 62 in second outer layer 52 of flex circuit 32, to
contact appropriate lower flex contacts 44.
[0073] In particular, in the embodiment depicted in FIGS. 21 and
22, module contacts 36E contact flex contacts 44E and 44EE. Those
of skill will recognize that lower flex contacts 44E are, in the
depicted embodiment, eight (8) in number and that there is another
lower flex contacts identified by reference 44EE shown on FIG. 21.
Lower flex contact 44EE is contacted by one of the module contacts
36E to provide differential enablement between upper and lower
CSPs. Those of skill will recognize that lower flex contacts 44E
are connected to corresponding upper flex contacts 42E. CSP
contacts 24 of upper CSP 12 that convey data are in contact with
upper flex contacts 42E. Consequently, the datapaths of both upper
CSP 12 and lower CSP 14 are combined to provide a wide datapath on
module 10. With the depicted connections of FIGS. 21 and 22, lower
flex contacts 44E of flex circuits 30 and 32 convey to module
contacts 36E, the datapath of upper CSP 12, while other lower flex
contacts 44 convey the datapath of lower CSP 14 to module contacts
36 to provide module 10 with a module datapath that is the
combination of the datapath of upper CSP 12 and lower CSP 14. In
the depicted particular embodiment of FIGS. 21 and 22, module 10
expresses a 16-bit datapath and CSP 12 and CSP 14 each express an
8-bit datapath.
[0074] Although the present invention has been described in detail,
it will be apparent to those skilled in the art that the invention
may be embodied in a variety of specific forms and that various
changes, substitutions and alterations can be made without
departing from the spirit and scope of the invention. The described
embodiments are only illustrative and not restrictive and the scope
of the invention is, therefore, indicated by the following
claims.
* * * * *